2 * MPC8260 FCC Fast Ethernet
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * SPDX-License-Identifier: GPL-2.0+
13 * MPC8260 FCC Fast Ethernet
14 * Basic ET HW initialization and packet RX/TX routines
16 * This code will not perform the IO port configuration. This should be
17 * done in the iop_conf_t structure specific for the board.
20 * add a PHY driver to do the negotiation
21 * reflect negotiation results in FPSMR
22 * look for ways to configure the board specific stuff elsewhere, eg.
23 * config_xxx.h or the board directory
29 #include <asm/cpm_8260.h>
35 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
39 DECLARE_GLOBAL_DATA_PTR;
41 #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
43 static struct ether_fcc_info_s
47 ulong cpm_cr_enet_sblock;
48 ulong cpm_cr_enet_page;
54 #ifdef CONFIG_ETHER_ON_FCC1
60 CONFIG_SYS_CMXFCR_MASK1,
61 CONFIG_SYS_CMXFCR_VALUE1
65 #ifdef CONFIG_ETHER_ON_FCC2
71 CONFIG_SYS_CMXFCR_MASK2,
72 CONFIG_SYS_CMXFCR_VALUE2
76 #ifdef CONFIG_ETHER_ON_FCC3
82 CONFIG_SYS_CMXFCR_MASK3,
83 CONFIG_SYS_CMXFCR_VALUE3
88 /*---------------------------------------------------------------------*/
90 /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
91 #define PKT_MAXDMA_SIZE 1520
93 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
94 #define PKT_MAXBUF_SIZE 1518
95 #define PKT_MINBUF_SIZE 64
97 /* Maximum input buffer size. Must be a multiple of 32. */
98 #define PKT_MAXBLR_SIZE 1536
100 #define TOUT_LOOP 1000000
104 static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
106 #error "txbuf must be 64-bit aligned"
109 static uint rxIdx; /* index of the current RX buffer */
110 static uint txIdx; /* index of the current TX buffer */
113 * FCC Ethernet Tx and Rx buffer descriptors.
114 * Provide for Double Buffering
115 * Note: PKTBUFSRX is defined in net.h
118 typedef volatile struct rtxbd {
119 cbd_t rxbd[PKTBUFSRX];
120 cbd_t txbd[TX_BUF_CNT];
123 /* Good news: the FCC supports external BDs! */
125 static RTXBD rtx __attribute__ ((aligned(8)));
127 #error "rtx must be 64-bit aligned"
130 static int fec_send(struct eth_device *dev, void *packet, int length)
136 printf("fec: bad packet size: %d\n", length);
140 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
141 if (i >= TOUT_LOOP) {
142 puts ("fec: tx buffer not ready\n");
147 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
148 rtx.txbd[txIdx].cbd_datlen = length;
149 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
152 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
153 if (i >= TOUT_LOOP) {
154 puts ("fec: tx error\n");
160 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
163 /* return only status bits */
164 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
170 static int fec_recv(struct eth_device* dev)
176 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
178 break; /* nothing received - leave for() loop */
180 length = rtx.rxbd[rxIdx].cbd_datlen;
182 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
183 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
186 /* Pass the packet up to the protocol layers. */
187 net_process_received_packet(net_rx_packets[rxIdx], length - 4);
191 /* Give the buffer back to the FCC. */
192 rtx.rxbd[rxIdx].cbd_datlen = 0;
194 /* wrap around buffer index when necessary */
195 if ((rxIdx + 1) >= PKTBUFSRX) {
196 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
200 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
208 static int fec_init(struct eth_device* dev, bd_t *bis)
210 struct ether_fcc_info_s * info = dev->priv;
212 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
213 volatile cpm8260_t *cp = &(immr->im_cpm);
214 fcc_enet_t *pram_ptr;
215 unsigned long mem_addr;
221 /* 28.9 - (1-2): ioports have been set up already */
223 /* 28.9 - (3): connect FCC's tx and rx clocks */
224 immr->im_cpmux.cmx_uar = 0;
225 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
228 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
229 immr->im_fcc[info->ether_index].fcc_gfmr =
230 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
232 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
233 immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
235 /* 28.9 - (6): FDSR: Ethernet Syn */
236 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
238 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
242 /* Setup Receiver Buffer Descriptors */
243 for (i = 0; i < PKTBUFSRX; i++)
245 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
246 rtx.rxbd[i].cbd_datlen = 0;
247 rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
249 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
251 /* Setup Ethernet Transmitter Buffer Descriptors */
252 for (i = 0; i < TX_BUF_CNT; i++)
254 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
255 rtx.txbd[i].cbd_datlen = 0;
256 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
258 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
260 /* 28.9 - (7): initialise parameter ram */
261 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
263 /* clear whole structure to make sure all reserved fields are zero */
264 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
267 * common Parameter RAM area
269 * Allocate space in the reserved FCC area of DPRAM for the
270 * internal buffers. No one uses this space (yet), so we
271 * can do this. Later, we will add resource management for
274 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
275 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
276 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
278 * Set maximum bytes per receive buffer.
279 * It must be a multiple of 32.
281 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
282 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
283 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
284 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
285 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
286 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
287 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
289 /* protocol-specific area */
290 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
291 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
292 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
293 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
295 * Set Ethernet station address.
297 * This is supplied in the board information structure, so we
298 * copy that into the controller.
299 * So, far we have only been given one Ethernet address. We make
300 * it unique by setting a few bits in the upper byte of the
301 * non-static part of the address.
303 #define ea eth_get_ethaddr()
304 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
305 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
306 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
308 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
309 /* pad pointer. use tiptr since we don't need a specific padding char */
310 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
311 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
312 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
313 pram_ptr->fen_rfthr = 1;
314 pram_ptr->fen_rfcnt = 1;
316 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
317 pram_ptr->fen_genfcc.fcc_rbase);
318 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
319 pram_ptr->fen_genfcc.fcc_tbase);
322 /* 28.9 - (8): clear out events in FCCE */
323 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
325 /* 28.9 - (9): FCCM: mask all events */
326 immr->im_fcc[info->ether_index].fcc_fccm = 0;
328 /* 28.9 - (10-12): we don't use ethernet interrupts */
332 * Let's re-initialize the channel now. We have to do it later
333 * than the manual describes because we have just now finished
334 * the BD initialization.
336 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
337 info->cpm_cr_enet_sblock,
339 CPM_CR_INIT_TRX) | CPM_CR_FLG;
341 __asm__ __volatile__ ("eieio");
342 } while (cp->cp_cpcr & CPM_CR_FLG);
344 /* 28.9 - (14): enable tx/rx in gfmr */
345 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
350 static void fec_halt(struct eth_device* dev)
352 struct ether_fcc_info_s * info = dev->priv;
353 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
355 /* write GFMR: disable tx/rx */
356 immr->im_fcc[info->ether_index].fcc_gfmr &=
357 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
360 int fec_initialize(bd_t *bis)
362 struct eth_device* dev;
365 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
367 dev = (struct eth_device*) malloc(sizeof *dev);
368 memset(dev, 0, sizeof *dev);
370 sprintf(dev->name, "FCC%d",
371 ether_fcc_info[i].ether_index + 1);
372 dev->priv = ðer_fcc_info[i];
373 dev->init = fec_init;
374 dev->halt = fec_halt;
375 dev->send = fec_send;
376 dev->recv = fec_recv;
380 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
381 && defined(CONFIG_BITBANGMII)
382 miiphy_register(dev->name,
383 bb_miiphy_read, bb_miiphy_write);
390 #ifdef CONFIG_ETHER_LOOPBACK_TEST
392 #define ELBT_BUFSZ 1024 /* must be multiple of 32 */
396 #define ELBT_NRXBD 4 /* must be at least 2 */
399 #define ELBT_MAXRXERR 32
400 #define ELBT_MAXTXERR 32
402 #define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
413 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
414 uint badsrc, badtyp, badlen, badbit;
418 static elbt_prdesc rxeacc_descs[] = {
419 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
420 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
421 { offsetof(elbt_rxeacc, m), "Address Miss" },
422 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
423 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
424 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
425 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
426 { offsetof(elbt_rxeacc, sh), "Short Frame" },
427 { offsetof(elbt_rxeacc, cr), "CRC Error" },
428 { offsetof(elbt_rxeacc, ov), "Overrun" },
429 { offsetof(elbt_rxeacc, cl), "Collision" },
430 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
431 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
432 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
433 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
435 static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs);
439 uint def, hb, lc, rl, rc, un, csl;
443 static elbt_prdesc txeacc_descs[] = {
444 { offsetof(elbt_txeacc, def), "Defer Indication" },
445 { offsetof(elbt_txeacc, hb), "Heartbeat" },
446 { offsetof(elbt_txeacc, lc), "Late Collision" },
447 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
448 { offsetof(elbt_txeacc, rc), "Retry Count" },
449 { offsetof(elbt_txeacc, un), "Underrun" },
450 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
452 static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs);
456 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
457 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
458 cbd_t rxbd[ELBT_NRXBD];
459 cbd_t txbd[ELBT_NTXBD];
460 enum { Idle, Running, Closing, Closed } state;
461 int proff, page, sblock;
462 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
463 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
466 } __attribute__ ((aligned(8)))
469 static uchar patbytes[ELBT_NTXBD] = {
470 0xff, 0xaa, 0x55, 0x00
472 static uint patwords[ELBT_NTXBD] = {
473 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
477 static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
479 #error "elbt_chans must be 64-bit aligned"
482 #define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
484 static elbt_prdesc epram_descs[] = {
485 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
486 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
487 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
488 { offsetof(fcc_enet_t, fen_octc), "Octets" },
489 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
490 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
491 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
492 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
493 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
494 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
495 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
496 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
497 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
498 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
499 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
500 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
501 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
503 static int epram_ndesc = ARRAY_SIZE(epram_descs);
506 * given an elbt_prdesc array and an array of base addresses, print
507 * each prdesc down the screen with the values fetched from each
508 * base address across the screen
511 print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
513 elbt_prdesc *dp = descs, *edp = dp + ndesc;
518 for (i = 0; i < nbase; i++)
519 printf (" Channel %d", i);
525 printf ("%-32s", dp->lab);
527 for (i = 0; i < nbase; i++) {
528 uint val = *(uint *)(bases[i] + dp->off);
530 printf (" %10u", val);
540 * return number of bits that are set in a value; value contains
541 * nbits (right-justified) bits.
543 static uint __inline__
544 nbs (uint value, uint nbits)
548 uint pos = sizeof (uint) * 8;
550 __asm__ __volatile__ ("\
552 1: rlwnm. %2,%1,%4,31,31\n\
558 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
574 badbits (uchar *bp, int n, ulong pat)
579 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
582 diff = *bp++ ^ (uchar)pat;
585 cnt += nbs ((ulong)diff, 8);
591 nl = n / sizeof (ulong);
592 n -= nl * sizeof (ulong);
600 cnt += nbs (diff, 32);
610 diff = *bp++ ^ (uchar)pat;
613 cnt += nbs ((ulong)diff, 8);
621 static inline unsigned short
622 swap16 (unsigned short x)
624 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
627 /* broadcast is not an error - we send them like that */
628 #define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
631 eth_loopback_test (void)
633 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
634 volatile cpm8260_t *cp = &(immr->im_cpm);
636 ulong runtime, nmsec;
639 puts ("FCC Ethernet External loopback test\n");
641 eth_getenv_enetaddr("ethaddr", net_ethaddr);
644 * global initialisations for all FCC channels
647 /* 28.9 - (1-2): ioports have been set up already */
649 #if defined(CONFIG_SACSng)
651 * Attention: this is board-specific
654 # define FCC_START_LOOP 1
655 # define FCC_END_LOOP 1
658 * Attention: this is board-specific
659 * - FCC2 Rx-CLK is CLK13
660 * - FCC2 Tx-CLK is CLK14
663 /* 28.9 - (3): connect FCC's tx and rx clocks */
664 immr->im_cpmux.cmx_uar = 0;
665 immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
667 #error "eth_loopback_test not supported on your board"
670 puts ("Initialise FCC channels:");
672 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
673 elbt_chan *ecp = &elbt_chans[c];
674 volatile fcc_t *fcp = &immr->im_fcc[c];
675 volatile fcc_enet_t *fpp;
680 * initialise channel data
685 memset ((void *)ecp, 0, sizeof (*ecp));
692 ecp->proff = PROFF_FCC1;
693 ecp->page = CPM_CR_FCC1_PAGE;
694 ecp->sblock = CPM_CR_FCC1_SBLOCK;
698 ecp->proff = PROFF_FCC2;
699 ecp->page = CPM_CR_FCC2_PAGE;
700 ecp->sblock = CPM_CR_FCC2_SBLOCK;
704 ecp->proff = PROFF_FCC3;
705 ecp->page = CPM_CR_FCC3_PAGE;
706 ecp->sblock = CPM_CR_FCC3_SBLOCK;
711 * set up tx buffers and bds
714 for (i = 0; i < ELBT_NTXBD; i++) {
715 cbd_t *bdp = &ecp->txbd[i];
716 uchar *bp = &ecp->txbufs[i][0];
718 bdp->cbd_bufaddr = (uint)bp;
720 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
721 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
722 BD_ENET_TX_LAST | BD_ENET_TX_TC;
724 memset((void *)bp, patbytes[i], ELBT_BUFSZ);
725 net_set_ether(bp, net_bcast_ethaddr, 0x8000);
727 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
730 * set up rx buffers and bds
733 for (i = 0; i < ELBT_NRXBD; i++) {
734 cbd_t *bdp = &ecp->rxbd[i];
735 uchar *bp = &ecp->rxbufs[i][0];
737 bdp->cbd_bufaddr = (uint)bp;
739 bdp->cbd_sc = BD_ENET_RX_EMPTY;
741 memset ((void *)bp, 0, ELBT_BUFSZ);
743 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
746 * set up the FCC channel hardware
749 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
750 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
752 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
753 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
754 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
755 FCC_PSMR_MON | FCC_PSMR_RSH;
757 /* 28.9 - (6): FDSR: Ethernet Syn */
758 fcp->fcc_fdsr = 0xD555;
760 /* 29.9 - (7): initialise parameter ram */
761 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
763 /* clear whole struct to make sure all resv fields are zero */
764 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
767 * common Parameter RAM area
769 * Allocate space in the reserved FCC area of DPRAM for the
770 * internal buffers. No one uses this space (yet), so we
771 * can do this. Later, we will add resource management for
774 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
775 fpp->fen_genfcc.fcc_riptr = addr;
776 fpp->fen_genfcc.fcc_tiptr = addr + 32;
779 * Set maximum bytes per receive buffer.
780 * It must be a multiple of 32.
781 * buffers are in 60x bus memory.
783 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
784 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
785 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
786 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
787 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
789 /* protocol-specific area */
790 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
791 fpp->fen_cpres = 0xffffffff; /* CRC preset */
792 fpp->fen_retlim = 15; /* Retry limit threshold */
793 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
796 * Set Ethernet station address.
798 * This is supplied in the board information structure, so we
799 * copy that into the controller.
800 * So, far we have only been given one Ethernet address. We use
801 * the same address for all channels
803 fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4];
804 fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2];
805 fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0];
807 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
809 * pad pointer. use tiptr since we don't need
810 * a specific padding char
812 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
813 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
814 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
818 /* 28.9 - (8): clear out events in FCCE */
819 fcp->fcc_fcce = ~0x0;
821 /* 28.9 - (9): FCCM: mask all events */
824 /* 28.9 - (10-12): we don't use ethernet interrupts */
828 * Let's re-initialize the channel now. We have to do it later
829 * than the manual describes because we have just now finished
830 * the BD initialization.
832 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
833 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
835 __asm__ __volatile__ ("eieio");
836 } while (cp->cp_cpcr & CPM_CR_FLG);
839 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
842 * Note: don't want serial output from here until the end of the
843 * test - the delays would probably stuff things up.
847 runtime = get_timer (0);
852 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
853 volatile fcc_t *fcp = &immr->im_fcc[c];
854 elbt_chan *ecp = &elbt_chans[c];
857 switch (ecp->state) {
861 * set the channel Running ...
864 /* 28.9 - (14): enable tx/rx in gfmr */
865 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
867 ecp->state = Running;
872 * (while Running only) check for
873 * termination of the test
880 * initiate a "graceful stop transmit"
883 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
885 CPM_CR_GRACEFUL_STOP_TX) | \
888 __asm__ __volatile__ ("eieio");
889 } while (cp->cp_cpcr & CPM_CR_FLG);
891 ecp->clstime = get_timer (0);
892 ecp->state = Closing;
894 /* fall through ... */
898 * (while Running or Closing) poll the channel:
899 * - check for any non-READY tx buffers and
901 * - check for any non-EMPTY rx buffers and
902 * check that they were received correctly,
903 * adjust counters etc, then make empty
906 for (i = 0; i < ELBT_NTXBD; i++) {
907 cbd_t *bdp = &ecp->txbd[i];
908 ushort sc = bdp->cbd_sc;
910 if ((sc & BD_ENET_TX_READY) != 0)
914 * this frame has finished
919 if (sc & BD_ENET_TX_STATS) {
927 if (n < ELBT_MAXTXERR)
930 if (sc & BD_ENET_TX_DEF)
932 if (sc & BD_ENET_TX_HB)
934 if (sc & BD_ENET_TX_LC)
936 if (sc & BD_ENET_TX_RL)
938 if (sc & BD_ENET_TX_RCMASK)
940 if (sc & BD_ENET_TX_UN)
942 if (sc & BD_ENET_TX_CSL)
949 if (ecp->state == Closing)
950 ecp->clstime = get_timer (0);
952 /* make it ready again */
953 bdp->cbd_sc |= BD_ENET_TX_READY;
956 for (i = 0; i < ELBT_NRXBD; i++) {
957 cbd_t *bdp = &ecp->rxbd[i];
958 ushort sc = bdp->cbd_sc, mask;
960 if ((sc & BD_ENET_RX_EMPTY) != 0)
963 /* we have a new frame in this buffer */
966 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
967 if ((sc & mask) != mask) {
968 /* somethings wrong here ... */
969 if (!(sc & BD_ENET_RX_LAST))
971 if (!(sc & BD_ENET_RX_FIRST))
975 if (sc & BD_ENET_RX_ERRS) {
979 * we had some sort of error
983 if (n < ELBT_MAXRXERR)
986 if (sc & BD_ENET_RX_MISS)
988 if (sc & BD_ENET_RX_BC)
990 if (sc & BD_ENET_RX_MC)
992 if (sc & BD_ENET_RX_LG)
994 if (sc & BD_ENET_RX_NO)
996 if (sc & BD_ENET_RX_SH)
998 if (sc & BD_ENET_RX_CR)
1000 if (sc & BD_ENET_RX_OV)
1002 if (sc & BD_ENET_RX_CL)
1009 ushort datlen = bdp->cbd_datlen;
1010 struct ethernet_hdr *ehp;
1012 int ours, tb, n, nbytes;
1014 ehp = (struct ethernet_hdr *) \
1017 ours = memcmp (ehp->et_src, \
1020 prot = swap16 (ehp->et_protlen);
1024 nbytes = ELBT_BUFSZ -
1028 /* check the frame is correct */
1029 if (datlen != ELBT_BUFSZ)
1030 ecp->rxeacc.badlen++;
1032 ecp->rxeacc.badsrc++;
1033 else if (!tb || n >= ELBT_NTXBD)
1034 ecp->rxeacc.badtyp++;
1045 ecp->rxeacc.badbit += \
1050 if (ecp->state == Closing)
1051 ecp->clstime = get_timer (0);
1053 /* make it empty again */
1054 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1057 if (ecp->state != Closing)
1061 * (while Closing) check to see if
1062 * waited long enough
1065 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1066 /* write GFMR: disable tx/rx */
1068 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1069 ecp->state = Closed;
1080 } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
1082 runtime = get_timer (runtime);
1083 if (runtime <= ELBT_CLSWAIT) {
1084 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1085 runtime, ELBT_CLSWAIT);
1088 nmsec = runtime - ELBT_CLSWAIT;
1090 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1091 nmsec, ELBT_CLSWAIT);
1097 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
1098 elbt_chan *ecp = &elbt_chans[c];
1099 uint rxpps, txpps, nerr;
1101 rxpps = (ecp->nrcvd * 1000) / nmsec;
1102 txpps = (ecp->nsent * 1000) / nmsec;
1104 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1105 "%d sent (%d pps, %d txerrs)\n\n", c,
1106 ecp->nrcvd, rxpps, ecp->nrxerr,
1107 ecp->nsent, txpps, ecp->ntxerr);
1109 if ((nerr = ecp->nrxerr) > 0) {
1112 printf ("\tFirst %d rx errs:", nerr);
1113 for (i = 0; i < nerr; i++)
1114 printf (" %04x", ecp->rxerrs[i]);
1118 if ((nerr = ecp->ntxerr) > 0) {
1121 printf ("\tFirst %d tx errs:", nerr);
1122 for (i = 0; i < nerr; i++)
1123 printf (" %04x", ecp->txerrs[i]);
1128 puts ("Receive Error Counts:\n");
1129 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1130 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1131 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1133 puts ("\nTransmit Error Counts:\n");
1134 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1135 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1136 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1138 puts ("\nRMON(-like) Counters:\n");
1139 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1140 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1141 print_desc (epram_descs, epram_ndesc, bases, 3);
1144 #endif /* CONFIG_ETHER_LOOPBACK_TEST */