2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC5xxx CPUs
35 #include <asm/processor.h>
37 #if defined(CONFIG_OF_LIBFDT)
39 #include <libfdt_env.h>
40 #include <fdt_support.h>
43 #if defined(CONFIG_OF_IDE_FIXUP)
47 DECLARE_GLOBAL_DATA_PTR;
51 ulong clock = gd->cpu_clk;
68 printf("Unknown MPC5xxx");
72 printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
73 PVR_MAJ(pvr), PVR_MIN(pvr));
74 printf (" at %s MHz\n", strmhz (buf, clock));
78 /* ------------------------------------------------------------------------- */
81 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
84 /* Interrupts and MMU off */
85 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
87 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
88 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
90 /* Charge the watchdog timer */
91 *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
92 *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
99 /* ------------------------------------------------------------------------- */
102 * Get timebase clock frequency (like cpu_clk in Hz)
105 unsigned long get_tbclk (void)
109 tbclk = (gd->bus_clk + 3L) / 4L;
114 /* ------------------------------------------------------------------------- */
116 #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
117 void ft_cpu_setup(void *blob, bd_t *bd)
119 int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
120 char * cpu_path = "/cpus/" OF_CPU;
121 #ifdef CONFIG_MPC5xxx_FEC
123 char * eth_path = "/" OF_SOC "/ethernet@3000";
126 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
127 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
128 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
129 do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
130 do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
131 bd->bi_busfreq*div, 1);
132 #ifdef CONFIG_MPC5xxx_FEC
133 eth_getenv_enetaddr("ethaddr", enetaddr);
134 do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
135 do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
137 #if defined(CONFIG_OF_IDE_FIXUP)
138 if (!ide_device_present(0)) {
139 /* NO CF card detected -> delete ata node in DTS */
141 char nodename[] = "/soc5200@f0000000/ata@3a00";
143 nodeoffset = fdt_path_offset(blob, nodename);
144 if (nodeoffset >= 0) {
145 fdt_del_node(blob, nodeoffset);
147 printf("%s: cannot find %s node err:%s\n",
148 __func__, nodename, fdt_strerror(nodeoffset));
153 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
157 #ifdef CONFIG_BOOTCOUNT_LIMIT
159 void bootcount_store (ulong a)
161 volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
163 *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a;
166 ulong bootcount_load (void)
168 volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
170 if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
173 return (*save_addr & 0x0000ffff);
175 #endif /* CONFIG_BOOTCOUNT_LIMIT */
177 #ifdef CONFIG_MPC5xxx_FEC
178 /* Default initializations for FEC controllers. To override,
179 * create a board-specific function called:
180 * int board_eth_init(bd_t *bis)
183 int cpu_eth_init(bd_t *bis)
185 return mpc5xxx_fec_initialize(bis);
189 #if defined(CONFIG_WATCHDOG)
190 void watchdog_reset(void)
192 int re_enable = disable_interrupts();
193 reset_5xxx_watchdog();
194 if (re_enable) enable_interrupts();
197 void reset_5xxx_watchdog(void)
199 volatile struct mpc5xxx_gpt *gpt0 =
200 (struct mpc5xxx_gpt *) MPC5XXX_GPT;
202 /* Trigger TIMER_0 by writing A5 to OCPW */
203 clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
205 #endif /* CONFIG_WATCHDOG */