arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8568@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51                 reg = <0x0 0x10000000>;
  52         };
  53
  54         bcsr@f8000000 {
  55                 compatible = "fsl,mpc8568mds-bcsr";
  56                 reg = <0xf8000000 0x8000>;
  57         };
  58
  59         soc8568@e0000000 {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 device_type = "soc";
  63                 compatible = "simple-bus";
  64                 ranges = <0x0 0xe0000000 0x100000>;
  65                 reg = <0xe0000000 0x1000>;
  66                 bus-frequency = <0>;
  67
  68                 ecm-law@0 {
  69                         compatible = "fsl,ecm-law";
  70                         reg = <0x0 0x1000>;
  71                         fsl,num-laws = <10>;
  72                 };
  73
  74                 ecm@1000 {
  75                         compatible = "fsl,mpc8568-ecm", "fsl,ecm";
  76                         reg = <0x1000 0x1000>;
  77                         interrupts = <17 2>;
  78                         interrupt-parent = <&mpic>;
  79                 };
  80
  81                 memory-controller@2000 {
  82                         compatible = "fsl,8568-memory-controller";
  83                         reg = <0x2000 0x1000>;
  84                         interrupt-parent = <&mpic>;
  85                         interrupts = <18 2>;
  86                 };
  87
  88                 L2: l2-cache-controller@20000 {
  89                         compatible = "fsl,8568-l2-cache-controller";
  90                         reg = <0x20000 0x1000>;
  91                         cache-line-size = <32>; // 32 bytes
  92                         cache-size = <0x80000>; // L2, 512K
  93                         interrupt-parent = <&mpic>;
  94                         interrupts = <16 2>;
  95                 };
  96
  97                 i2c@3000 {
  98                         #address-cells = <1>;
  99                         #size-cells = <0>;
 100                         cell-index = <0>;
 101                         compatible = "fsl-i2c";
 102                         reg = <0x3000 0x100>;
 103                         interrupts = <43 2>;
 104                         interrupt-parent = <&mpic>;
 105                         dfsrr;
 106
 107                         rtc@68 {
 108                                 compatible = "dallas,ds1374";
 109                                 reg = <0x68>;
 110                         };
 111                 };
 112
 113                 i2c@3100 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         cell-index = <1>;
 117                         compatible = "fsl-i2c";
 118                         reg = <0x3100 0x100>;
 119                         interrupts = <43 2>;
 120                         interrupt-parent = <&mpic>;
 121                         dfsrr;
 122                 };
 123
 124                 dma@21300 {
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
 128                         reg = <0x21300 0x4>;
 129                         ranges = <0x0 0x21100 0x200>;
 130                         cell-index = <0>;
 131                         dma-channel@0 {
 132                                 compatible = "fsl,mpc8568-dma-channel",
 133                                                 "fsl,eloplus-dma-channel";
 134                                 reg = <0x0 0x80>;
 135                                 cell-index = <0>;
 136                                 interrupt-parent = <&mpic>;
 137                                 interrupts = <20 2>;
 138                         };
 139                         dma-channel@80 {
 140                                 compatible = "fsl,mpc8568-dma-channel",
 141                                                 "fsl,eloplus-dma-channel";
 142                                 reg = <0x80 0x80>;
 143                                 cell-index = <1>;
 144                                 interrupt-parent = <&mpic>;
 145                                 interrupts = <21 2>;
 146                         };
 147                         dma-channel@100 {
 148                                 compatible = "fsl,mpc8568-dma-channel",
 149                                                 "fsl,eloplus-dma-channel";
 150                                 reg = <0x100 0x80>;
 151                                 cell-index = <2>;
 152                                 interrupt-parent = <&mpic>;
 153                                 interrupts = <22 2>;
 154                         };
 155                         dma-channel@180 {
 156                                 compatible = "fsl,mpc8568-dma-channel",
 157                                                 "fsl,eloplus-dma-channel";
 158                                 reg = <0x180 0x80>;
 159                                 cell-index = <3>;
 160                                 interrupt-parent = <&mpic>;
 161                                 interrupts = <23 2>;
 162                         };
 163                 };
 164
 165                 enet0: ethernet@24000 {
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         cell-index = <0>;
 169                         device_type = "network";
 170                         model = "eTSEC";
 171                         compatible = "gianfar";
 172                         reg = <0x24000 0x1000>;
 173                         ranges = <0x0 0x24000 0x1000>;
 174                         local-mac-address = [ 00 00 00 00 00 00 ];
 175                         interrupts = <29 2 30 2 34 2>;
 176                         interrupt-parent = <&mpic>;
 177                         tbi-handle = <&tbi0>;
 178                         phy-handle = <&phy2>;
 179
 180                         mdio@520 {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183                                 compatible = "fsl,gianfar-mdio";
 184                                 reg = <0x520 0x20>;
 185
 186                                 phy0: ethernet-phy@7 {
 187                                         interrupt-parent = <&mpic>;
 188                                         interrupts = <1 1>;
 189                                         reg = <0x7>;
 190                                         device_type = "ethernet-phy";
 191                                 };
 192                                 phy1: ethernet-phy@1 {
 193                                         interrupt-parent = <&mpic>;
 194                                         interrupts = <2 1>;
 195                                         reg = <0x1>;
 196                                         device_type = "ethernet-phy";
 197                                 };
 198                                 phy2: ethernet-phy@2 {
 199                                         interrupt-parent = <&mpic>;
 200                                         interrupts = <1 1>;
 201                                         reg = <0x2>;
 202                                         device_type = "ethernet-phy";
 203                                 };
 204                                 phy3: ethernet-phy@3 {
 205                                         interrupt-parent = <&mpic>;
 206                                         interrupts = <2 1>;
 207                                         reg = <0x3>;
 208                                         device_type = "ethernet-phy";
 209                                 };
 210                                 tbi0: tbi-phy@11 {
 211                                         reg = <0x11>;
 212                                         device_type = "tbi-phy";
 213                                 };
 214                         };
 215                 };
 216
 217                 enet1: ethernet@25000 {
 218                         #address-cells = <1>;
 219                         #size-cells = <1>;
 220                         cell-index = <1>;
 221                         device_type = "network";
 222                         model = "eTSEC";
 223                         compatible = "gianfar";
 224                         reg = <0x25000 0x1000>;
 225                         ranges = <0x0 0x25000 0x1000>;
 226                         local-mac-address = [ 00 00 00 00 00 00 ];
 227                         interrupts = <35 2 36 2 40 2>;
 228                         interrupt-parent = <&mpic>;
 229                         tbi-handle = <&tbi1>;
 230                         phy-handle = <&phy3>;
 231
 232                         mdio@520 {
 233                                 #address-cells = <1>;
 234                                 #size-cells = <0>;
 235                                 compatible = "fsl,gianfar-tbi";
 236                                 reg = <0x520 0x20>;
 237
 238                                 tbi1: tbi-phy@11 {
 239                                         reg = <0x11>;
 240                                         device_type = "tbi-phy";
 241                                 };
 242                         };
 243                 };
 244
 245                 serial0: serial@4500 {
 246                         cell-index = <0>;
 247                         device_type = "serial";
 248                         compatible = "ns16550";
 249                         reg = <0x4500 0x100>;
 250                         clock-frequency = <0>;
 251                         interrupts = <42 2>;
 252                         interrupt-parent = <&mpic>;
 253                 };
 254
 255                 global-utilities@e0000 {        //global utilities block
 256                         compatible = "fsl,mpc8548-guts";
 257                         reg = <0xe0000 0x1000>;
 258                         fsl,has-rstcr;
 259                 };
 260
 261                 serial1: serial@4600 {
 262                         cell-index = <1>;
 263                         device_type = "serial";
 264                         compatible = "ns16550";
 265                         reg = <0x4600 0x100>;
 266                         clock-frequency = <0>;
 267                         interrupts = <42 2>;
 268                         interrupt-parent = <&mpic>;
 269                 };
 270
 271                 crypto@30000 {
 272                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 273                         reg = <0x30000 0x10000>;
 274                         interrupts = <45 2>;
 275                         interrupt-parent = <&mpic>;
 276                         fsl,num-channels = <4>;
 277                         fsl,channel-fifo-len = <24>;
 278                         fsl,exec-units-mask = <0xfe>;
 279                         fsl,descriptor-types-mask = <0x12b0ebf>;
 280                 };
 281
 282                 mpic: pic@40000 {
 283                         interrupt-controller;
 284                         #address-cells = <0>;
 285                         #interrupt-cells = <2>;
 286                         reg = <0x40000 0x40000>;
 287                         compatible = "chrp,open-pic";
 288                         device_type = "open-pic";
 289                 };
 290
 291                 par_io@e0100 {
 292                         reg = <0xe0100 0x100>;
 293                         device_type = "par_io";
 294                         num-ports = <7>;
 295
 296                         pio1: ucc_pin@01 {
 297                                 pio-map = <
 298                         /* port  pin  dir  open_drain  assignment  has_irq */
 299                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 300                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 301                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 302                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 303                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 304                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 305                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 306                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 307                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 308                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 309                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 310                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 311                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 312                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 313                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 314                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 315                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 316                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 317                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 318                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 319                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 320                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 321                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 322                         };
 323
 324                         pio2: ucc_pin@02 {
 325                                 pio-map = <
 326                         /* port  pin  dir  open_drain  assignment  has_irq */
 327                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 328                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 329                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 330                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 331                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 332                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 333                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 334                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 335                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 336                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 337                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 338                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 339                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 340                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 341                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 342                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 343                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 344                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 345                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 346                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 347                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 348                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 349                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 350                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 351                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 352                         };
 353                 };
 354         };
 355
 356         qe@e0080000 {
 357                 #address-cells = <1>;
 358                 #size-cells = <1>;
 359                 device_type = "qe";
 360                 compatible = "fsl,qe";
 361                 ranges = <0x0 0xe0080000 0x40000>;
 362                 reg = <0xe0080000 0x480>;
 363                 brg-frequency = <0>;
 364                 bus-frequency = <396000000>;
 365                 fsl,qe-num-riscs = <2>;
 366                 fsl,qe-num-snums = <28>;
 367
 368                 muram@10000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <1>;
 371                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 372                         ranges = <0x0 0x10000 0x10000>;
 373
 374                         data-only@0 {
 375                                 compatible = "fsl,qe-muram-data",
 376                                              "fsl,cpm-muram-data";
 377                                 reg = <0x0 0x10000>;
 378                         };
 379                 };
 380
 381                 spi@4c0 {
 382                         cell-index = <0>;
 383                         compatible = "fsl,spi";
 384                         reg = <0x4c0 0x40>;
 385                         interrupts = <2>;
 386                         interrupt-parent = <&qeic>;
 387                         mode = "cpu";
 388                 };
 389
 390                 spi@500 {
 391                         cell-index = <1>;
 392                         compatible = "fsl,spi";
 393                         reg = <0x500 0x40>;
 394                         interrupts = <1>;
 395                         interrupt-parent = <&qeic>;
 396                         mode = "cpu";
 397                 };
 398
 399                 enet2: ucc@2000 {
 400                         device_type = "network";
 401                         compatible = "ucc_geth";
 402                         cell-index = <1>;
 403                         reg = <0x2000 0x200>;
 404                         interrupts = <32>;
 405                         interrupt-parent = <&qeic>;
 406                         local-mac-address = [ 00 00 00 00 00 00 ];
 407                         rx-clock-name = "none";
 408                         tx-clock-name = "clk16";
 409                         pio-handle = <&pio1>;
 410                         phy-handle = <&phy0>;
 411                         phy-connection-type = "rgmii-id";
 412                 };
 413
 414                 enet3: ucc@3000 {
 415                         device_type = "network";
 416                         compatible = "ucc_geth";
 417                         cell-index = <2>;
 418                         reg = <0x3000 0x200>;
 419                         interrupts = <33>;
 420                         interrupt-parent = <&qeic>;
 421                         local-mac-address = [ 00 00 00 00 00 00 ];
 422                         rx-clock-name = "none";
 423                         tx-clock-name = "clk16";
 424                         pio-handle = <&pio2>;
 425                         phy-handle = <&phy1>;
 426                         phy-connection-type = "rgmii-id";
 427                 };
 428
 429                 mdio@2120 {
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         reg = <0x2120 0x18>;
 433                         compatible = "fsl,ucc-mdio";
 434
 435                         /* These are the same PHYs as on
 436                          * gianfar's MDIO bus */
 437                         qe_phy0: ethernet-phy@07 {
 438                                 interrupt-parent = <&mpic>;
 439                                 interrupts = <1 1>;
 440                                 reg = <0x7>;
 441                                 device_type = "ethernet-phy";
 442                         };
 443                         qe_phy1: ethernet-phy@01 {
 444                                 interrupt-parent = <&mpic>;
 445                                 interrupts = <2 1>;
 446                                 reg = <0x1>;
 447                                 device_type = "ethernet-phy";
 448                         };
 449                         qe_phy2: ethernet-phy@02 {
 450                                 interrupt-parent = <&mpic>;
 451                                 interrupts = <1 1>;
 452                                 reg = <0x2>;
 453                                 device_type = "ethernet-phy";
 454                         };
 455                         qe_phy3: ethernet-phy@03 {
 456                                 interrupt-parent = <&mpic>;
 457                                 interrupts = <2 1>;
 458                                 reg = <0x3>;
 459                                 device_type = "ethernet-phy";
 460                         };
 461                 };
 462
 463                 qeic: interrupt-controller@80 {
 464                         interrupt-controller;
 465                         compatible = "fsl,qe-ic";
 466                         #address-cells = <0>;
 467                         #interrupt-cells = <1>;
 468                         reg = <0x80 0x80>;
 469                         big-endian;
 470                         interrupts = <46 2 46 2>; //high:30 low:30
 471                         interrupt-parent = <&mpic>;
 472                 };
 473
 474         };
 475
 476         pci0: pci@e0008000 {
 477                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 478                 interrupt-map = <
 479                         /* IDSEL 0x12 AD18 */
 480                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 481                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 482                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 483                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 484
 485                         /* IDSEL 0x13 AD19 */
 486                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 487                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 488                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 489                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 490
 491                 interrupt-parent = <&mpic>;
 492                 interrupts = <24 2>;
 493                 bus-range = <0 255>;
 494                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 495                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 496                 clock-frequency = <66666666>;
 497                 #interrupt-cells = <1>;
 498                 #size-cells = <2>;
 499                 #address-cells = <3>;
 500                 reg = <0xe0008000 0x1000>;
 501                 compatible = "fsl,mpc8540-pci";
 502                 device_type = "pci";
 503         };
 504
 505         /* PCI Express */
 506         pci1: pcie@e000a000 {
 507                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 508                 interrupt-map = <
 509
 510                         /* IDSEL 0x0 (PEX) */
 511                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 512                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 513                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 514                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 515
 516                 interrupt-parent = <&mpic>;
 517                 interrupts = <26 2>;
 518                 bus-range = <0 255>;
 519                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 520                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 521                 clock-frequency = <33333333>;
 522                 #interrupt-cells = <1>;
 523                 #size-cells = <2>;
 524                 #address-cells = <3>;
 525                 reg = <0xe000a000 0x1000>;
 526                 compatible = "fsl,mpc8548-pcie";
 527                 device_type = "pci";
 528                 pcie@0 {
 529                         reg = <0x0 0x0 0x0 0x0 0x0>;
 530                         #size-cells = <2>;
 531                         #address-cells = <3>;
 532                         device_type = "pci";
 533                         ranges = <0x2000000 0x0 0xa0000000
 534                                   0x2000000 0x0 0xa0000000
 535                                   0x0 0x10000000
 536
 537                                   0x1000000 0x0 0x0
 538                                   0x1000000 0x0 0x0
 539                                   0x0 0x800000>;
 540                 };
 541         };
 542 };