2 * MPC8568E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 /memreserve/ 00000000 1000000;
18 model = "MPC8568EMDS";
19 compatible = "MPC8568EMDS", "MPC85xxMDS";
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K
33 i-cache-size = <8000>; // L1, 32K
34 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 device_type = "memory";
43 reg = <00000000 10000000>;
47 device_type = "board-control";
48 reg = <f8000000 8000>;
54 #interrupt-cells = <2>;
56 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00100000>;
62 compatible = "fsl-i2c";
65 interrupt-parent = <&mpic>;
71 compatible = "fsl-i2c";
74 interrupt-parent = <&mpic>;
82 compatible = "gianfar";
84 phy0: ethernet-phy@0 {
85 interrupt-parent = <&mpic>;
88 device_type = "ethernet-phy";
90 phy1: ethernet-phy@1 {
91 interrupt-parent = <&mpic>;
94 device_type = "ethernet-phy";
96 phy2: ethernet-phy@2 {
97 interrupt-parent = <&mpic>;
100 device_type = "ethernet-phy";
102 phy3: ethernet-phy@3 {
103 interrupt-parent = <&mpic>;
106 device_type = "ethernet-phy";
111 #address-cells = <1>;
113 device_type = "network";
115 compatible = "gianfar";
117 mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <d 2 e 2 12 2>;
119 interrupt-parent = <&mpic>;
120 phy-handle = <&phy2>;
124 #address-cells = <1>;
126 device_type = "network";
128 compatible = "gianfar";
130 mac-address = [ 00 00 00 00 00 00];
131 interrupts = <13 2 14 2 18 2>;
132 interrupt-parent = <&mpic>;
133 phy-handle = <&phy3>;
137 device_type = "serial";
138 compatible = "ns16550";
140 clock-frequency = <0>;
142 interrupt-parent = <&mpic>;
146 device_type = "serial";
147 compatible = "ns16550";
149 clock-frequency = <0>;
151 interrupt-parent = <&mpic>;
155 device_type = "crypto";
157 compatible = "talitos";
160 interrupt-parent = <&mpic>;
162 channel-fifo-len = <18>;
163 exec-units-mask = <000000fe>;
164 descriptor-types-mask = <012b0ebf>;
168 clock-frequency = <0>;
169 interrupt-controller;
170 #address-cells = <0>;
171 #interrupt-cells = <2>;
174 compatible = "chrp,open-pic";
175 device_type = "open-pic";
180 device_type = "par_io";
185 /* port pin dir open_drain assignment has_irq */
186 4 0a 1 0 2 0 /* TxD0 */
187 4 09 1 0 2 0 /* TxD1 */
188 4 08 1 0 2 0 /* TxD2 */
189 4 07 1 0 2 0 /* TxD3 */
190 4 17 1 0 2 0 /* TxD4 */
191 4 16 1 0 2 0 /* TxD5 */
192 4 15 1 0 2 0 /* TxD6 */
193 4 14 1 0 2 0 /* TxD7 */
194 4 0f 2 0 2 0 /* RxD0 */
195 4 0e 2 0 2 0 /* RxD1 */
196 4 0d 2 0 2 0 /* RxD2 */
197 4 0c 2 0 2 0 /* RxD3 */
198 4 1d 2 0 2 0 /* RxD4 */
199 4 1c 2 0 2 0 /* RxD5 */
200 4 1b 2 0 2 0 /* RxD6 */
201 4 1a 2 0 2 0 /* RxD7 */
202 4 0b 1 0 2 0 /* TX_EN */
203 4 18 1 0 2 0 /* TX_ER */
204 4 0f 2 0 2 0 /* RX_DV */
205 4 1e 2 0 2 0 /* RX_ER */
206 4 11 2 0 2 0 /* RX_CLK */
207 4 13 1 0 2 0 /* GTX_CLK */
208 1 1f 2 0 3 0>; /* GTX125 */
212 /* port pin dir open_drain assignment has_irq */
213 5 0a 1 0 2 0 /* TxD0 */
214 5 09 1 0 2 0 /* TxD1 */
215 5 08 1 0 2 0 /* TxD2 */
216 5 07 1 0 2 0 /* TxD3 */
217 5 17 1 0 2 0 /* TxD4 */
218 5 16 1 0 2 0 /* TxD5 */
219 5 15 1 0 2 0 /* TxD6 */
220 5 14 1 0 2 0 /* TxD7 */
221 5 0f 2 0 2 0 /* RxD0 */
222 5 0e 2 0 2 0 /* RxD1 */
223 5 0d 2 0 2 0 /* RxD2 */
224 5 0c 2 0 2 0 /* RxD3 */
225 5 1d 2 0 2 0 /* RxD4 */
226 5 1c 2 0 2 0 /* RxD5 */
227 5 1b 2 0 2 0 /* RxD6 */
228 5 1a 2 0 2 0 /* RxD7 */
229 5 0b 1 0 2 0 /* TX_EN */
230 5 18 1 0 2 0 /* TX_ER */
231 5 10 2 0 2 0 /* RX_DV */
232 5 1e 2 0 2 0 /* RX_ER */
233 5 11 2 0 2 0 /* RX_CLK */
234 5 13 1 0 2 0 /* GTX_CLK */
235 1 1f 2 0 3 0 /* GTX125 */
236 4 06 3 0 2 0 /* MDIO */
237 4 05 1 0 2 0>; /* MDC */
243 #address-cells = <1>;
247 ranges = <0 e0080000 00040000>;
248 reg = <e0080000 480>;
250 bus-frequency = <179A7B00>;
253 device_type = "muram";
254 ranges = <0 00010000 0000c000>;
263 compatible = "fsl_spi";
266 interrupt-parent = <&qeic>;
272 compatible = "fsl_spi";
275 interrupt-parent = <&qeic>;
280 device_type = "network";
281 compatible = "ucc_geth";
286 interrupt-parent = <&qeic>;
287 mac-address = [ 00 04 9f 00 23 23 ];
290 phy-handle = <&qe_phy0>;
291 phy-connection-type = "gmii";
292 pio-handle = <&pio1>;
296 device_type = "network";
297 compatible = "ucc_geth";
302 interrupt-parent = <&qeic>;
303 mac-address = [ 00 11 22 33 44 55 ];
306 phy-handle = <&qe_phy1>;
307 phy-connection-type = "gmii";
308 pio-handle = <&pio2>;
312 #address-cells = <1>;
315 device_type = "mdio";
316 compatible = "ucc_geth_phy";
318 /* These are the same PHYs as on
319 * gianfar's MDIO bus */
320 qe_phy0: ethernet-phy@00 {
321 interrupt-parent = <&mpic>;
324 device_type = "ethernet-phy";
326 qe_phy1: ethernet-phy@01 {
327 interrupt-parent = <&mpic>;
330 device_type = "ethernet-phy";
332 qe_phy2: ethernet-phy@02 {
333 interrupt-parent = <&mpic>;
336 device_type = "ethernet-phy";
338 qe_phy3: ethernet-phy@03 {
339 interrupt-parent = <&mpic>;
342 device_type = "ethernet-phy";
347 interrupt-controller;
348 device_type = "qeic";
349 #address-cells = <0>;
350 #interrupt-cells = <1>;
354 interrupts = <1e 2 1e 2>; //high:30 low:30
355 interrupt-parent = <&mpic>;