2 * GE Fanuc SBC310 Device Tree Source
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
25 compatible = "gef,sbc310";
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
86 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
87 reg = <0x0 0x0 0x01000000>;
94 reg = <0x0 0x01000000>;
101 compatible = "gef,sbc310-paged-flash", "cfi-flash";
102 reg = <0x1 0x0 0x8000000>;
105 #address-cells = <1>;
109 reg = <0x0 0x7800000>;
113 reg = <0x7800000 0x800000>;
119 device_type = "nvram";
120 compatible = "simtek,stk14ca8";
121 reg = <0x3 0x0 0x20000>;
125 compatible = "gef,fpga-regs";
126 reg = <0x4 0x0 0x40>;
130 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
132 reg = <0x4 0x2000 0x8>;
133 interrupts = <0x1a 0x4>;
134 interrupt-parent = <&gef_pic>;
138 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
140 reg = <0x4 0x2010 0x8>;
141 interrupts = <0x1b 0x4>;
142 interrupt-parent = <&gef_pic>;
145 gef_pic: pic@4,4000 {
146 #interrupt-cells = <1>;
147 interrupt-controller;
148 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
149 reg = <0x4 0x4000 0x20>;
152 interrupt-parent = <&mpic>;
155 gef_gpio: gpio@4,8000 {
157 compatible = "gef,sbc310-gpio";
158 reg = <0x4 0x8000 0x24>;
164 #address-cells = <1>;
166 #interrupt-cells = <2>;
168 compatible = "fsl,mpc8641-soc", "simple-bus";
169 ranges = <0x0 0xfef00000 0x00100000>;
170 bus-frequency = <33333333>;
173 compatible = "fsl,mcm-law";
179 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
180 reg = <0x1000 0x1000>;
182 interrupt-parent = <&mpic>;
186 #address-cells = <1>;
188 compatible = "fsl-i2c";
189 reg = <0x3000 0x100>;
190 interrupts = <0x2b 0x2>;
191 interrupt-parent = <&mpic>;
195 compatible = "epson,rx8581";
201 #address-cells = <1>;
203 compatible = "fsl-i2c";
204 reg = <0x3100 0x100>;
205 interrupts = <0x2b 0x2>;
206 interrupt-parent = <&mpic>;
210 compatible = "national,lm92";
215 compatible = "adi,adt7461";
220 compatible = "dallas,ds1682";
226 #address-cells = <1>;
228 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
230 ranges = <0x0 0x21100 0x200>;
233 compatible = "fsl,mpc8641-dma-channel",
234 "fsl,eloplus-dma-channel";
237 interrupt-parent = <&mpic>;
241 compatible = "fsl,mpc8641-dma-channel",
242 "fsl,eloplus-dma-channel";
245 interrupt-parent = <&mpic>;
249 compatible = "fsl,mpc8641-dma-channel",
250 "fsl,eloplus-dma-channel";
253 interrupt-parent = <&mpic>;
257 compatible = "fsl,mpc8641-dma-channel",
258 "fsl,eloplus-dma-channel";
261 interrupt-parent = <&mpic>;
266 enet0: ethernet@24000 {
267 #address-cells = <1>;
269 device_type = "network";
271 compatible = "gianfar";
272 reg = <0x24000 0x1000>;
273 ranges = <0x0 0x24000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
276 interrupt-parent = <&mpic>;
277 phy-handle = <&phy0>;
278 phy-connection-type = "gmii";
281 #address-cells = <1>;
283 compatible = "fsl,gianfar-mdio";
286 phy0: ethernet-phy@0 {
287 interrupt-parent = <&gef_pic>;
288 interrupts = <0x9 0x4>;
291 phy2: ethernet-phy@2 {
292 interrupt-parent = <&gef_pic>;
293 interrupts = <0x8 0x4>;
299 enet1: ethernet@26000 {
300 device_type = "network";
302 compatible = "gianfar";
303 reg = <0x26000 0x1000>;
304 local-mac-address = [ 00 00 00 00 00 00 ];
305 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
306 interrupt-parent = <&mpic>;
307 phy-handle = <&phy2>;
308 phy-connection-type = "gmii";
311 serial0: serial@4500 {
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>;
316 clock-frequency = <0>;
317 interrupts = <0x2a 0x2>;
318 interrupt-parent = <&mpic>;
321 serial1: serial@4600 {
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>;
326 clock-frequency = <0>;
327 interrupts = <0x1c 0x2>;
328 interrupt-parent = <&mpic>;
332 clock-frequency = <0>;
333 interrupt-controller;
334 #address-cells = <0>;
335 #interrupt-cells = <2>;
336 reg = <0x40000 0x40000>;
337 compatible = "chrp,open-pic";
338 device_type = "open-pic";
341 global-utilities@e0000 {
342 compatible = "fsl,mpc8641-guts";
343 reg = <0xe0000 0x1000>;
348 pci0: pcie@fef08000 {
349 compatible = "fsl,mpc8641-pcie";
351 #interrupt-cells = <1>;
353 #address-cells = <3>;
354 reg = <0xfef08000 0x1000>;
355 bus-range = <0x0 0xff>;
356 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
357 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
358 clock-frequency = <33333333>;
359 interrupt-parent = <&mpic>;
360 interrupts = <0x18 0x2>;
361 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
363 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
364 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
365 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
366 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
372 #address-cells = <3>;
374 ranges = <0x02000000 0x0 0x80000000
375 0x02000000 0x0 0x80000000
378 0x01000000 0x0 0x00000000
379 0x01000000 0x0 0x00000000
384 pci1: pcie@fef09000 {
385 compatible = "fsl,mpc8641-pcie";
387 #interrupt-cells = <1>;
389 #address-cells = <3>;
390 reg = <0xfef09000 0x1000>;
391 bus-range = <0x0 0xff>;
392 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
393 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
394 clock-frequency = <33333333>;
395 interrupt-parent = <&mpic>;
396 interrupts = <0x19 0x2>;
397 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
400 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
401 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
402 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
408 #address-cells = <3>;
410 ranges = <0x02000000 0x0 0xc0000000
411 0x02000000 0x0 0xc0000000
414 0x01000000 0x0 0x00000000
415 0x01000000 0x0 0x00000000