2 * Device Tree Source for AMCC Canyonlands (460EX)
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
16 model = "amcc,canyonlands";
17 compatible = "amcc,canyonlands";
18 dcr-parent = <&{/cpus/cpu@0}>;
33 model = "PowerPC,460EX";
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
42 dcr-access-method = "native";
43 next-level-cache = <&L2C0>;
48 device_type = "memory";
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-460ex","ibm,uic";
56 dcr-reg = <0x0c0 0x009>;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-460ex","ibm,uic";
66 dcr-reg = <0x0d0 0x009>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-460ex","ibm,uic";
78 dcr-reg = <0x0e0 0x009>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-460ex","ibm,uic";
90 dcr-reg = <0x0f0 0x009>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
99 compatible = "ibm,sdr-460ex";
100 dcr-reg = <0x00e 0x002>;
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
111 0x030 0x008>; /* L2 cache DCR's */
112 cache-line-size = <32>; /* 32 bytes */
113 cache-size = <262144>; /* L2, 256K */
114 interrupt-parent = <&UIC1>;
119 compatible = "ibm,plb-460ex", "ibm,plb4";
120 #address-cells = <2>;
123 clock-frequency = <0>; /* Filled in by U-Boot */
126 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
127 dcr-reg = <0x010 0x002>;
130 CRYPTO: crypto@180000 {
131 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
132 reg = <4 0x00180000 0x80400>;
133 interrupt-parent = <&UIC0>;
134 interrupts = <0x1d 0x4>;
138 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
139 dcr-reg = <0x180 0x062>;
142 #address-cells = <0>;
144 interrupt-parent = <&UIC2>;
145 interrupts = < /*TXEOB*/ 0x6 0x4
152 USB0: ehci@bffd0400 {
153 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
154 interrupt-parent = <&UIC2>;
155 interrupts = <0x1d 4>;
156 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
160 compatible = "ohci-le";
161 reg = <4 0xbffd0000 0x60>;
162 interrupt-parent = <&UIC2>;
163 interrupts = <0x1e 4>;
166 SATA0: sata@bffd1000 {
167 compatible = "amcc,sata-460ex";
168 reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
169 interrupt-parent = <&UIC3>;
170 interrupts = <0x0 0x4 /* SATA */
171 0x5 0x4>; /* AHBDMA */
175 compatible = "ibm,opb-460ex", "ibm,opb";
176 #address-cells = <1>;
178 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
179 clock-frequency = <0>; /* Filled in by U-Boot */
182 compatible = "ibm,ebc-460ex", "ibm,ebc";
183 dcr-reg = <0x012 0x002>;
184 #address-cells = <2>;
186 clock-frequency = <0>; /* Filled in by U-Boot */
187 /* ranges property is supplied by U-Boot */
188 interrupts = <0x6 0x4>;
189 interrupt-parent = <&UIC1>;
192 compatible = "amd,s29gl512n", "cfi-flash";
194 reg = <0x00000000 0x00000000 0x04000000>;
195 #address-cells = <1>;
199 reg = <0x00000000 0x001e0000>;
203 reg = <0x001e0000 0x00020000>;
207 reg = <0x00200000 0x01400000>;
211 reg = <0x01600000 0x00400000>;
215 reg = <0x01a00000 0x02560000>;
219 reg = <0x03f60000 0x00040000>;
223 reg = <0x03fa0000 0x00060000>;
228 compatible = "ibm,ndfc";
229 reg = <0x00000003 0x00000000 0x00002000>;
231 bank-settings = <0x80002222>;
232 #address-cells = <1>;
236 #address-cells = <1>;
241 reg = <0x00000000 0x00100000>;
245 reg = <0x00000000 0x03f00000>;
251 UART0: serial@ef600300 {
252 device_type = "serial";
253 compatible = "ns16550";
254 reg = <0xef600300 0x00000008>;
255 virtual-reg = <0xef600300>;
256 clock-frequency = <0>; /* Filled in by U-Boot */
257 current-speed = <0>; /* Filled in by U-Boot */
258 interrupt-parent = <&UIC1>;
259 interrupts = <0x1 0x4>;
262 UART1: serial@ef600400 {
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0xef600400 0x00000008>;
266 virtual-reg = <0xef600400>;
267 clock-frequency = <0>; /* Filled in by U-Boot */
268 current-speed = <0>; /* Filled in by U-Boot */
269 interrupt-parent = <&UIC0>;
270 interrupts = <0x1 0x4>;
273 UART2: serial@ef600500 {
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0xef600500 0x00000008>;
277 virtual-reg = <0xef600500>;
278 clock-frequency = <0>; /* Filled in by U-Boot */
279 current-speed = <0>; /* Filled in by U-Boot */
280 interrupt-parent = <&UIC1>;
281 interrupts = <28 0x4>;
284 UART3: serial@ef600600 {
285 device_type = "serial";
286 compatible = "ns16550";
287 reg = <0xef600600 0x00000008>;
288 virtual-reg = <0xef600600>;
289 clock-frequency = <0>; /* Filled in by U-Boot */
290 current-speed = <0>; /* Filled in by U-Boot */
291 interrupt-parent = <&UIC1>;
292 interrupts = <29 0x4>;
296 compatible = "ibm,iic-460ex", "ibm,iic";
297 reg = <0xef600700 0x00000014>;
298 interrupt-parent = <&UIC0>;
299 interrupts = <0x2 0x4>;
300 #address-cells = <1>;
303 compatible = "stm,m41t80";
305 interrupt-parent = <&UIC2>;
306 interrupts = <0x19 0x8>;
309 compatible = "ad,ad7414";
311 interrupt-parent = <&UIC1>;
312 interrupts = <0x14 0x8>;
317 compatible = "ibm,iic-460ex", "ibm,iic";
318 reg = <0xef600800 0x00000014>;
319 interrupt-parent = <&UIC0>;
320 interrupts = <0x3 0x4>;
323 ZMII0: emac-zmii@ef600d00 {
324 compatible = "ibm,zmii-460ex", "ibm,zmii";
325 reg = <0xef600d00 0x0000000c>;
328 RGMII0: emac-rgmii@ef601500 {
329 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
330 reg = <0xef601500 0x00000008>;
334 TAH0: emac-tah@ef601350 {
335 compatible = "ibm,tah-460ex", "ibm,tah";
336 reg = <0xef601350 0x00000030>;
339 TAH1: emac-tah@ef601450 {
340 compatible = "ibm,tah-460ex", "ibm,tah";
341 reg = <0xef601450 0x00000030>;
344 EMAC0: ethernet@ef600e00 {
345 device_type = "network";
346 compatible = "ibm,emac-460ex", "ibm,emac4sync";
347 interrupt-parent = <&EMAC0>;
348 interrupts = <0x0 0x1>;
349 #interrupt-cells = <1>;
350 #address-cells = <0>;
352 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
353 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
354 reg = <0xef600e00 0x000000c4>;
355 local-mac-address = [000000000000]; /* Filled in by U-Boot */
356 mal-device = <&MAL0>;
357 mal-tx-channel = <0>;
358 mal-rx-channel = <0>;
360 max-frame-size = <9000>;
361 rx-fifo-size = <4096>;
362 tx-fifo-size = <2048>;
363 rx-fifo-size-gige = <16384>;
365 phy-map = <0x00000000>;
366 rgmii-device = <&RGMII0>;
368 tah-device = <&TAH0>;
370 has-inverted-stacr-oc;
371 has-new-stacr-staopc;
374 EMAC1: ethernet@ef600f00 {
375 device_type = "network";
376 compatible = "ibm,emac-460ex", "ibm,emac4sync";
377 interrupt-parent = <&EMAC1>;
378 interrupts = <0x0 0x1>;
379 #interrupt-cells = <1>;
380 #address-cells = <0>;
382 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
383 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
384 reg = <0xef600f00 0x000000c4>;
385 local-mac-address = [000000000000]; /* Filled in by U-Boot */
386 mal-device = <&MAL0>;
387 mal-tx-channel = <1>;
388 mal-rx-channel = <8>;
390 max-frame-size = <9000>;
391 rx-fifo-size = <4096>;
392 tx-fifo-size = <2048>;
393 rx-fifo-size-gige = <16384>;
395 phy-map = <0x00000000>;
396 rgmii-device = <&RGMII0>;
398 tah-device = <&TAH1>;
400 has-inverted-stacr-oc;
401 has-new-stacr-staopc;
402 mdio-device = <&EMAC0>;
406 PCIX0: pci@c0ec00000 {
408 #interrupt-cells = <1>;
410 #address-cells = <3>;
411 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
413 large-inbound-windows;
415 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
416 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
417 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
418 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
419 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
421 /* Outbound ranges, one memory and one IO,
422 * later cannot be changed
424 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
425 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
426 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
428 /* Inbound 2GB range starting at 0 */
429 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
431 /* This drives busses 0 to 0x3f */
432 bus-range = <0x0 0x3f>;
434 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
435 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
436 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
439 PCIE0: pciex@d00000000 {
441 #interrupt-cells = <1>;
443 #address-cells = <3>;
444 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
446 port = <0x0>; /* port number */
447 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
448 0x0000000c 0x08010000 0x00001000>; /* Registers */
449 dcr-reg = <0x100 0x020>;
452 /* Outbound ranges, one memory and one IO,
453 * later cannot be changed
455 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
456 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
457 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
459 /* Inbound 2GB range starting at 0 */
460 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
462 /* This drives busses 40 to 0x7f */
463 bus-range = <0x40 0x7f>;
465 /* Legacy interrupts (note the weird polarity, the bridge seems
466 * to invert PCIe legacy interrupts).
467 * We are de-swizzling here because the numbers are actually for
468 * port of the root complex virtual P2P bridge. But I want
469 * to avoid putting a node for it in the tree, so the numbers
470 * below are basically de-swizzled numbers.
471 * The real slot is on idsel 0, so the swizzling is 1:1
473 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
475 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
476 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
477 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
478 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
481 PCIE1: pciex@d20000000 {
483 #interrupt-cells = <1>;
485 #address-cells = <3>;
486 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
488 port = <0x1>; /* port number */
489 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
490 0x0000000c 0x08011000 0x00001000>; /* Registers */
491 dcr-reg = <0x120 0x020>;
494 /* Outbound ranges, one memory and one IO,
495 * later cannot be changed
497 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
498 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
499 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
501 /* Inbound 2GB range starting at 0 */
502 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
504 /* This drives busses 80 to 0xbf */
505 bus-range = <0x80 0xbf>;
507 /* Legacy interrupts (note the weird polarity, the bridge seems
508 * to invert PCIe legacy interrupts).
509 * We are de-swizzling here because the numbers are actually for
510 * port of the root complex virtual P2P bridge. But I want
511 * to avoid putting a node for it in the tree, so the numbers
512 * below are basically de-swizzled numbers.
513 * The real slot is on idsel 0, so the swizzling is 1:1
515 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
517 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
518 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
519 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
520 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;