2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
40 #include <linux/linkage.h>
48 .import pa_dbit_lock,data
50 /* space_to_prot macro creates a prot id from a space id */
52 #if (SPACEID_SHIFT) == 0
53 .macro space_to_prot spc prot
54 depd,z \spc,62,31,\prot
57 .macro space_to_prot spc prot
58 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
62 /* Switch to virtual mapping, trashing only %r1 */
65 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
69 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
72 load32 KERNEL_PSW, %r1
74 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
77 mtctl %r0, %cr17 /* Clear IIASQ tail */
78 mtctl %r0, %cr17 /* Clear IIASQ head */
81 mtctl %r1, %cr18 /* Set IIAOQ tail */
83 mtctl %r1, %cr18 /* Set IIAOQ head */
90 * The "get_stack" macros are responsible for determining the
94 * Already using a kernel stack, so call the
95 * get_stack_use_r30 macro to push a pt_regs structure
96 * on the stack, and store registers there.
98 * Need to set up a kernel stack, so call the
99 * get_stack_use_cr30 macro to set up a pointer
100 * to the pt_regs structure contained within the
101 * task pointer pointed to by cr30. Set the stack
102 * pointer to point to the end of the task structure.
104 * Note that we use shadowed registers for temps until
105 * we can save %r26 and %r29. %r26 is used to preserve
106 * %r8 (a shadowed register) which temporarily contained
107 * either the fault type ("code") or the eirr. We need
108 * to use a non-shadowed register to carry the value over
109 * the rfir in virt_map. We use %r26 since this value winds
110 * up being passed as the argument to either do_cpu_irq_mask
111 * or handle_interruption. %r29 is used to hold a pointer
112 * the register save area, and once again, it needs to
113 * be a non-shadowed register so that it survives the rfir.
115 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
118 .macro get_stack_use_cr30
120 /* we save the registers in the task struct */
124 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
126 ldo TASK_REGS(%r9),%r9
127 STREG %r30, PT_GR30(%r9)
128 STREG %r29,PT_GR29(%r9)
129 STREG %r26,PT_GR26(%r9)
132 ldo THREAD_SZ_ALGN(%r1), %r30
135 .macro get_stack_use_r30
137 /* we put a struct pt_regs on the stack and save the registers there */
140 STREG %r30,PT_GR30(%r9)
141 ldo PT_SZ_ALGN(%r30),%r30
142 STREG %r29,PT_GR29(%r9)
143 STREG %r26,PT_GR26(%r9)
148 LDREG PT_GR1(%r29), %r1
149 LDREG PT_GR30(%r29),%r30
150 LDREG PT_GR29(%r29),%r29
153 /* default interruption handler
154 * (calls traps.c:handle_interruption) */
161 /* Interrupt interruption handler
162 * (calls irq.c:do_cpu_irq_mask) */
169 .import os_hpmc, code
173 nop /* must be a NOP, will be patched later */
174 load32 PA(os_hpmc), %r3
177 .word 0 /* checksum (will be patched) */
178 .word PA(os_hpmc) /* address of handler */
179 .word 0 /* length of handler */
183 * Performance Note: Instructions will be moved up into
184 * this part of the code later on, once we are sure
185 * that the tlb miss handlers are close to final form.
188 /* Register definitions for tlb miss handler macros */
190 va = r8 /* virtual address for which the trap occured */
191 spc = r24 /* space for which the trap occured */
196 * itlb miss interruption handler (parisc 1.1 - 32 bit)
210 * itlb miss interruption handler (parisc 2.0)
227 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
229 * Note: naitlb misses will be treated
230 * as an ordinary itlb miss for now.
231 * However, note that naitlb misses
232 * have the faulting address in the
236 .macro naitlb_11 code
241 /* FIXME: If user causes a naitlb miss, the priv level may not be in
242 * lower bits of va, where the itlb miss handler is expecting them
250 * naitlb miss interruption handler (parisc 2.0)
252 * Note: naitlb misses will be treated
253 * as an ordinary itlb miss for now.
254 * However, note that naitlb misses
255 * have the faulting address in the
259 .macro naitlb_20 code
268 /* FIXME: If user causes a naitlb miss, the priv level may not be in
269 * lower bits of va, where the itlb miss handler is expecting them
277 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
291 * dtlb miss interruption handler (parisc 2.0)
308 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
310 .macro nadtlb_11 code
320 /* nadtlb miss interruption handler (parisc 2.0) */
322 .macro nadtlb_20 code
337 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
351 * dirty bit trap interruption handler (parisc 2.0)
367 /* The following are simple 32 vs 64 bit instruction
368 * abstractions for the macros */
369 .macro EXTR reg1,start,length,reg2
371 extrd,u \reg1,32+(\start),\length,\reg2
373 extrw,u \reg1,\start,\length,\reg2
377 .macro DEP reg1,start,length,reg2
379 depd \reg1,32+(\start),\length,\reg2
381 depw \reg1,\start,\length,\reg2
385 .macro DEPI val,start,length,reg
387 depdi \val,32+(\start),\length,\reg
389 depwi \val,\start,\length,\reg
393 /* In LP64, the space contains part of the upper 32 bits of the
394 * fault. We have to extract this and place it in the va,
395 * zeroing the corresponding bits in the space register */
396 .macro space_adjust spc,va,tmp
398 extrd,u \spc,63,SPACEID_SHIFT,\tmp
399 depd %r0,63,SPACEID_SHIFT,\spc
400 depd \tmp,31,SPACEID_SHIFT,\va
404 .import swapper_pg_dir,code
406 /* Get the pgd. For faults on space zero (kernel space), this
407 * is simply swapper_pg_dir. For user space faults, the
408 * pgd is stored in %cr25 */
409 .macro get_pgd spc,reg
410 ldil L%PA(swapper_pg_dir),\reg
411 ldo R%PA(swapper_pg_dir)(\reg),\reg
412 or,COND(=) %r0,\spc,%r0
417 space_check(spc,tmp,fault)
419 spc - The space we saw the fault with.
420 tmp - The place to store the current space.
421 fault - Function to call on failure.
423 Only allow faults on different spaces from the
424 currently active one if we're the kernel
427 .macro space_check spc,tmp,fault
429 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
430 * as kernel, so defeat the space
433 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
434 cmpb,COND(<>),n \tmp,\spc,\fault
437 /* Look up a PTE in a 2-Level scheme (faulting at each
438 * level if the entry isn't present
440 * NOTE: we use ldw even for LP64, since the short pointers
441 * can address up to 1TB
443 .macro L2_ptep pmd,pte,index,va,fault
445 EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
447 EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
449 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
451 ldw,s \index(\pmd),\pmd
452 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
453 DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
455 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
456 EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
457 DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
458 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
459 LDREG %r0(\pmd),\pte /* pmd is now pte */
460 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
463 /* Look up PTE in a 3-Level scheme.
465 * Here we implement a Hybrid L2/L3 scheme: we allocate the
466 * first pmd adjacent to the pgd. This means that we can
467 * subtract a constant offset to get to it. The pmd and pgd
468 * sizes are arranged so that a single pmd covers 4GB (giving
469 * a full LP64 process access to 8TB) so our lookups are
470 * effectively L2 for the first 4GB of the kernel (i.e. for
471 * all ILP32 processes and all the kernel for machines with
472 * under 4GB of memory) */
473 .macro L3_ptep pgd,pte,index,va,fault
474 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
475 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
477 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
478 ldw,s \index(\pgd),\pgd
479 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
480 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
481 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
482 shld \pgd,PxD_VALUE_SHIFT,\index
483 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
485 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
486 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
488 L2_ptep \pgd,\pte,\index,\va,\fault
491 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
492 * don't needlessly dirty the cache line if it was already set */
493 .macro update_ptep ptep,pte,tmp,tmp1
494 ldi _PAGE_ACCESSED,\tmp1
496 and,COND(<>) \tmp1,\pte,%r0
500 /* Set the dirty bit (and accessed bit). No need to be
501 * clever, this is only used from the dirty fault */
502 .macro update_dirty ptep,pte,tmp
503 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
508 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
509 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
510 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
512 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
513 .macro convert_for_tlb_insert20 pte
514 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
515 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
516 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
517 (63-58)+PAGE_ADD_SHIFT,\pte
520 /* Convert the pte and prot to tlb insertion values. How
521 * this happens is quite subtle, read below */
522 .macro make_insert_tlb spc,pte,prot
523 space_to_prot \spc \prot /* create prot id from space */
524 /* The following is the real subtlety. This is depositing
525 * T <-> _PAGE_REFTRAP
527 * B <-> _PAGE_DMB (memory break)
529 * Then incredible subtlety: The access rights are
530 * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
531 * See 3-14 of the parisc 2.0 manual
533 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
534 * trigger an access rights trap in user space if the user
535 * tries to read an unreadable page */
538 /* PAGE_USER indicates the page can be read with user privileges,
539 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
540 * contains _PAGE_READ */
541 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
543 /* If we're a gateway page, drop PL2 back to zero for promotion
544 * to kernel privilege (so we can execute the page as kernel).
545 * Any privilege promotion page always denys read and write */
546 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
547 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
549 /* Enforce uncacheable pages.
550 * This should ONLY be use for MMIO on PA 2.0 machines.
551 * Memory/DMA is cache coherent on all PA2.0 machines we support
552 * (that means T-class is NOT supported) and the memory controllers
553 * on most of those machines only handles cache transactions.
555 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
558 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
559 convert_for_tlb_insert20 \pte
562 /* Identical macro to make_insert_tlb above, except it
563 * makes the tlb entry for the differently formatted pa11
564 * insertion instructions */
565 .macro make_insert_tlb_11 spc,pte,prot
566 zdep \spc,30,15,\prot
568 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
570 extru,= \pte,_PAGE_USER_BIT,1,%r0
571 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
572 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
573 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
575 /* Get rid of prot bits and convert to page addr for iitlba */
577 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
578 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
581 /* This is for ILP32 PA2.0 only. The TLB insertion needs
582 * to extend into I/O space if the address is 0xfXXXXXXX
583 * so we extend the f's into the top word of the pte in
585 .macro f_extend pte,tmp
586 extrd,s \pte,42,4,\tmp
588 extrd,s \pte,63,25,\pte
591 /* The alias region is an 8MB aligned 16MB to do clear and
592 * copy user pages at addresses congruent with the user
595 * To use the alias page, you set %r26 up with the to TLB
596 * entry (identifying the physical page) and %r23 up with
597 * the from tlb entry (or nothing if only a to entry---for
598 * clear_user_page_asm) */
599 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault
600 cmpib,COND(<>),n 0,\spc,\fault
601 ldil L%(TMPALIAS_MAP_START),\tmp
602 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
603 /* on LP64, ldi will sign extend into the upper 32 bits,
604 * which is behaviour we don't want */
609 cmpb,COND(<>),n \tmp,\tmp1,\fault
610 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
611 depd,z \prot,8,7,\prot
613 * OK, it is in the temp alias region, check whether "from" or "to".
614 * Check "subtle" note in pacache.S re: r23/r26.
617 extrd,u,*= \va,41,1,%r0
619 extrw,u,= \va,9,1,%r0
621 or,COND(tr) %r23,%r0,\pte
627 * Align fault_vector_20 on 4K boundary so that both
628 * fault_vector_11 and fault_vector_20 are on the
629 * same page. This is only necessary as long as we
630 * write protect the kernel text, which we may stop
631 * doing once we use large page translations to cover
632 * the static part of the kernel address space.
639 ENTRY(fault_vector_20)
640 /* First vector is invalid (0) */
641 .ascii "cows can fly"
686 ENTRY(fault_vector_11)
687 /* First vector is invalid (0) */
688 .ascii "cows can fly"
731 .import handle_interruption,code
732 .import do_cpu_irq_mask,code
735 * r26 = function to be called
736 * r25 = argument to pass in
737 * r24 = flags for do_fork()
739 * Kernel threads don't ever return, so they don't need
740 * a true register context. We just save away the arguments
741 * for copy_thread/ret_ to properly set up the child.
744 #define CLONE_VM 0x100 /* Must agree with <linux/sched.h> */
745 #define CLONE_UNTRACED 0x00800000
748 ENTRY(__kernel_thread)
749 STREG %r2, -RP_OFFSET(%r30)
752 ldo PT_SZ_ALGN(%r30),%r30
754 /* Yo, function pointers in wide mode are little structs... -PB */
756 STREG %r2, PT_GR27(%r1) /* Store childs %dp */
759 STREG %r22, PT_GR22(%r1) /* save r22 (arg5) */
760 copy %r0, %r22 /* user_tid */
762 STREG %r26, PT_GR26(%r1) /* Store function & argument for child */
763 STREG %r25, PT_GR25(%r1)
764 ldil L%CLONE_UNTRACED, %r26
765 ldo CLONE_VM(%r26), %r26 /* Force CLONE_VM since only init_mm */
766 or %r26, %r24, %r26 /* will have kernel mappings. */
767 ldi 1, %r25 /* stack_start, signals kernel thread */
768 stw %r0, -52(%r30) /* user_tid */
770 ldo -16(%r30),%r29 /* Reference param save area */
773 copy %r1, %r24 /* pt_regs */
775 /* Parent Returns here */
777 LDREG -PT_SZ_ALGN-RP_OFFSET(%r30), %r2
778 ldo -PT_SZ_ALGN(%r30), %r30
781 ENDPROC(__kernel_thread)
786 * copy_thread moved args from temp save area set up above
787 * into task save area.
790 ENTRY(ret_from_kernel_thread)
792 /* Call schedule_tail first though */
793 BL schedule_tail, %r2
796 LDREG TI_TASK-THREAD_SZ_ALGN(%r30), %r1
797 LDREG TASK_PT_GR25(%r1), %r26
799 LDREG TASK_PT_GR27(%r1), %r27
800 LDREG TASK_PT_GR22(%r1), %r22
802 LDREG TASK_PT_GR26(%r1), %r1
807 ldo -16(%r30),%r29 /* Reference param save area */
808 loadgp /* Thread could have been in a module */
817 ENDPROC(ret_from_kernel_thread)
819 .import sys_execve, code
823 ldo PT_SZ_ALGN(%r30), %r30
824 STREG %r26, PT_GR26(%r16)
825 STREG %r25, PT_GR25(%r16)
826 STREG %r24, PT_GR24(%r16)
828 ldo -16(%r30),%r29 /* Reference param save area */
833 cmpib,=,n 0,%r28,intr_return /* forward */
835 /* yes, this will trap and die. */
844 * struct task_struct *_switch_to(struct task_struct *prev,
845 * struct task_struct *next)
847 * switch kernel stacks and return prev */
849 STREG %r2, -RP_OFFSET(%r30)
854 load32 _switch_to_ret, %r2
856 STREG %r2, TASK_PT_KPC(%r26)
857 LDREG TASK_PT_KPC(%r25), %r2
859 STREG %r30, TASK_PT_KSP(%r26)
860 LDREG TASK_PT_KSP(%r25), %r30
861 LDREG TASK_THREAD_INFO(%r25), %r25
866 mtctl %r0, %cr0 /* Needed for single stepping */
870 LDREG -RP_OFFSET(%r30), %r2
876 * Common rfi return path for interruptions, kernel execve, and
877 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
878 * return via this path if the signal was received when the process
879 * was running; if the process was blocked on a syscall then the
880 * normal syscall_exit path is used. All syscalls for traced
881 * proceses exit via intr_restore.
883 * XXX If any syscalls that change a processes space id ever exit
884 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
891 ENTRY(syscall_exit_rfi)
893 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
894 ldo TASK_REGS(%r16),%r16
895 /* Force iaoq to userspace, as the user has had access to our current
896 * context via sigcontext. Also Filter the PSW for the same reason.
898 LDREG PT_IAOQ0(%r16),%r19
900 STREG %r19,PT_IAOQ0(%r16)
901 LDREG PT_IAOQ1(%r16),%r19
903 STREG %r19,PT_IAOQ1(%r16)
904 LDREG PT_PSW(%r16),%r19
905 load32 USER_PSW_MASK,%r1
907 load32 USER_PSW_HI_MASK,%r20
910 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
912 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
913 STREG %r19,PT_PSW(%r16)
916 * If we aren't being traced, we never saved space registers
917 * (we don't store them in the sigcontext), so set them
918 * to "proper" values now (otherwise we'll wind up restoring
919 * whatever was last stored in the task structure, which might
920 * be inconsistent if an interrupt occured while on the gateway
921 * page). Note that we may be "trashing" values the user put in
922 * them, but we don't support the user changing them.
925 STREG %r0,PT_SR2(%r16)
927 STREG %r19,PT_SR0(%r16)
928 STREG %r19,PT_SR1(%r16)
929 STREG %r19,PT_SR3(%r16)
930 STREG %r19,PT_SR4(%r16)
931 STREG %r19,PT_SR5(%r16)
932 STREG %r19,PT_SR6(%r16)
933 STREG %r19,PT_SR7(%r16)
936 /* NOTE: Need to enable interrupts incase we schedule. */
941 /* check for reschedule */
943 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
944 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
946 .import do_notify_resume,code
950 LDREG TI_FLAGS(%r1),%r19
951 ldi (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK|_TIF_NOTIFY_RESUME), %r20
952 and,COND(<>) %r19, %r20, %r0
953 b,n intr_restore /* skip past if we've nothing to do */
955 /* This check is critical to having LWS
956 * working. The IASQ is zero on the gateway
957 * page and we cannot deliver any signals until
958 * we get off the gateway page.
960 * Only do signals if we are returning to user space
962 LDREG PT_IASQ0(%r16), %r20
963 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
964 LDREG PT_IASQ1(%r16), %r20
965 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
967 copy %r0, %r25 /* long in_syscall = 0 */
969 ldo -16(%r30),%r29 /* Reference param save area */
972 BL do_notify_resume,%r2
973 copy %r16, %r26 /* struct pt_regs *regs */
979 ldo PT_FR31(%r29),%r1
983 /* inverse of virt_map */
985 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
988 /* Restore space id's and special cr's from PT_REGS
989 * structure pointed to by r29
993 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
994 * It also restores r1 and r30.
1001 #ifndef CONFIG_PREEMPT
1002 # define intr_do_preempt intr_restore
1003 #endif /* !CONFIG_PREEMPT */
1005 .import schedule,code
1007 /* Only call schedule on return to userspace. If we're returning
1008 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
1009 * we jump back to intr_restore.
1011 LDREG PT_IASQ0(%r16), %r20
1012 cmpib,COND(=) 0, %r20, intr_do_preempt
1014 LDREG PT_IASQ1(%r16), %r20
1015 cmpib,COND(=) 0, %r20, intr_do_preempt
1019 ldo -16(%r30),%r29 /* Reference param save area */
1022 ldil L%intr_check_sig, %r2
1023 #ifndef CONFIG_64BIT
1026 load32 schedule, %r20
1029 ldo R%intr_check_sig(%r2), %r2
1031 /* preempt the current task on returning to kernel
1032 * mode from an interrupt, iff need_resched is set,
1033 * and preempt_count is 0. otherwise, we continue on
1034 * our merry way back to the current running task.
1036 #ifdef CONFIG_PREEMPT
1037 .import preempt_schedule_irq,code
1039 rsm PSW_SM_I, %r0 /* disable interrupts */
1041 /* current_thread_info()->preempt_count */
1043 LDREG TI_PRE_COUNT(%r1), %r19
1044 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1045 nop /* prev insn branched backwards */
1047 /* check if we interrupted a critical path */
1048 LDREG PT_PSW(%r16), %r20
1049 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1052 BL preempt_schedule_irq, %r2
1055 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1056 #endif /* CONFIG_PREEMPT */
1059 * External interrupts.
1063 cmpib,COND(=),n 0,%r16,1f
1075 ldo PT_FR0(%r29), %r24
1080 copy %r29, %r26 /* arg0 is pt_regs */
1081 copy %r29, %r16 /* save pt_regs */
1083 ldil L%intr_return, %r2
1086 ldo -16(%r30),%r29 /* Reference param save area */
1090 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1091 ENDPROC(syscall_exit_rfi)
1094 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1096 ENTRY(intr_save) /* for os_hpmc */
1098 cmpib,COND(=),n 0,%r16,1f
1110 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1113 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1115 * 2) Once we start executing code above 4 Gb, we need
1116 * to adjust iasq/iaoq here in the same way we
1117 * adjust isr/ior below.
1120 cmpib,COND(=),n 6,%r26,skip_save_ior
1123 mfctl %cr20, %r16 /* isr */
1124 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1125 mfctl %cr21, %r17 /* ior */
1130 * If the interrupted code was running with W bit off (32 bit),
1131 * clear the b bits (bits 0 & 1) in the ior.
1132 * save_specials left ipsw value in r8 for us to test.
1134 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1138 * FIXME: This code has hardwired assumptions about the split
1139 * between space bits and offset bits. This will change
1140 * when we allow alternate page sizes.
1143 /* adjust isr/ior. */
1144 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1145 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1146 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1148 STREG %r16, PT_ISR(%r29)
1149 STREG %r17, PT_IOR(%r29)
1156 ldo PT_FR0(%r29), %r25
1161 copy %r29, %r25 /* arg1 is pt_regs */
1163 ldo -16(%r30),%r29 /* Reference param save area */
1166 ldil L%intr_check_sig, %r2
1167 copy %r25, %r16 /* save pt_regs */
1169 b handle_interruption
1170 ldo R%intr_check_sig(%r2), %r2
1175 * Note for all tlb miss handlers:
1177 * cr24 contains a pointer to the kernel address space
1180 * cr25 contains a pointer to the current user address
1181 * space page directory.
1183 * sr3 will contain the space id of the user address space
1184 * of the current running thread while that thread is
1185 * running in the kernel.
1189 * register number allocations. Note that these are all
1190 * in the shadowed registers
1193 t0 = r1 /* temporary register 0 */
1194 va = r8 /* virtual address for which the trap occured */
1195 t1 = r9 /* temporary register 1 */
1196 pte = r16 /* pte/phys page # */
1197 prot = r17 /* prot bits */
1198 spc = r24 /* space for which the trap occured */
1199 ptp = r25 /* page directory/page table pointer */
1204 space_adjust spc,va,t0
1206 space_check spc,t0,dtlb_fault
1208 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1210 update_ptep ptp,pte,t0,t1
1212 make_insert_tlb spc,pte,prot
1219 dtlb_check_alias_20w:
1220 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1228 space_adjust spc,va,t0
1230 space_check spc,t0,nadtlb_fault
1232 L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w
1234 update_ptep ptp,pte,t0,t1
1236 make_insert_tlb spc,pte,prot
1243 nadtlb_check_flush_20w:
1244 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1246 /* Insert a "flush only" translation */
1251 /* Drop prot bits from pte and convert to page addr for idtlbt */
1252 convert_for_tlb_insert20 pte
1264 space_check spc,t0,dtlb_fault
1266 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1268 update_ptep ptp,pte,t0,t1
1270 make_insert_tlb_11 spc,pte,prot
1272 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1275 idtlba pte,(%sr1,va)
1276 idtlbp prot,(%sr1,va)
1278 mtsp t0, %sr1 /* Restore sr1 */
1283 dtlb_check_alias_11:
1285 /* Check to see if fault is in the temporary alias region */
1287 cmpib,<>,n 0,spc,dtlb_fault /* forward */
1288 ldil L%(TMPALIAS_MAP_START),t0
1291 cmpb,<>,n t0,t1,dtlb_fault /* forward */
1292 ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot
1293 depw,z prot,8,7,prot
1296 * OK, it is in the temp alias region, check whether "from" or "to".
1297 * Check "subtle" note in pacache.S re: r23/r26.
1301 or,tr %r23,%r0,pte /* If "from" use "from" page */
1302 or %r26,%r0,pte /* else "to", use "to" page */
1313 space_check spc,t0,nadtlb_fault
1315 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11
1317 update_ptep ptp,pte,t0,t1
1319 make_insert_tlb_11 spc,pte,prot
1322 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1325 idtlba pte,(%sr1,va)
1326 idtlbp prot,(%sr1,va)
1328 mtsp t0, %sr1 /* Restore sr1 */
1333 nadtlb_check_flush_11:
1334 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1336 /* Insert a "flush only" translation */
1341 /* Get rid of prot bits and convert to page addr for idtlba */
1343 depi 0,31,ASM_PFN_PTE_SHIFT,pte
1344 SHRREG pte,(ASM_PFN_PTE_SHIFT-(31-26)),pte
1346 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1349 idtlba pte,(%sr1,va)
1350 idtlbp prot,(%sr1,va)
1352 mtsp t0, %sr1 /* Restore sr1 */
1358 space_adjust spc,va,t0
1360 space_check spc,t0,dtlb_fault
1362 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1364 update_ptep ptp,pte,t0,t1
1366 make_insert_tlb spc,pte,prot
1375 dtlb_check_alias_20:
1376 do_alias spc,t0,t1,va,pte,prot,dtlb_fault
1386 space_check spc,t0,nadtlb_fault
1388 L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20
1390 update_ptep ptp,pte,t0,t1
1392 make_insert_tlb spc,pte,prot
1401 nadtlb_check_flush_20:
1402 bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
1404 /* Insert a "flush only" translation */
1409 /* Drop prot bits from pte and convert to page addr for idtlbt */
1410 convert_for_tlb_insert20 pte
1421 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1422 * probei instructions. We don't want to fault for these
1423 * instructions (not only does it not make sense, it can cause
1424 * deadlocks, since some flushes are done with the mmap
1425 * semaphore held). If the translation doesn't exist, we can't
1426 * insert a translation, so have to emulate the side effects
1427 * of the instruction. Since we don't insert a translation
1428 * we can get a lot of faults during a flush loop, so it makes
1429 * sense to try to do it here with minimum overhead. We only
1430 * emulate fdc,fic,pdc,probew,prober instructions whose base
1431 * and index registers are not shadowed. We defer everything
1432 * else to the "slow" path.
1435 mfctl %cr19,%r9 /* Get iir */
1437 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1438 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1440 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1443 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1444 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1445 BL get_register,%r25
1446 extrw,u %r9,15,5,%r8 /* Get index register # */
1447 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1449 BL get_register,%r25
1450 extrw,u %r9,10,5,%r8 /* Get base register # */
1451 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1452 BL set_register,%r25
1453 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1458 or %r8,%r9,%r8 /* Set PSW_N */
1465 When there is no translation for the probe address then we
1466 must nullify the insn and return zero in the target regsiter.
1467 This will indicate to the calling code that it does not have
1468 write/read privileges to this address.
1470 This should technically work for prober and probew in PA 1.1,
1471 and also probe,r and probe,w in PA 2.0
1473 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1474 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1480 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1481 BL get_register,%r25 /* Find the target register */
1482 extrw,u %r9,31,5,%r8 /* Get target register */
1483 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1484 BL set_register,%r25
1485 copy %r0,%r1 /* Write zero to target register */
1486 b nadtlb_nullify /* Nullify return insn */
1494 * I miss is a little different, since we allow users to fault
1495 * on the gateway page which is in the kernel address space.
1498 space_adjust spc,va,t0
1500 space_check spc,t0,itlb_fault
1502 L3_ptep ptp,pte,t0,va,itlb_fault
1504 update_ptep ptp,pte,t0,t1
1506 make_insert_tlb spc,pte,prot
1518 space_check spc,t0,itlb_fault
1520 L2_ptep ptp,pte,t0,va,itlb_fault
1522 update_ptep ptp,pte,t0,t1
1524 make_insert_tlb_11 spc,pte,prot
1526 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1529 iitlba pte,(%sr1,va)
1530 iitlbp prot,(%sr1,va)
1532 mtsp t0, %sr1 /* Restore sr1 */
1540 space_check spc,t0,itlb_fault
1542 L2_ptep ptp,pte,t0,va,itlb_fault
1544 update_ptep ptp,pte,t0,t1
1546 make_insert_tlb spc,pte,prot
1560 space_adjust spc,va,t0
1562 space_check spc,t0,dbit_fault
1564 L3_ptep ptp,pte,t0,va,dbit_fault
1567 cmpib,COND(=),n 0,spc,dbit_nolock_20w
1568 load32 PA(pa_dbit_lock),t0
1572 cmpib,COND(=) 0,t1,dbit_spin_20w
1577 update_dirty ptp,pte,t1
1579 make_insert_tlb spc,pte,prot
1583 cmpib,COND(=),n 0,spc,dbit_nounlock_20w
1598 space_check spc,t0,dbit_fault
1600 L2_ptep ptp,pte,t0,va,dbit_fault
1603 cmpib,COND(=),n 0,spc,dbit_nolock_11
1604 load32 PA(pa_dbit_lock),t0
1608 cmpib,= 0,t1,dbit_spin_11
1613 update_dirty ptp,pte,t1
1615 make_insert_tlb_11 spc,pte,prot
1617 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1620 idtlba pte,(%sr1,va)
1621 idtlbp prot,(%sr1,va)
1623 mtsp t1, %sr1 /* Restore sr1 */
1625 cmpib,COND(=),n 0,spc,dbit_nounlock_11
1638 space_check spc,t0,dbit_fault
1640 L2_ptep ptp,pte,t0,va,dbit_fault
1643 cmpib,COND(=),n 0,spc,dbit_nolock_20
1644 load32 PA(pa_dbit_lock),t0
1648 cmpib,= 0,t1,dbit_spin_20
1653 update_dirty ptp,pte,t1
1655 make_insert_tlb spc,pte,prot
1662 cmpib,COND(=),n 0,spc,dbit_nounlock_20
1673 .import handle_interruption,code
1677 ldi 31,%r8 /* Use an unused code */
1695 /* Register saving semantics for system calls:
1697 %r1 clobbered by system call macro in userspace
1698 %r2 saved in PT_REGS by gateway page
1699 %r3 - %r18 preserved by C code (saved by signal code)
1700 %r19 - %r20 saved in PT_REGS by gateway page
1701 %r21 - %r22 non-standard syscall args
1702 stored in kernel stack by gateway page
1703 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1704 %r27 - %r30 saved in PT_REGS by gateway page
1705 %r31 syscall return pointer
1708 /* Floating point registers (FIXME: what do we do with these?)
1710 %fr0 - %fr3 status/exception, not preserved
1711 %fr4 - %fr7 arguments
1712 %fr8 - %fr11 not preserved by C code
1713 %fr12 - %fr21 preserved by C code
1714 %fr22 - %fr31 not preserved by C code
1717 .macro reg_save regs
1718 STREG %r3, PT_GR3(\regs)
1719 STREG %r4, PT_GR4(\regs)
1720 STREG %r5, PT_GR5(\regs)
1721 STREG %r6, PT_GR6(\regs)
1722 STREG %r7, PT_GR7(\regs)
1723 STREG %r8, PT_GR8(\regs)
1724 STREG %r9, PT_GR9(\regs)
1725 STREG %r10,PT_GR10(\regs)
1726 STREG %r11,PT_GR11(\regs)
1727 STREG %r12,PT_GR12(\regs)
1728 STREG %r13,PT_GR13(\regs)
1729 STREG %r14,PT_GR14(\regs)
1730 STREG %r15,PT_GR15(\regs)
1731 STREG %r16,PT_GR16(\regs)
1732 STREG %r17,PT_GR17(\regs)
1733 STREG %r18,PT_GR18(\regs)
1736 .macro reg_restore regs
1737 LDREG PT_GR3(\regs), %r3
1738 LDREG PT_GR4(\regs), %r4
1739 LDREG PT_GR5(\regs), %r5
1740 LDREG PT_GR6(\regs), %r6
1741 LDREG PT_GR7(\regs), %r7
1742 LDREG PT_GR8(\regs), %r8
1743 LDREG PT_GR9(\regs), %r9
1744 LDREG PT_GR10(\regs),%r10
1745 LDREG PT_GR11(\regs),%r11
1746 LDREG PT_GR12(\regs),%r12
1747 LDREG PT_GR13(\regs),%r13
1748 LDREG PT_GR14(\regs),%r14
1749 LDREG PT_GR15(\regs),%r15
1750 LDREG PT_GR16(\regs),%r16
1751 LDREG PT_GR17(\regs),%r17
1752 LDREG PT_GR18(\regs),%r18
1755 ENTRY(sys_fork_wrapper)
1756 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1757 ldo TASK_REGS(%r1),%r1
1760 STREG %r3, PT_CR27(%r1)
1762 STREG %r2,-RP_OFFSET(%r30)
1763 ldo FRAME_SIZE(%r30),%r30
1765 ldo -16(%r30),%r29 /* Reference param save area */
1768 /* These are call-clobbered registers and therefore
1769 also syscall-clobbered (we hope). */
1770 STREG %r2,PT_GR19(%r1) /* save for child */
1771 STREG %r30,PT_GR21(%r1)
1773 LDREG PT_GR30(%r1),%r25
1778 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1780 ldo -FRAME_SIZE(%r30),%r30 /* get the stackframe */
1781 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1782 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1784 LDREG PT_CR27(%r1), %r3
1788 /* strace expects syscall # to be preserved in r20 */
1791 STREG %r20,PT_GR20(%r1)
1792 ENDPROC(sys_fork_wrapper)
1794 /* Set the return value for the child */
1796 BL schedule_tail, %r2
1799 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1800 LDREG TASK_PT_GR19(%r1),%r2
1803 ENDPROC(child_return)
1806 ENTRY(sys_clone_wrapper)
1807 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1808 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1811 STREG %r3, PT_CR27(%r1)
1813 STREG %r2,-RP_OFFSET(%r30)
1814 ldo FRAME_SIZE(%r30),%r30
1816 ldo -16(%r30),%r29 /* Reference param save area */
1819 /* WARNING - Clobbers r19 and r21, userspace must save these! */
1820 STREG %r2,PT_GR19(%r1) /* save for child */
1821 STREG %r30,PT_GR21(%r1)
1826 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1827 ENDPROC(sys_clone_wrapper)
1830 ENTRY(sys_vfork_wrapper)
1831 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1832 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1835 STREG %r3, PT_CR27(%r1)
1837 STREG %r2,-RP_OFFSET(%r30)
1838 ldo FRAME_SIZE(%r30),%r30
1840 ldo -16(%r30),%r29 /* Reference param save area */
1843 STREG %r2,PT_GR19(%r1) /* save for child */
1844 STREG %r30,PT_GR21(%r1)
1850 LDREG -RP_OFFSET-FRAME_SIZE(%r30),%r2
1851 ENDPROC(sys_vfork_wrapper)
1854 .macro execve_wrapper execve
1855 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1856 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1859 * Do we need to save/restore r3-r18 here?
1860 * I don't think so. why would new thread need old
1861 * threads registers?
1864 /* %arg0 - %arg3 are already saved for us. */
1866 STREG %r2,-RP_OFFSET(%r30)
1867 ldo FRAME_SIZE(%r30),%r30
1869 ldo -16(%r30),%r29 /* Reference param save area */
1874 ldo -FRAME_SIZE(%r30),%r30
1875 LDREG -RP_OFFSET(%r30),%r2
1877 /* If exec succeeded we need to load the args */
1880 cmpb,>>= %r28,%r1,error_\execve
1889 ENTRY(sys_execve_wrapper)
1890 execve_wrapper sys_execve
1891 ENDPROC(sys_execve_wrapper)
1894 .import sys32_execve
1895 ENTRY(sys32_execve_wrapper)
1896 execve_wrapper sys32_execve
1897 ENDPROC(sys32_execve_wrapper)
1900 ENTRY(sys_rt_sigreturn_wrapper)
1901 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1902 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1903 /* Don't save regs, we are going to restore them from sigcontext. */
1904 STREG %r2, -RP_OFFSET(%r30)
1906 ldo FRAME_SIZE(%r30), %r30
1907 BL sys_rt_sigreturn,%r2
1908 ldo -16(%r30),%r29 /* Reference param save area */
1910 BL sys_rt_sigreturn,%r2
1911 ldo FRAME_SIZE(%r30), %r30
1914 ldo -FRAME_SIZE(%r30), %r30
1915 LDREG -RP_OFFSET(%r30), %r2
1917 /* FIXME: I think we need to restore a few more things here. */
1918 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1919 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1922 /* If the signal was received while the process was blocked on a
1923 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1924 * take us to syscall_exit_rfi and on to intr_return.
1927 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1928 ENDPROC(sys_rt_sigreturn_wrapper)
1930 ENTRY(sys_sigaltstack_wrapper)
1931 /* Get the user stack pointer */
1932 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1933 ldo TASK_REGS(%r1),%r24 /* get pt regs */
1934 LDREG TASK_PT_GR30(%r24),%r24
1935 STREG %r2, -RP_OFFSET(%r30)
1937 ldo FRAME_SIZE(%r30), %r30
1938 BL do_sigaltstack,%r2
1939 ldo -16(%r30),%r29 /* Reference param save area */
1941 BL do_sigaltstack,%r2
1942 ldo FRAME_SIZE(%r30), %r30
1945 ldo -FRAME_SIZE(%r30), %r30
1946 LDREG -RP_OFFSET(%r30), %r2
1949 ENDPROC(sys_sigaltstack_wrapper)
1952 ENTRY(sys32_sigaltstack_wrapper)
1953 /* Get the user stack pointer */
1954 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
1955 LDREG TASK_PT_GR30(%r24),%r24
1956 STREG %r2, -RP_OFFSET(%r30)
1957 ldo FRAME_SIZE(%r30), %r30
1958 BL do_sigaltstack32,%r2
1959 ldo -16(%r30),%r29 /* Reference param save area */
1961 ldo -FRAME_SIZE(%r30), %r30
1962 LDREG -RP_OFFSET(%r30), %r2
1965 ENDPROC(sys32_sigaltstack_wrapper)
1969 /* NOTE: HP-UX syscalls also come through here
1970 * after hpux_syscall_exit fixes up return
1973 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1974 * via syscall_exit_rfi if the signal was received while the process
1978 /* save return value now */
1981 LDREG TI_TASK(%r1),%r1
1982 STREG %r28,TASK_PT_GR28(%r1)
1985 /* <linux/personality.h> cannot be easily included */
1986 #define PER_HPUX 0x10
1987 ldw TASK_PERSONALITY(%r1),%r19
1989 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1990 ldo -PER_HPUX(%r19), %r19
1991 cmpib,COND(<>),n 0,%r19,1f
1993 /* Save other hpux returns if personality is PER_HPUX */
1994 STREG %r22,TASK_PT_GR22(%r1)
1995 STREG %r29,TASK_PT_GR29(%r1)
1998 #endif /* CONFIG_HPUX */
2000 /* Seems to me that dp could be wrong here, if the syscall involved
2001 * calling a module, and nothing got round to restoring dp on return.
2005 syscall_check_resched:
2007 /* check for reschedule */
2009 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
2010 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
2012 .import do_signal,code
2014 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
2015 ldi (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %r26
2016 and,COND(<>) %r19, %r26, %r0
2017 b,n syscall_restore /* skip past if we've nothing to do */
2020 /* Save callee-save registers (for sigcontext).
2021 * FIXME: After this point the process structure should be
2022 * consistent with all the relevant state of the process
2023 * before the syscall. We need to verify this.
2025 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2026 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
2030 ldo -16(%r30),%r29 /* Reference param save area */
2033 BL do_notify_resume,%r2
2034 ldi 1, %r25 /* long in_syscall = 1 */
2036 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2037 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
2040 b,n syscall_check_sig
2043 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2045 /* Are we being ptraced? */
2046 ldw TASK_FLAGS(%r1),%r19
2047 ldi (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
2048 and,COND(=) %r19,%r2,%r0
2049 b,n syscall_restore_rfi
2051 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
2054 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
2057 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
2058 LDREG TASK_PT_GR19(%r1),%r19
2059 LDREG TASK_PT_GR20(%r1),%r20
2060 LDREG TASK_PT_GR21(%r1),%r21
2061 LDREG TASK_PT_GR22(%r1),%r22
2062 LDREG TASK_PT_GR23(%r1),%r23
2063 LDREG TASK_PT_GR24(%r1),%r24
2064 LDREG TASK_PT_GR25(%r1),%r25
2065 LDREG TASK_PT_GR26(%r1),%r26
2066 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
2067 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
2068 LDREG TASK_PT_GR29(%r1),%r29
2069 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
2071 /* NOTE: We use rsm/ssm pair to make this operation atomic */
2072 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
2074 copy %r1,%r30 /* Restore user sp */
2075 mfsp %sr3,%r1 /* Get user space id */
2076 mtsp %r1,%sr7 /* Restore sr7 */
2079 /* Set sr2 to zero for userspace syscalls to work. */
2081 mtsp %r1,%sr4 /* Restore sr4 */
2082 mtsp %r1,%sr5 /* Restore sr5 */
2083 mtsp %r1,%sr6 /* Restore sr6 */
2085 depi 3,31,2,%r31 /* ensure return to user mode. */
2088 /* decide whether to reset the wide mode bit
2090 * For a syscall, the W bit is stored in the lowest bit
2091 * of sp. Extract it and reset W if it is zero */
2092 extrd,u,*<> %r30,63,1,%r1
2094 /* now reset the lowest bit of sp if it was set */
2097 be,n 0(%sr3,%r31) /* return to user space */
2099 /* We have to return via an RFI, so that PSW T and R bits can be set
2101 * This sets up pt_regs so we can return via intr_restore, which is not
2102 * the most efficient way of doing things, but it works.
2104 syscall_restore_rfi:
2105 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
2106 mtctl %r2,%cr0 /* for immediate trap */
2107 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
2108 ldi 0x0b,%r20 /* Create new PSW */
2109 depi -1,13,1,%r20 /* C, Q, D, and I bits */
2111 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
2112 * set in thread_info.h and converted to PA bitmap
2113 * numbers in asm-offsets.c */
2115 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
2116 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
2117 depi -1,27,1,%r20 /* R bit */
2119 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
2120 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
2121 depi -1,7,1,%r20 /* T bit */
2123 STREG %r20,TASK_PT_PSW(%r1)
2125 /* Always store space registers, since sr3 can be changed (e.g. fork) */
2128 STREG %r25,TASK_PT_SR3(%r1)
2129 STREG %r25,TASK_PT_SR4(%r1)
2130 STREG %r25,TASK_PT_SR5(%r1)
2131 STREG %r25,TASK_PT_SR6(%r1)
2132 STREG %r25,TASK_PT_SR7(%r1)
2133 STREG %r25,TASK_PT_IASQ0(%r1)
2134 STREG %r25,TASK_PT_IASQ1(%r1)
2137 /* Now if old D bit is clear, it means we didn't save all registers
2138 * on syscall entry, so do that now. This only happens on TRACEME
2139 * calls, or if someone attached to us while we were on a syscall.
2140 * We could make this more efficient by not saving r3-r18, but
2141 * then we wouldn't be able to use the common intr_restore path.
2142 * It is only for traced processes anyway, so performance is not
2145 bb,< %r2,30,pt_regs_ok /* Branch if D set */
2146 ldo TASK_REGS(%r1),%r25
2147 reg_save %r25 /* Save r3 to r18 */
2149 /* Save the current sr */
2151 STREG %r2,TASK_PT_SR0(%r1)
2153 /* Save the scratch sr */
2155 STREG %r2,TASK_PT_SR1(%r1)
2157 /* sr2 should be set to zero for userspace syscalls */
2158 STREG %r0,TASK_PT_SR2(%r1)
2161 LDREG TASK_PT_GR31(%r1),%r2
2162 depi 3,31,2,%r2 /* ensure return to user mode. */
2163 STREG %r2,TASK_PT_IAOQ0(%r1)
2165 STREG %r2,TASK_PT_IAOQ1(%r1)
2170 .import schedule,code
2174 ldo -16(%r30),%r29 /* Reference param save area */
2178 b syscall_check_resched /* if resched, we start over again */
2180 ENDPROC(syscall_exit)
2183 #ifdef CONFIG_FUNCTION_TRACER
2184 .import ftrace_function_trampoline,code
2187 b ftrace_function_trampoline
2191 ENTRY(return_to_handler)
2192 load32 return_trampoline, %rp
2195 b ftrace_return_to_handler
2206 ENDPROC(return_to_handler)
2207 #endif /* CONFIG_FUNCTION_TRACER */
2212 * get_register is used by the non access tlb miss handlers to
2213 * copy the value of the general register specified in r8 into
2214 * r1. This routine can't be used for shadowed registers, since
2215 * the rfir will restore the original value. So, for the shadowed
2216 * registers we put a -1 into r1 to indicate that the register
2217 * should not be used (the register being copied could also have
2218 * a -1 in it, but that is OK, it just means that we will have
2219 * to use the slow path instead).
2223 bv %r0(%r25) /* r0 */
2225 bv %r0(%r25) /* r1 - shadowed */
2227 bv %r0(%r25) /* r2 */
2229 bv %r0(%r25) /* r3 */
2231 bv %r0(%r25) /* r4 */
2233 bv %r0(%r25) /* r5 */
2235 bv %r0(%r25) /* r6 */
2237 bv %r0(%r25) /* r7 */
2239 bv %r0(%r25) /* r8 - shadowed */
2241 bv %r0(%r25) /* r9 - shadowed */
2243 bv %r0(%r25) /* r10 */
2245 bv %r0(%r25) /* r11 */
2247 bv %r0(%r25) /* r12 */
2249 bv %r0(%r25) /* r13 */
2251 bv %r0(%r25) /* r14 */
2253 bv %r0(%r25) /* r15 */
2255 bv %r0(%r25) /* r16 - shadowed */
2257 bv %r0(%r25) /* r17 - shadowed */
2259 bv %r0(%r25) /* r18 */
2261 bv %r0(%r25) /* r19 */
2263 bv %r0(%r25) /* r20 */
2265 bv %r0(%r25) /* r21 */
2267 bv %r0(%r25) /* r22 */
2269 bv %r0(%r25) /* r23 */
2271 bv %r0(%r25) /* r24 - shadowed */
2273 bv %r0(%r25) /* r25 - shadowed */
2275 bv %r0(%r25) /* r26 */
2277 bv %r0(%r25) /* r27 */
2279 bv %r0(%r25) /* r28 */
2281 bv %r0(%r25) /* r29 */
2283 bv %r0(%r25) /* r30 */
2285 bv %r0(%r25) /* r31 */
2291 * set_register is used by the non access tlb miss handlers to
2292 * copy the value of r1 into the general register specified in
2297 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2299 bv %r0(%r25) /* r1 */
2301 bv %r0(%r25) /* r2 */
2303 bv %r0(%r25) /* r3 */
2305 bv %r0(%r25) /* r4 */
2307 bv %r0(%r25) /* r5 */
2309 bv %r0(%r25) /* r6 */
2311 bv %r0(%r25) /* r7 */
2313 bv %r0(%r25) /* r8 */
2315 bv %r0(%r25) /* r9 */
2317 bv %r0(%r25) /* r10 */
2319 bv %r0(%r25) /* r11 */
2321 bv %r0(%r25) /* r12 */
2323 bv %r0(%r25) /* r13 */
2325 bv %r0(%r25) /* r14 */
2327 bv %r0(%r25) /* r15 */
2329 bv %r0(%r25) /* r16 */
2331 bv %r0(%r25) /* r17 */
2333 bv %r0(%r25) /* r18 */
2335 bv %r0(%r25) /* r19 */
2337 bv %r0(%r25) /* r20 */
2339 bv %r0(%r25) /* r21 */
2341 bv %r0(%r25) /* r22 */
2343 bv %r0(%r25) /* r23 */
2345 bv %r0(%r25) /* r24 */
2347 bv %r0(%r25) /* r25 */
2349 bv %r0(%r25) /* r26 */
2351 bv %r0(%r25) /* r27 */
2353 bv %r0(%r25) /* r28 */
2355 bv %r0(%r25) /* r29 */
2357 bv %r0(%r25) /* r30 */
2359 bv %r0(%r25) /* r31 */