4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
27 #include <linux/swap.h>
28 #include <linux/smp.h>
29 #include <linux/bootmem.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/blkdev.h> /* for initrd_* */
33 #include <linux/pagemap.h>
34 #include <linux/memblock.h>
36 #include <asm/segment.h>
37 #include <asm/pgalloc.h>
38 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
43 #include <asm/kmap_types.h>
44 #include <asm/fixmap.h>
45 #include <asm/tlbflush.h>
46 #include <asm/sections.h>
50 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
52 static void __init zone_sizes_init(void)
54 unsigned long zones_size[MAX_NR_ZONES];
56 /* Clear the zone sizes */
57 memset(zones_size, 0, sizeof(zones_size));
60 * We use only ZONE_NORMAL
62 zones_size[ZONE_NORMAL] = max_low_pfn;
64 free_area_init(zones_size);
67 extern const char _s_kernel_ro[], _e_kernel_ro[];
70 * Map all physical memory into kernel's address space.
72 * This is explicitly coded for two-level page tables, so if you need
73 * something else then this needs to change.
75 static void __init map_ram(void)
77 unsigned long v, p, e;
83 /* These mark extents of read-only kernel pages...
84 * ...from vmlinux.lds.S
86 struct memblock_region *region;
90 for_each_memblock(memory, region) {
91 p = (u32) region->base & PAGE_MASK;
92 e = p + (u32) region->size;
95 pge = pgd_offset_k(v);
99 pue = pud_offset(pge, v);
100 pme = pmd_offset(pue, v);
102 if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
103 panic("%s: OR1K kernel hardcoded for "
104 "two-level page tables",
108 /* Alloc one page for holding PTE's... */
109 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
110 set_pmd(pme, __pmd(_KERNPG_TABLE + __pa(pte)));
112 /* Fill the newly allocated page with PTE'S */
113 for (j = 0; p < e && j < PTRS_PER_PGD;
114 v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) {
115 if (v >= (u32) _e_kernel_ro ||
116 v < (u32) _s_kernel_ro)
119 prot = PAGE_KERNEL_RO;
121 set_pte(pte, mk_pte_phys(p, prot));
127 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
128 region->base, region->base + region->size);
132 void __init paging_init(void)
134 extern void tlb_init(void);
139 printk(KERN_INFO "Setting up paging and PTEs.\n");
141 /* clear out the init_mm.pgd that will contain the kernel's mappings */
143 for (i = 0; i < PTRS_PER_PGD; i++)
144 swapper_pg_dir[i] = __pgd(0);
146 /* make sure the current pgd table points to something sane
147 * (even if it is most probably not used until the next
150 current_pgd = init_mm.pgd;
152 end = (unsigned long)__va(max_low_pfn * PAGE_SIZE);
158 /* self modifying code ;) */
159 /* Since the old TLB miss handler has been running up until now,
160 * the kernel pages are still all RW, so we can still modify the
161 * text directly... after this change and a TLB flush, the kernel
162 * pages will become RO.
165 extern unsigned long dtlb_miss_handler;
166 extern unsigned long itlb_miss_handler;
168 unsigned long *dtlb_vector = __va(0x900);
169 unsigned long *itlb_vector = __va(0xa00);
171 printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
172 *itlb_vector = ((unsigned long)&itlb_miss_handler -
173 (unsigned long)itlb_vector) >> 2;
175 /* Soft ordering constraint to ensure that dtlb_vector is
176 * the last thing updated
180 printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler);
181 *dtlb_vector = ((unsigned long)&dtlb_miss_handler -
182 (unsigned long)dtlb_vector) >> 2;
186 /* Soft ordering constraint to ensure that cache invalidation and
187 * TLB flush really happen _after_ code has been modified.
191 /* Invalidate instruction caches after code modification */
192 mtspr(SPR_ICBIR, 0x900);
193 mtspr(SPR_ICBIR, 0xa00);
195 /* New TLB miss handlers and kernel page tables are in now place.
196 * Make sure that page flags get updated for all pages in TLB by
197 * flushing the TLB and forcing all TLB entries to be recreated
198 * from their page table flags.
203 /* References to section boundaries */
205 void __init mem_init(void)
209 max_mapnr = max_low_pfn;
210 high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
212 /* clear the zero-page */
213 memset((void *)empty_zero_page, 0, PAGE_SIZE);
215 /* this will put all low memory onto the freelists */
218 mem_init_print_info(NULL);
220 printk("mem_init_done ...........................................\n");
225 #ifdef CONFIG_BLK_DEV_INITRD
226 void free_initrd_mem(unsigned long start, unsigned long end)
228 free_reserved_area((void *)start, (void *)end, -1, "initrd");
232 void free_initmem(void)
234 free_initmem_default(-1);