1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/types.h>
20 #include <linux/ptrace.h>
21 #include <linux/mman.h>
23 #include <linux/swap.h>
24 #include <linux/smp.h>
25 #include <linux/memblock.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/blkdev.h> /* for initrd_* */
29 #include <linux/pagemap.h>
31 #include <asm/pgalloc.h>
35 #include <asm/mmu_context.h>
36 #include <asm/kmap_types.h>
37 #include <asm/fixmap.h>
38 #include <asm/tlbflush.h>
39 #include <asm/sections.h>
43 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
45 static void __init zone_sizes_init(void)
47 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
50 * We use only ZONE_NORMAL
52 max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
54 free_area_init(max_zone_pfn);
57 extern const char _s_kernel_ro[], _e_kernel_ro[];
60 * Map all physical memory into kernel's address space.
62 * This is explicitly coded for two-level page tables, so if you need
63 * something else then this needs to change.
65 static void __init map_ram(void)
67 unsigned long v, p, e;
74 /* These mark extents of read-only kernel pages...
75 * ...from vmlinux.lds.S
77 struct memblock_region *region;
81 for_each_memblock(memory, region) {
82 p = (u32) region->base & PAGE_MASK;
83 e = p + (u32) region->size;
86 pge = pgd_offset_k(v);
90 p4e = p4d_offset(pge, v);
91 pue = pud_offset(p4e, v);
92 pme = pmd_offset(pue, v);
94 if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
95 panic("%s: OR1K kernel hardcoded for "
96 "two-level page tables",
100 /* Alloc one page for holding PTE's... */
101 pte = memblock_alloc_raw(PAGE_SIZE, PAGE_SIZE);
103 panic("%s: Failed to allocate page for PTEs\n",
105 set_pmd(pme, __pmd(_KERNPG_TABLE + __pa(pte)));
107 /* Fill the newly allocated page with PTE'S */
108 for (j = 0; p < e && j < PTRS_PER_PTE;
109 v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) {
110 if (v >= (u32) _e_kernel_ro ||
111 v < (u32) _s_kernel_ro)
114 prot = PAGE_KERNEL_RO;
116 set_pte(pte, mk_pte_phys(p, prot));
122 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__,
123 region->base, region->base + region->size);
127 void __init paging_init(void)
129 extern void tlb_init(void);
134 printk(KERN_INFO "Setting up paging and PTEs.\n");
136 /* clear out the init_mm.pgd that will contain the kernel's mappings */
138 for (i = 0; i < PTRS_PER_PGD; i++)
139 swapper_pg_dir[i] = __pgd(0);
141 /* make sure the current pgd table points to something sane
142 * (even if it is most probably not used until the next
145 current_pgd[smp_processor_id()] = init_mm.pgd;
147 end = (unsigned long)__va(max_low_pfn * PAGE_SIZE);
153 /* self modifying code ;) */
154 /* Since the old TLB miss handler has been running up until now,
155 * the kernel pages are still all RW, so we can still modify the
156 * text directly... after this change and a TLB flush, the kernel
157 * pages will become RO.
160 extern unsigned long dtlb_miss_handler;
161 extern unsigned long itlb_miss_handler;
163 unsigned long *dtlb_vector = __va(0x900);
164 unsigned long *itlb_vector = __va(0xa00);
166 printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
167 *itlb_vector = ((unsigned long)&itlb_miss_handler -
168 (unsigned long)itlb_vector) >> 2;
170 /* Soft ordering constraint to ensure that dtlb_vector is
171 * the last thing updated
175 printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler);
176 *dtlb_vector = ((unsigned long)&dtlb_miss_handler -
177 (unsigned long)dtlb_vector) >> 2;
181 /* Soft ordering constraint to ensure that cache invalidation and
182 * TLB flush really happen _after_ code has been modified.
186 /* Invalidate instruction caches after code modification */
187 mtspr(SPR_ICBIR, 0x900);
188 mtspr(SPR_ICBIR, 0xa00);
190 /* New TLB miss handlers and kernel page tables are in now place.
191 * Make sure that page flags get updated for all pages in TLB by
192 * flushing the TLB and forcing all TLB entries to be recreated
193 * from their page table flags.
198 /* References to section boundaries */
200 void __init mem_init(void)
204 max_mapnr = max_low_pfn;
205 high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
207 /* clear the zero-page */
208 memset((void *)empty_zero_page, 0, PAGE_SIZE);
210 /* this will put all low memory onto the freelists */
213 mem_init_print_info(NULL);
215 printk("mem_init_done ...........................................\n");