1 // SPDX-License-Identifier: GPL-2.0-only
4 * Parts of this file are based on Ralink's 2.6.21 BSP
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/bug.h>
14 #include <linux/slab.h>
15 #include <linux/sys_soc.h>
17 #include <asm/mipsregs.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7620.h>
25 #define PMU_SW_SET BIT(28)
26 #define A_DCDC_EN BIT(24)
27 #define A_SSC_PERI BIT(19)
28 #define A_SSC_GEN BIT(18)
33 #define A_VTUNE_M 0xff
37 #define DIG_SW_SEL BIT(25)
40 #define EFUSE_MT7688 0x100000
43 #define DRAM_TYPE_MT7628_MASK 0x1
45 /* does the board have sdram or ddram */
48 static struct ralink_soc_info *soc_info_ptr;
51 mt7620_dram_init(struct ralink_soc_info *soc_info)
54 case SYSCFG0_DRAM_TYPE_SDRAM:
55 pr_info("Board has SDRAM\n");
56 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
57 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
60 case SYSCFG0_DRAM_TYPE_DDR1:
61 pr_info("Board has DDR1\n");
62 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
63 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
66 case SYSCFG0_DRAM_TYPE_DDR2:
67 pr_info("Board has DDR2\n");
68 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
69 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
77 mt7628_dram_init(struct ralink_soc_info *soc_info)
80 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
81 pr_info("Board has DDR1\n");
82 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
83 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
86 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
87 pr_info("Board has DDR2\n");
88 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
89 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
96 static unsigned int __init mt7620_get_soc_name0(void)
98 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);
101 static unsigned int __init mt7620_get_soc_name1(void)
103 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);
106 static bool __init mt7620_soc_valid(void)
108 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
109 mt7620_get_soc_name1() == MT7620_CHIP_NAME1)
115 static bool __init mt7628_soc_valid(void)
117 if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
118 mt7620_get_soc_name1() == MT7628_CHIP_NAME1)
124 static unsigned int __init mt7620_get_rev(void)
126 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);
129 static unsigned int __init mt7620_get_bga(void)
131 return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
134 static unsigned int __init mt7620_get_efuse(void)
136 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);
139 static unsigned int __init mt7620_get_soc_ver(void)
141 return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
144 static unsigned int __init mt7620_get_soc_eco(void)
146 return (mt7620_get_rev() & CHIP_REV_ECO_MASK);
149 static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info)
151 if (mt7620_soc_valid()) {
152 u32 bga = mt7620_get_bga();
155 ralink_soc = MT762X_SOC_MT7620A;
156 soc_info->compatible = "ralink,mt7620a-soc";
159 ralink_soc = MT762X_SOC_MT7620N;
160 soc_info->compatible = "ralink,mt7620n-soc";
163 } else if (mt7628_soc_valid()) {
164 u32 efuse = mt7620_get_efuse();
165 unsigned char *name = NULL;
167 if (efuse & EFUSE_MT7688) {
168 ralink_soc = MT762X_SOC_MT7688;
171 ralink_soc = MT762X_SOC_MT7628AN;
174 soc_info->compatible = "ralink,mt7628an-soc";
177 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n",
178 mt7620_get_soc_name0(), mt7620_get_soc_name1());
182 static const char __init *mt7620_get_soc_id_name(void)
184 if (ralink_soc == MT762X_SOC_MT7620A)
186 else if (ralink_soc == MT762X_SOC_MT7620N)
188 else if (ralink_soc == MT762X_SOC_MT7688)
190 else if (ralink_soc == MT762X_SOC_MT7628AN)
196 static int __init mt7620_soc_dev_init(void)
198 struct soc_device *soc_dev;
199 struct soc_device_attribute *soc_dev_attr;
201 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
205 soc_dev_attr->family = "Ralink";
206 soc_dev_attr->soc_id = mt7620_get_soc_id_name();
208 soc_dev_attr->data = soc_info_ptr;
210 soc_dev = soc_device_register(soc_dev_attr);
211 if (IS_ERR(soc_dev)) {
213 return PTR_ERR(soc_dev);
218 device_initcall(mt7620_soc_dev_init);
220 void __init prom_soc_init(struct ralink_soc_info *soc_info)
222 const char *name = mt7620_get_soc_name(soc_info);
227 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
228 "MediaTek %s ver:%u eco:%u",
229 name, mt7620_get_soc_ver(), mt7620_get_soc_eco());
231 cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);
233 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
235 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
236 SYSCFG0_DRAM_TYPE_MASK;
237 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
238 dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
241 soc_info->mem_base = MT7620_DRAM_BASE;
243 mt7628_dram_init(soc_info);
245 mt7620_dram_init(soc_info);
247 pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);
248 pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);
250 pr_info("Analog PMU set to %s control\n",
251 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
252 pr_info("Digital PMU set to %s control\n",
253 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
255 soc_info_ptr = soc_info;