arch/mips/pci/pci-vr41xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
   4  *
   5  *  Copyright (C) 2001-2003 MontaVista Software Inc.
   6  *    Author: Yoichi Yuasa <source@mvista.com>
   7  *  Copyright (C) 2004-2008  Yoichi Yuasa <yuasa@linux-mips.org>
   8  *  Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   9  */
  10 /*
  11  * Changes:
  12  *  MontaVista Software Inc. <source@mvista.com>
  13  *  - New creation, NEC VR4122 and VR4131 are supported.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/cpu.h>
  20 #include <asm/io.h>
  21 #include <asm/vr41xx/pci.h>
  22 #include <asm/vr41xx/vr41xx.h>
  23
  24 #include "pci-vr41xx.h"
  25
  26 extern struct pci_ops vr41xx_pci_ops;
  27
  28 static void __iomem *pciu_base;
  29
  30 #define pciu_read(offset)               readl(pciu_base + (offset))
  31 #define pciu_write(offset, value)       writel((value), pciu_base + (offset))
  32
  33 static struct pci_master_address_conversion pci_master_memory1 = {
  34         .bus_base_address       = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
  35         .address_mask           = PCI_MASTER_MEM1_ADDRESS_MASK,
  36         .pci_base_address       = PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
  37 };
  38
  39 static struct pci_target_address_conversion pci_target_memory1 = {
  40         .address_mask           = PCI_TARGET_MEM1_ADDRESS_MASK,
  41         .bus_base_address       = PCI_TARGET_MEM1_BUS_BASE_ADDRESS,
  42 };
  43
  44 static struct pci_master_address_conversion pci_master_io = {
  45         .bus_base_address       = PCI_MASTER_IO_BUS_BASE_ADDRESS,
  46         .address_mask           = PCI_MASTER_IO_ADDRESS_MASK,
  47         .pci_base_address       = PCI_MASTER_IO_PCI_BASE_ADDRESS,
  48 };
  49
  50 static struct pci_mailbox_address pci_mailbox = {
  51         .base_address           = PCI_MAILBOX_BASE_ADDRESS,
  52 };
  53
  54 static struct pci_target_address_window pci_target_window1 = {
  55         .base_address           = PCI_TARGET_WINDOW1_BASE_ADDRESS,
  56 };
  57
  58 static struct resource pci_mem_resource = {
  59         .name   = "PCI Memory resources",
  60         .start  = PCI_MEM_RESOURCE_START,
  61         .end    = PCI_MEM_RESOURCE_END,
  62         .flags  = IORESOURCE_MEM,
  63 };
  64
  65 static struct resource pci_io_resource = {
  66         .name   = "PCI I/O resources",
  67         .start  = PCI_IO_RESOURCE_START,
  68         .end    = PCI_IO_RESOURCE_END,
  69         .flags  = IORESOURCE_IO,
  70 };
  71
  72 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
  73         .master_memory1                         = &pci_master_memory1,
  74         .target_memory1                         = &pci_target_memory1,
  75         .master_io                              = &pci_master_io,
  76         .exclusive_access                       = CANNOT_LOCK_FROM_DEVICE,
  77         .wait_time_limit_from_irdy_to_trdy      = 0,
  78         .mailbox                                = &pci_mailbox,
  79         .target_window1                         = &pci_target_window1,
  80         .master_latency_timer                   = 0x80,
  81         .retry_limit                            = 0,
  82         .arbiter_priority_control               = PCI_ARBITRATION_MODE_FAIR,
  83         .take_away_gnt_mode                     = PCI_TAKE_AWAY_GNT_DISABLE,
  84 };
  85
  86 static struct pci_controller vr41xx_pci_controller = {
  87         .pci_ops        = &vr41xx_pci_ops,
  88         .mem_resource   = &pci_mem_resource,
  89         .io_resource    = &pci_io_resource,
  90 };
  91
  92 void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup)
  93 {
  94         vr41xx_pci_controller_unit_setup = *setup;
  95 }
  96
  97 static int __init vr41xx_pciu_init(void)
  98 {
  99         struct pci_controller_unit_setup *setup;
 100         struct pci_master_address_conversion *master;
 101         struct pci_target_address_conversion *target;
 102         struct pci_mailbox_address *mailbox;
 103         struct pci_target_address_window *window;
 104         unsigned long vtclock, pci_clock_max;
 105         uint32_t val;
 106
 107         setup = &vr41xx_pci_controller_unit_setup;
 108
 109         if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
 110                 return -EBUSY;
 111
 112         pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
 113         if (pciu_base == NULL) {
 114                 release_mem_region(PCIU_BASE, PCIU_SIZE);
 115                 return -EBUSY;
 116         }
 117
 118         /* Disable PCI interrupt */
 119         vr41xx_disable_pciint();
 120
 121         /* Supply VTClock to PCIU */
 122         vr41xx_supply_clock(PCIU_CLOCK);
 123
 124         /* Dummy write, waiting for supply of VTClock. */
 125         vr41xx_disable_pciint();
 126
 127         /* Select PCI clock */
 128         if (setup->pci_clock_max != 0)
 129                 pci_clock_max = setup->pci_clock_max;
 130         else
 131                 pci_clock_max = PCI_CLOCK_MAX;
 132         vtclock = vr41xx_get_vtclock_frequency();
 133         if (vtclock < pci_clock_max)
 134                 pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
 135         else if ((vtclock / 2) < pci_clock_max)
 136                 pciu_write(PCICLKSELREG, HALF_VTCLOCK);
 137         else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
 138                  (vtclock / 3) < pci_clock_max)
 139                 pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
 140         else if ((vtclock / 4) < pci_clock_max)
 141                 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
 142         else {
 143                 printk(KERN_ERR "PCI Clock is over 33MHz.\n");
 144                 iounmap(pciu_base);
 145                 return -EINVAL;
 146         }
 147
 148         /* Supply PCI clock by PCI bus */
 149         vr41xx_supply_clock(PCI_CLOCK);
 150
 151         if (setup->master_memory1 != NULL) {
 152                 master = setup->master_memory1;
 153                 val = IBA(master->bus_base_address) |
 154                       MASTER_MSK(master->address_mask) |
 155                       WINEN |
 156                       PCIA(master->pci_base_address);
 157                 pciu_write(PCIMMAW1REG, val);
 158         } else {
 159                 val = pciu_read(PCIMMAW1REG);
 160                 val &= ~WINEN;
 161                 pciu_write(PCIMMAW1REG, val);
 162         }
 163
 164         if (setup->master_memory2 != NULL) {
 165                 master = setup->master_memory2;
 166                 val = IBA(master->bus_base_address) |
 167                       MASTER_MSK(master->address_mask) |
 168                       WINEN |
 169                       PCIA(master->pci_base_address);
 170                 pciu_write(PCIMMAW2REG, val);
 171         } else {
 172                 val = pciu_read(PCIMMAW2REG);
 173                 val &= ~WINEN;
 174                 pciu_write(PCIMMAW2REG, val);
 175         }
 176
 177         if (setup->target_memory1 != NULL) {
 178                 target = setup->target_memory1;
 179                 val = TARGET_MSK(target->address_mask) |
 180                       WINEN |
 181                       ITA(target->bus_base_address);
 182                 pciu_write(PCITAW1REG, val);
 183         } else {
 184                 val = pciu_read(PCITAW1REG);
 185                 val &= ~WINEN;
 186                 pciu_write(PCITAW1REG, val);
 187         }
 188
 189         if (setup->target_memory2 != NULL) {
 190                 target = setup->target_memory2;
 191                 val = TARGET_MSK(target->address_mask) |
 192                       WINEN |
 193                       ITA(target->bus_base_address);
 194                 pciu_write(PCITAW2REG, val);
 195         } else {
 196                 val = pciu_read(PCITAW2REG);
 197                 val &= ~WINEN;
 198                 pciu_write(PCITAW2REG, val);
 199         }
 200
 201         if (setup->master_io != NULL) {
 202                 master = setup->master_io;
 203                 val = IBA(master->bus_base_address) |
 204                       MASTER_MSK(master->address_mask) |
 205                       WINEN |
 206                       PCIIA(master->pci_base_address);
 207                 pciu_write(PCIMIOAWREG, val);
 208         } else {
 209                 val = pciu_read(PCIMIOAWREG);
 210                 val &= ~WINEN;
 211                 pciu_write(PCIMIOAWREG, val);
 212         }
 213
 214         if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
 215                 pciu_write(PCIEXACCREG, UNLOCK);
 216         else
 217                 pciu_write(PCIEXACCREG, 0);
 218
 219         if (current_cpu_type() == CPU_VR4122)
 220                 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
 221
 222         pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
 223
 224         if (setup->mailbox != NULL) {
 225                 mailbox = setup->mailbox;
 226                 val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
 227                       MSI_MEMORY | PREF_APPROVAL;
 228                 pciu_write(MAILBAREG, val);
 229         }
 230
 231         if (setup->target_window1) {
 232                 window = setup->target_window1;
 233                 val = PMBA(window->base_address) | TYPE_32BITSPACE |
 234                       MSI_MEMORY | PREF_APPROVAL;
 235                 pciu_write(PCIMBA1REG, val);
 236         }
 237
 238         if (setup->target_window2) {
 239                 window = setup->target_window2;
 240                 val = PMBA(window->base_address) | TYPE_32BITSPACE |
 241                       MSI_MEMORY | PREF_APPROVAL;
 242                 pciu_write(PCIMBA2REG, val);
 243         }
 244
 245         val = pciu_read(RETVALREG);
 246         val &= ~RTYVAL_MASK;
 247         val |= RTYVAL(setup->retry_limit);
 248         pciu_write(RETVALREG, val);
 249
 250         val = pciu_read(PCIAPCNTREG);
 251         val &= ~(TKYGNT | PAPC);
 252
 253         switch (setup->arbiter_priority_control) {
 254         case PCI_ARBITRATION_MODE_ALTERNATE_0:
 255                 val |= PAPC_ALTERNATE_0;
 256                 break;
 257         case PCI_ARBITRATION_MODE_ALTERNATE_B:
 258                 val |= PAPC_ALTERNATE_B;
 259                 break;
 260         default:
 261                 val |= PAPC_FAIR;
 262                 break;
 263         }
 264
 265         if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
 266                 val |= TKYGNT_ENABLE;
 267
 268         pciu_write(PCIAPCNTREG, val);
 269
 270         pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 271                                PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
 272                                PCI_COMMAND_SERR);
 273
 274         /* Clear bus error */
 275         pciu_read(BUSERRADREG);
 276
 277         pciu_write(PCIENREG, PCIU_CONFIG_DONE);
 278
 279         if (setup->mem_resource != NULL)
 280                 vr41xx_pci_controller.mem_resource = setup->mem_resource;
 281
 282         if (setup->io_resource != NULL) {
 283                 vr41xx_pci_controller.io_resource = setup->io_resource;
 284         } else {
 285                 set_io_port_base(IO_PORT_BASE);
 286                 ioport_resource.start = IO_PORT_RESOURCE_START;
 287                 ioport_resource.end = IO_PORT_RESOURCE_END;
 288         }
 289
 290         if (setup->master_io) {
 291                 void __iomem *io_map_base;
 292                 struct resource *res = vr41xx_pci_controller.io_resource;
 293                 master = setup->master_io;
 294                 io_map_base = ioremap(master->bus_base_address,
 295                                       resource_size(res));
 296                 if (!io_map_base) {
 297                         iounmap(pciu_base);
 298                         return -EBUSY;
 299                 }
 300
 301                 vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
 302         }
 303
 304         register_pci_controller(&vr41xx_pci_controller);
 305
 306         return 0;
 307 }
 308
 309 arch_initcall(vr41xx_pciu_init);