arch/mips/mti-malta/malta-time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20 #include <linux/types.h>
  21 #include <linux/i8253.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/timex.h>
  28 #include <linux/mc146818rtc.h>
  29
  30 #include <asm/mipsregs.h>
  31 #include <asm/mipsmtregs.h>
  32 #include <asm/hardirq.h>
  33 #include <asm/irq.h>
  34 #include <asm/div64.h>
  35 #include <asm/setup.h>
  36 #include <asm/time.h>
  37 #include <asm/mc146818-time.h>
  38 #include <asm/msc01_ic.h>
  39 #include <asm/gic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/maltaint.h>
  43
  44 unsigned long cpu_khz;
  45 int gic_frequency;
  46
  47 static int mips_cpu_timer_irq;
  48 static int mips_cpu_perf_irq;
  49 extern int cp0_perfcount_irq;
  50
  51 static void mips_timer_dispatch(void)
  52 {
  53         do_IRQ(mips_cpu_timer_irq);
  54 }
  55
  56 static void mips_perf_dispatch(void)
  57 {
  58         do_IRQ(mips_cpu_perf_irq);
  59 }
  60
  61 static unsigned int freqround(unsigned int freq, unsigned int amount)
  62 {
  63         freq += amount;
  64         freq -= freq % (amount*2);
  65         return freq;
  66 }
  67
  68 /*
  69  * Estimate CPU and GIC frequencies.
  70  */
  71 static void __init estimate_frequencies(void)
  72 {
  73         unsigned long flags;
  74         unsigned int count, start;
  75         unsigned int giccount = 0, gicstart = 0;
  76
  77         local_irq_save(flags);
  78
  79         /* Start counter exactly on falling edge of update flag. */
  80         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  81         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  82
  83         /* Initialize counters. */
  84         start = read_c0_count();
  85         if (gic_present)
  86                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
  87
  88         /* Read counter exactly on falling edge of update flag. */
  89         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  90         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  91
  92         count = read_c0_count();
  93         if (gic_present)
  94                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
  95
  96         local_irq_restore(flags);
  97
  98         count -= start;
  99         if (gic_present)
 100                 giccount -= gicstart;
 101
 102         mips_hpt_frequency = count;
 103         if (gic_present)
 104                 gic_frequency = giccount;
 105 }
 106
 107 void read_persistent_clock(struct timespec *ts)
 108 {
 109         ts->tv_sec = mc146818_get_cmos_time();
 110         ts->tv_nsec = 0;
 111 }
 112
 113 static void __init plat_perf_setup(void)
 114 {
 115 #ifdef MSC01E_INT_BASE
 116         if (cpu_has_veic) {
 117                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 118                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 119         } else
 120 #endif
 121         if (cp0_perfcount_irq >= 0) {
 122                 if (cpu_has_vint)
 123                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 124                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 125 #ifdef CONFIG_SMP
 126                 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
 127 #endif
 128         }
 129 }
 130
 131 unsigned int __cpuinit get_c0_compare_int(void)
 132 {
 133 #ifdef MSC01E_INT_BASE
 134         if (cpu_has_veic) {
 135                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 136                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 137         } else
 138 #endif
 139         {
 140                 if (cpu_has_vint)
 141                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 142                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 143         }
 144
 145         return mips_cpu_timer_irq;
 146 }
 147
 148 void __init plat_time_init(void)
 149 {
 150         unsigned int prid = read_c0_prid() & 0xffff00;
 151         unsigned int freq;
 152
 153         estimate_frequencies();
 154
 155         freq = mips_hpt_frequency;
 156         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 157             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 158                 freq *= 2;
 159         freq = freqround(freq, 5000);
 160         pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
 161                (freq%1000000)*100/1000000);
 162         cpu_khz = freq / 1000;
 163
 164         if (gic_present) {
 165                 freq = freqround(gic_frequency, 5000);
 166                 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
 167                        (freq%1000000)*100/1000000);
 168                 gic_clocksource_init(gic_frequency);
 169         } else
 170                 init_r4k_clocksource();
 171
 172 #ifdef CONFIG_I8253
 173         /* Only Malta has a PIT. */
 174         setup_pit_timer();
 175 #endif
 176
 177         mips_scroll_message();
 178
 179         plat_perf_setup();
 180 }