2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/cache.h>
32 #include <asm/cacheflush.h>
33 #include <asm/pgtable.h>
36 #include <asm/setup.h>
39 * TLB load/store/modify handlers.
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
47 struct work_registers {
56 } ____cacheline_aligned_in_smp;
58 static struct tlb_reg_save handler_reg_save[NR_CPUS];
60 static inline int r45k_bvahwbug(void)
62 /* XXX: We should probe for the presence of this bug, but we don't. */
66 static inline int r4k_250MHZhwbug(void)
68 /* XXX: We should probe for the presence of this bug, but we don't. */
72 static inline int __maybe_unused bcm1250_m3_war(void)
74 return BCM1250_M3_WAR;
77 static inline int __maybe_unused r10000_llsc_war(void)
79 return R10000_LLSC_WAR;
82 static int use_bbit_insns(void)
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
94 static int use_lwx_insns(void)
96 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2:
103 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
104 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
105 static bool scratchpad_available(void)
109 static int scratchpad_offset(int i)
112 * CVMSEG starts at address -32768 and extends for
113 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
115 i += 1; /* Kernel use starts at the top and works down. */
116 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
119 static bool scratchpad_available(void)
123 static int scratchpad_offset(int i)
126 /* Really unreachable, but evidently some GCC want this. */
131 * Found by experiment: At least some revisions of the 4kc throw under
132 * some circumstances a machine check exception, triggered by invalid
133 * values in the index register. Delaying the tlbp instruction until
134 * after the next branch, plus adding an additional nop in front of
135 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
136 * why; it's not an issue caused by the core RTL.
139 static int __cpuinit m4kc_tlbp_war(void)
141 return (current_cpu_data.processor_id & 0xffff00) ==
142 (PRID_COMP_MIPS | PRID_IMP_4KC);
145 /* Handle labels (which must be positive integers). */
147 label_second_part = 1,
152 label_split = label_tlbw_hazard_0 + 8,
153 label_tlbl_goaround1,
154 label_tlbl_goaround2,
158 label_smp_pgtable_change,
159 label_r3000_write_probe_fail,
160 label_large_segbits_fault,
161 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
162 label_tlb_huge_update,
166 UASM_L_LA(_second_part)
169 UASM_L_LA(_vmalloc_done)
170 /* _tlbw_hazard_x is handled differently. */
172 UASM_L_LA(_tlbl_goaround1)
173 UASM_L_LA(_tlbl_goaround2)
174 UASM_L_LA(_nopage_tlbl)
175 UASM_L_LA(_nopage_tlbs)
176 UASM_L_LA(_nopage_tlbm)
177 UASM_L_LA(_smp_pgtable_change)
178 UASM_L_LA(_r3000_write_probe_fail)
179 UASM_L_LA(_large_segbits_fault)
180 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
181 UASM_L_LA(_tlb_huge_update)
184 static int __cpuinitdata hazard_instance;
186 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
190 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
197 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
201 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
209 * pgtable bits are assigned dynamically depending on processor feature
210 * and statically based on kernel configuration. This spits out the actual
211 * values the kernel is using. Required to make sense from disassembled
212 * TLB exception handlers.
214 static void output_pgtable_bits_defines(void)
216 #define pr_define(fmt, ...) \
217 pr_debug("#define " fmt, ##__VA_ARGS__)
219 pr_debug("#include <asm/asm.h>\n");
220 pr_debug("#include <asm/regdef.h>\n");
223 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
224 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
225 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
226 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
227 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
228 #ifdef _PAGE_HUGE_SHIFT
229 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
232 #ifdef _PAGE_NO_EXEC_SHIFT
233 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
235 #ifdef _PAGE_NO_READ_SHIFT
236 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
239 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
240 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
241 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
242 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
246 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
250 pr_debug("LEAF(%s)\n", symbol);
252 pr_debug("\t.set push\n");
253 pr_debug("\t.set noreorder\n");
255 for (i = 0; i < count; i++)
256 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
258 pr_debug("\t.set\tpop\n");
260 pr_debug("\tEND(%s)\n", symbol);
263 /* The only general purpose registers allowed in TLB handlers. */
267 /* Some CP0 registers */
268 #define C0_INDEX 0, 0
269 #define C0_ENTRYLO0 2, 0
270 #define C0_TCBIND 2, 2
271 #define C0_ENTRYLO1 3, 0
272 #define C0_CONTEXT 4, 0
273 #define C0_PAGEMASK 5, 0
274 #define C0_BADVADDR 8, 0
275 #define C0_ENTRYHI 10, 0
277 #define C0_XCONTEXT 20, 0
280 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
282 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
285 /* The worst case length of the handler is around 18 instructions for
286 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
287 * Maximum space available is 32 instructions for R3000 and 64
288 * instructions for R4000.
290 * We deliberately chose a buffer size of 128, so we won't scribble
291 * over anything important on overflow before we panic.
293 static u32 tlb_handler[128] __cpuinitdata;
295 /* simply assume worst case size for labels and relocs */
296 static struct uasm_label labels[128] __cpuinitdata;
297 static struct uasm_reloc relocs[128] __cpuinitdata;
300 static int check_for_high_segbits __cpuinitdata;
303 static int check_for_high_segbits __cpuinitdata;
305 static unsigned int kscratch_used_mask __cpuinitdata;
307 static int __cpuinit allocate_kscratch(void)
310 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
317 r--; /* make it zero based */
319 kscratch_used_mask |= (1 << r);
324 static int scratch_reg __cpuinitdata;
325 static int pgd_reg __cpuinitdata;
326 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
328 static struct work_registers __cpuinit build_get_work_registers(u32 **p)
330 struct work_registers r;
332 int smp_processor_id_reg;
333 int smp_processor_id_sel;
334 int smp_processor_id_shift;
336 if (scratch_reg > 0) {
337 /* Save in CPU local C0_KScratch? */
338 UASM_i_MTC0(p, 1, 31, scratch_reg);
345 if (num_possible_cpus() > 1) {
346 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
347 smp_processor_id_shift = 51;
348 smp_processor_id_reg = 20; /* XContext */
349 smp_processor_id_sel = 0;
352 smp_processor_id_shift = 25;
353 smp_processor_id_reg = 4; /* Context */
354 smp_processor_id_sel = 0;
357 smp_processor_id_shift = 26;
358 smp_processor_id_reg = 4; /* Context */
359 smp_processor_id_sel = 0;
362 /* Get smp_processor_id */
363 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
364 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
366 /* handler_reg_save index in K0 */
367 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
369 UASM_i_LA(p, K1, (long)&handler_reg_save);
370 UASM_i_ADDU(p, K0, K0, K1);
372 UASM_i_LA(p, K0, (long)&handler_reg_save);
374 /* K0 now points to save area, save $1 and $2 */
375 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
376 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
384 static void __cpuinit build_restore_work_registers(u32 **p)
386 if (scratch_reg > 0) {
387 UASM_i_MFC0(p, 1, 31, scratch_reg);
390 /* K0 already points to save area, restore $1 and $2 */
391 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
392 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
395 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
398 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
399 * we cannot do r3000 under these circumstances.
401 * Declare pgd_current here instead of including mmu_context.h to avoid type
402 * conflicts for tlbmiss_handler_setup_pgd
404 extern unsigned long pgd_current[];
407 * The R3000 TLB handler is simple.
409 static void __cpuinit build_r3000_tlb_refill_handler(void)
411 long pgdc = (long)pgd_current;
414 memset(tlb_handler, 0, sizeof(tlb_handler));
417 uasm_i_mfc0(&p, K0, C0_BADVADDR);
418 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
419 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
420 uasm_i_srl(&p, K0, K0, 22); /* load delay */
421 uasm_i_sll(&p, K0, K0, 2);
422 uasm_i_addu(&p, K1, K1, K0);
423 uasm_i_mfc0(&p, K0, C0_CONTEXT);
424 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
425 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
426 uasm_i_addu(&p, K1, K1, K0);
427 uasm_i_lw(&p, K0, 0, K1);
428 uasm_i_nop(&p); /* load delay */
429 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
430 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
431 uasm_i_tlbwr(&p); /* cp0 delay */
433 uasm_i_rfe(&p); /* branch delay */
435 if (p > tlb_handler + 32)
436 panic("TLB refill handler space exceeded");
438 pr_debug("Wrote TLB refill handler (%u instructions).\n",
439 (unsigned int)(p - tlb_handler));
441 memcpy((void *)ebase, tlb_handler, 0x80);
443 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
445 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
448 * The R4000 TLB handler is much more complicated. We have two
449 * consecutive handler areas with 32 instructions space each.
450 * Since they aren't used at the same time, we can overflow in the
451 * other one.To keep things simple, we first assume linear space,
452 * then we relocate it to the final handler layout as needed.
454 static u32 final_handler[64] __cpuinitdata;
459 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
460 * 2. A timing hazard exists for the TLBP instruction.
462 * stalling_instruction
465 * The JTLB is being read for the TLBP throughout the stall generated by the
466 * previous instruction. This is not really correct as the stalling instruction
467 * can modify the address used to access the JTLB. The failure symptom is that
468 * the TLBP instruction will use an address created for the stalling instruction
469 * and not the address held in C0_ENHI and thus report the wrong results.
471 * The software work-around is to not allow the instruction preceding the TLBP
472 * to stall - make it an NOP or some other instruction guaranteed not to stall.
474 * Errata 2 will not be fixed. This errata is also on the R5000.
476 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
478 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
480 switch (current_cpu_type()) {
481 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
497 * Write random or indexed TLB entry, and care about the hazards from
498 * the preceding mtc0 and for the following eret.
500 enum tlb_write_entry { tlb_random, tlb_indexed };
502 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
503 struct uasm_reloc **r,
504 enum tlb_write_entry wmode)
506 void(*tlbw)(u32 **) = NULL;
509 case tlb_random: tlbw = uasm_i_tlbwr; break;
510 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
513 if (cpu_has_mips_r2) {
515 * The architecture spec says an ehb is required here,
516 * but a number of cores do not have the hazard and
517 * using an ehb causes an expensive pipeline stall.
519 switch (current_cpu_type()) {
532 switch (current_cpu_type()) {
540 * This branch uses up a mtc0 hazard nop slot and saves
541 * two nops after the tlbw instruction.
543 uasm_bgezl_hazard(p, r, hazard_instance);
545 uasm_bgezl_label(l, p, hazard_instance);
559 uasm_i_nop(p); /* QED specifies 2 nops hazard */
560 uasm_i_nop(p); /* QED specifies 2 nops hazard */
607 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
608 * use of the JTLB for instructions should not occur for 4
609 * cpu cycles and use for data translations should not occur
649 panic("No TLB refill handler yet (CPU type: %d)",
650 current_cpu_data.cputype);
655 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
659 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
661 #ifdef CONFIG_64BIT_PHYS_ADDR
662 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
664 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
669 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
671 static __cpuinit void build_restore_pagemask(u32 **p,
672 struct uasm_reloc **r,
677 if (restore_scratch) {
678 /* Reset default page size */
679 if (PM_DEFAULT_MASK >> 16) {
680 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
681 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
682 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
683 uasm_il_b(p, r, lid);
684 } else if (PM_DEFAULT_MASK) {
685 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
686 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
687 uasm_il_b(p, r, lid);
689 uasm_i_mtc0(p, 0, C0_PAGEMASK);
690 uasm_il_b(p, r, lid);
693 UASM_i_MFC0(p, 1, 31, scratch_reg);
695 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
697 /* Reset default page size */
698 if (PM_DEFAULT_MASK >> 16) {
699 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
700 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
701 uasm_il_b(p, r, lid);
702 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
703 } else if (PM_DEFAULT_MASK) {
704 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
705 uasm_il_b(p, r, lid);
706 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
708 uasm_il_b(p, r, lid);
709 uasm_i_mtc0(p, 0, C0_PAGEMASK);
714 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
715 struct uasm_label **l,
716 struct uasm_reloc **r,
718 enum tlb_write_entry wmode,
721 /* Set huge page tlb entry size */
722 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
723 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
724 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
726 build_tlb_write_entry(p, l, r, wmode);
728 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
732 * Check if Huge PTE is present, if so then jump to LABEL.
734 static void __cpuinit
735 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
736 unsigned int pmd, int lid)
738 UASM_i_LW(p, tmp, 0, pmd);
739 if (use_bbit_insns()) {
740 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
742 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
743 uasm_il_bnez(p, r, tmp, lid);
747 static __cpuinit void build_huge_update_entries(u32 **p,
754 * A huge PTE describes an area the size of the
755 * configured huge page size. This is twice the
756 * of the large TLB entry size we intend to use.
757 * A TLB entry half the size of the configured
758 * huge page size is configured into entrylo0
759 * and entrylo1 to cover the contiguous huge PTE
762 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
764 /* We can clobber tmp. It isn't used after this.*/
766 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
768 build_convert_pte_to_entrylo(p, pte);
769 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
770 /* convert to entrylo1 */
772 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
774 UASM_i_ADDU(p, pte, pte, tmp);
776 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
779 static __cpuinit void build_huge_handler_tail(u32 **p,
780 struct uasm_reloc **r,
781 struct uasm_label **l,
786 UASM_i_SC(p, pte, 0, ptr);
787 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
788 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
790 UASM_i_SW(p, pte, 0, ptr);
792 build_huge_update_entries(p, pte, ptr);
793 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
795 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
799 * TMP and PTR are scratch.
800 * TMP will be clobbered, PTR will hold the pmd entry.
802 static void __cpuinit
803 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
804 unsigned int tmp, unsigned int ptr)
806 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
807 long pgdc = (long)pgd_current;
810 * The vmalloc handling is not in the hotpath.
812 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
814 if (check_for_high_segbits) {
816 * The kernel currently implicitely assumes that the
817 * MIPS SEGBITS parameter for the processor is
818 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
819 * allocate virtual addresses outside the maximum
820 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
821 * that doesn't prevent user code from accessing the
822 * higher xuseg addresses. Here, we make sure that
823 * everything but the lower xuseg addresses goes down
824 * the module_alloc/vmalloc path.
826 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
827 uasm_il_bnez(p, r, ptr, label_vmalloc);
829 uasm_il_bltz(p, r, tmp, label_vmalloc);
831 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
833 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
835 /* pgd is in pgd_reg */
836 UASM_i_MFC0(p, ptr, 31, pgd_reg);
839 * &pgd << 11 stored in CONTEXT [23..63].
841 UASM_i_MFC0(p, ptr, C0_CONTEXT);
843 /* Clear lower 23 bits of context. */
844 uasm_i_dins(p, ptr, 0, 0, 23);
846 /* 1 0 1 0 1 << 6 xkphys cached */
847 uasm_i_ori(p, ptr, ptr, 0x540);
848 uasm_i_drotr(p, ptr, ptr, 11);
850 #elif defined(CONFIG_SMP)
851 # ifdef CONFIG_MIPS_MT_SMTC
853 * SMTC uses TCBind value as "CPU" index
855 uasm_i_mfc0(p, ptr, C0_TCBIND);
856 uasm_i_dsrl_safe(p, ptr, ptr, 19);
859 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
862 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
863 uasm_i_dsrl_safe(p, ptr, ptr, 23);
865 UASM_i_LA_mostly(p, tmp, pgdc);
866 uasm_i_daddu(p, ptr, ptr, tmp);
867 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
868 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
870 UASM_i_LA_mostly(p, ptr, pgdc);
871 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
874 uasm_l_vmalloc_done(l, *p);
876 /* get pgd offset in bytes */
877 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
881 #ifndef __PAGETABLE_PMD_FOLDED
882 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
883 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
884 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
885 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
886 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
891 * BVADDR is the faulting address, PTR is scratch.
892 * PTR will hold the pgd for vmalloc.
894 static void __cpuinit
895 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
896 unsigned int bvaddr, unsigned int ptr,
897 enum vmalloc64_mode mode)
899 long swpd = (long)swapper_pg_dir;
900 int single_insn_swpd;
901 int did_vmalloc_branch = 0;
903 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
905 uasm_l_vmalloc(l, *p);
907 if (mode != not_refill && check_for_high_segbits) {
908 if (single_insn_swpd) {
909 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
910 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
911 did_vmalloc_branch = 1;
914 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
917 if (!did_vmalloc_branch) {
918 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
919 uasm_il_b(p, r, label_vmalloc_done);
920 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
922 UASM_i_LA_mostly(p, ptr, swpd);
923 uasm_il_b(p, r, label_vmalloc_done);
924 if (uasm_in_compat_space_p(swpd))
925 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
927 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
930 if (mode != not_refill && check_for_high_segbits) {
931 uasm_l_large_segbits_fault(l, *p);
933 * We get here if we are an xsseg address, or if we are
934 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
936 * Ignoring xsseg (assume disabled so would generate
937 * (address errors?), the only remaining possibility
938 * is the upper xuseg addresses. On processors with
939 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
940 * addresses would have taken an address error. We try
941 * to mimic that here by taking a load/istream page
944 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
947 if (mode == refill_scratch) {
949 UASM_i_MFC0(p, 1, 31, scratch_reg);
951 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
958 #else /* !CONFIG_64BIT */
961 * TMP and PTR are scratch.
962 * TMP will be clobbered, PTR will hold the pgd entry.
964 static void __cpuinit __maybe_unused
965 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
967 long pgdc = (long)pgd_current;
969 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
971 #ifdef CONFIG_MIPS_MT_SMTC
973 * SMTC uses TCBind value as "CPU" index
975 uasm_i_mfc0(p, ptr, C0_TCBIND);
976 UASM_i_LA_mostly(p, tmp, pgdc);
977 uasm_i_srl(p, ptr, ptr, 19);
980 * smp_processor_id() << 3 is stored in CONTEXT.
982 uasm_i_mfc0(p, ptr, C0_CONTEXT);
983 UASM_i_LA_mostly(p, tmp, pgdc);
984 uasm_i_srl(p, ptr, ptr, 23);
986 uasm_i_addu(p, ptr, tmp, ptr);
988 UASM_i_LA_mostly(p, ptr, pgdc);
990 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
991 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
993 if (cpu_has_mips_r2) {
994 uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT));
995 uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT));
999 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1000 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
1001 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1004 #endif /* !CONFIG_64BIT */
1006 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
1008 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1009 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1011 switch (current_cpu_type()) {
1028 UASM_i_SRL(p, ctx, ctx, shift);
1029 uasm_i_andi(p, ctx, ctx, mask);
1032 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1034 if (cpu_has_mips_r2) {
1035 /* PTE ptr offset is obtained from BadVAddr */
1036 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1037 UASM_i_LW(p, ptr, 0, ptr);
1038 uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
1039 uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
1044 * Bug workaround for the Nevada. It seems as if under certain
1045 * circumstances the move from cp0_context might produce a
1046 * bogus result when the mfc0 instruction and its consumer are
1047 * in a different cacheline or a load instruction, probably any
1048 * memory reference, is between them.
1050 switch (current_cpu_type()) {
1052 UASM_i_LW(p, ptr, 0, ptr);
1053 GET_CONTEXT(p, tmp); /* get context reg */
1057 GET_CONTEXT(p, tmp); /* get context reg */
1058 UASM_i_LW(p, ptr, 0, ptr);
1062 build_adjust_context(p, tmp);
1063 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1066 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
1070 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1071 * Kernel is a special case. Only a few CPUs use it.
1073 #ifdef CONFIG_64BIT_PHYS_ADDR
1074 if (cpu_has_64bits) {
1075 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
1076 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1078 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1079 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1080 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1082 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1083 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1084 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1086 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1088 int pte_off_even = sizeof(pte_t) / 2;
1089 int pte_off_odd = pte_off_even + sizeof(pte_t);
1091 /* The pte entries are pre-shifted */
1092 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1093 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1094 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1095 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1098 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1099 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1100 if (r45k_bvahwbug())
1101 build_tlb_probe_entry(p);
1103 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1104 if (r4k_250MHZhwbug())
1105 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1106 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1107 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1109 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1110 if (r4k_250MHZhwbug())
1111 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1112 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1113 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1114 if (r45k_bvahwbug())
1115 uasm_i_mfc0(p, tmp, C0_INDEX);
1117 if (r4k_250MHZhwbug())
1118 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1119 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1123 struct mips_huge_tlb_info {
1125 int restore_scratch;
1128 static struct mips_huge_tlb_info __cpuinit
1129 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1130 struct uasm_reloc **r, unsigned int tmp,
1131 unsigned int ptr, int c0_scratch)
1133 struct mips_huge_tlb_info rv;
1134 unsigned int even, odd;
1135 int vmalloc_branch_delay_filled = 0;
1136 const int scratch = 1; /* Our extra working register */
1138 rv.huge_pte = scratch;
1139 rv.restore_scratch = 0;
1141 if (check_for_high_segbits) {
1142 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1145 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1147 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1149 if (c0_scratch >= 0)
1150 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1152 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1154 uasm_i_dsrl_safe(p, scratch, tmp,
1155 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1156 uasm_il_bnez(p, r, scratch, label_vmalloc);
1158 if (pgd_reg == -1) {
1159 vmalloc_branch_delay_filled = 1;
1160 /* Clear lower 23 bits of context. */
1161 uasm_i_dins(p, ptr, 0, 0, 23);
1165 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1167 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1169 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1171 if (c0_scratch >= 0)
1172 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1174 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1177 /* Clear lower 23 bits of context. */
1178 uasm_i_dins(p, ptr, 0, 0, 23);
1180 uasm_il_bltz(p, r, tmp, label_vmalloc);
1183 if (pgd_reg == -1) {
1184 vmalloc_branch_delay_filled = 1;
1185 /* 1 0 1 0 1 << 6 xkphys cached */
1186 uasm_i_ori(p, ptr, ptr, 0x540);
1187 uasm_i_drotr(p, ptr, ptr, 11);
1190 #ifdef __PAGETABLE_PMD_FOLDED
1191 #define LOC_PTEP scratch
1193 #define LOC_PTEP ptr
1196 if (!vmalloc_branch_delay_filled)
1197 /* get pgd offset in bytes */
1198 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1200 uasm_l_vmalloc_done(l, *p);
1204 * fall-through case = badvaddr *pgd_current
1205 * vmalloc case = badvaddr swapper_pg_dir
1208 if (vmalloc_branch_delay_filled)
1209 /* get pgd offset in bytes */
1210 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1212 #ifdef __PAGETABLE_PMD_FOLDED
1213 GET_CONTEXT(p, tmp); /* get context reg */
1215 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1217 if (use_lwx_insns()) {
1218 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1220 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1221 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1224 #ifndef __PAGETABLE_PMD_FOLDED
1225 /* get pmd offset in bytes */
1226 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1227 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1228 GET_CONTEXT(p, tmp); /* get context reg */
1230 if (use_lwx_insns()) {
1231 UASM_i_LWX(p, scratch, scratch, ptr);
1233 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1234 UASM_i_LW(p, scratch, 0, ptr);
1237 /* Adjust the context during the load latency. */
1238 build_adjust_context(p, tmp);
1240 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1241 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1243 * The in the LWX case we don't want to do the load in the
1244 * delay slot. It cannot issue in the same cycle and may be
1245 * speculative and unneeded.
1247 if (use_lwx_insns())
1249 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1252 /* build_update_entries */
1253 if (use_lwx_insns()) {
1256 UASM_i_LWX(p, even, scratch, tmp);
1257 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1258 UASM_i_LWX(p, odd, scratch, tmp);
1260 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1263 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1264 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1267 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1268 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1269 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1271 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1272 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1273 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1275 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1277 if (c0_scratch >= 0) {
1278 UASM_i_MFC0(p, scratch, 31, c0_scratch);
1279 build_tlb_write_entry(p, l, r, tlb_random);
1280 uasm_l_leave(l, *p);
1281 rv.restore_scratch = 1;
1282 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1283 build_tlb_write_entry(p, l, r, tlb_random);
1284 uasm_l_leave(l, *p);
1285 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1287 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1288 build_tlb_write_entry(p, l, r, tlb_random);
1289 uasm_l_leave(l, *p);
1290 rv.restore_scratch = 1;
1293 uasm_i_eret(p); /* return from trap */
1299 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1300 * because EXL == 0. If we wrap, we can also use the 32 instruction
1301 * slots before the XTLB refill exception handler which belong to the
1302 * unused TLB refill exception.
1304 #define MIPS64_REFILL_INSNS 32
1306 static void __cpuinit build_r4000_tlb_refill_handler(void)
1308 u32 *p = tlb_handler;
1309 struct uasm_label *l = labels;
1310 struct uasm_reloc *r = relocs;
1312 unsigned int final_len;
1313 struct mips_huge_tlb_info htlb_info __maybe_unused;
1314 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1316 memset(tlb_handler, 0, sizeof(tlb_handler));
1317 memset(labels, 0, sizeof(labels));
1318 memset(relocs, 0, sizeof(relocs));
1319 memset(final_handler, 0, sizeof(final_handler));
1321 if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) {
1322 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1324 vmalloc_mode = refill_scratch;
1326 htlb_info.huge_pte = K0;
1327 htlb_info.restore_scratch = 0;
1328 vmalloc_mode = refill_noscratch;
1330 * create the plain linear handler
1332 if (bcm1250_m3_war()) {
1333 unsigned int segbits = 44;
1335 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1336 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1337 uasm_i_xor(&p, K0, K0, K1);
1338 uasm_i_dsrl_safe(&p, K1, K0, 62);
1339 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1340 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1341 uasm_i_or(&p, K0, K0, K1);
1342 uasm_il_bnez(&p, &r, K0, label_leave);
1343 /* No need for uasm_i_nop */
1347 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1349 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1352 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1353 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1356 build_get_ptep(&p, K0, K1);
1357 build_update_entries(&p, K0, K1);
1358 build_tlb_write_entry(&p, &l, &r, tlb_random);
1359 uasm_l_leave(&l, p);
1360 uasm_i_eret(&p); /* return from trap */
1362 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1363 uasm_l_tlb_huge_update(&l, p);
1364 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1365 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1366 htlb_info.restore_scratch);
1370 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1374 * Overflow check: For the 64bit handler, we need at least one
1375 * free instruction slot for the wrap-around branch. In worst
1376 * case, if the intended insertion point is a delay slot, we
1377 * need three, with the second nop'ed and the third being
1380 /* Loongson2 ebase is different than r4k, we have more space */
1381 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1382 if ((p - tlb_handler) > 64)
1383 panic("TLB refill handler space exceeded");
1385 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1386 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1387 && uasm_insn_has_bdelay(relocs,
1388 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1389 panic("TLB refill handler space exceeded");
1393 * Now fold the handler in the TLB refill handler space.
1395 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1397 /* Simplest case, just copy the handler. */
1398 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1399 final_len = p - tlb_handler;
1400 #else /* CONFIG_64BIT */
1401 f = final_handler + MIPS64_REFILL_INSNS;
1402 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1403 /* Just copy the handler. */
1404 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1405 final_len = p - tlb_handler;
1407 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1408 const enum label_id ls = label_tlb_huge_update;
1410 const enum label_id ls = label_vmalloc;
1416 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1418 BUG_ON(i == ARRAY_SIZE(labels));
1419 split = labels[i].addr;
1422 * See if we have overflown one way or the other.
1424 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1425 split < p - MIPS64_REFILL_INSNS)
1430 * Split two instructions before the end. One
1431 * for the branch and one for the instruction
1432 * in the delay slot.
1434 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1437 * If the branch would fall in a delay slot,
1438 * we must back up an additional instruction
1439 * so that it is no longer in a delay slot.
1441 if (uasm_insn_has_bdelay(relocs, split - 1))
1444 /* Copy first part of the handler. */
1445 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1446 f += split - tlb_handler;
1449 /* Insert branch. */
1450 uasm_l_split(&l, final_handler);
1451 uasm_il_b(&f, &r, label_split);
1452 if (uasm_insn_has_bdelay(relocs, split))
1455 uasm_copy_handler(relocs, labels,
1456 split, split + 1, f);
1457 uasm_move_labels(labels, f, f + 1, -1);
1463 /* Copy the rest of the handler. */
1464 uasm_copy_handler(relocs, labels, split, p, final_handler);
1465 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1468 #endif /* CONFIG_64BIT */
1470 uasm_resolve_relocs(relocs, labels);
1471 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1474 memcpy((void *)ebase, final_handler, 0x100);
1476 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1480 * 128 instructions for the fastpath handler is generous and should
1481 * never be exceeded.
1483 #define FASTPATH_SIZE 128
1485 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1486 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1487 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1488 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1489 u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned;
1491 static void __cpuinit build_r4000_setup_pgd(void)
1495 u32 *p = tlbmiss_handler_setup_pgd;
1496 struct uasm_label *l = labels;
1497 struct uasm_reloc *r = relocs;
1499 memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd));
1500 memset(labels, 0, sizeof(labels));
1501 memset(relocs, 0, sizeof(relocs));
1503 pgd_reg = allocate_kscratch();
1505 if (pgd_reg == -1) {
1506 /* PGD << 11 in c0_Context */
1508 * If it is a ckseg0 address, convert to a physical
1509 * address. Shifting right by 29 and adding 4 will
1510 * result in zero for these addresses.
1513 UASM_i_SRA(&p, a1, a0, 29);
1514 UASM_i_ADDIU(&p, a1, a1, 4);
1515 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1517 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1518 uasm_l_tlbl_goaround1(&l, p);
1519 UASM_i_SLL(&p, a0, a0, 11);
1521 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1523 /* PGD in c0_KScratch */
1525 UASM_i_MTC0(&p, a0, 31, pgd_reg);
1527 if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd))
1528 panic("tlbmiss_handler_setup_pgd space exceeded");
1529 uasm_resolve_relocs(relocs, labels);
1530 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1531 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1533 dump_handler("tlbmiss_handler",
1534 tlbmiss_handler_setup_pgd,
1535 ARRAY_SIZE(tlbmiss_handler_setup_pgd));
1539 static void __cpuinit
1540 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1543 # ifdef CONFIG_64BIT_PHYS_ADDR
1545 uasm_i_lld(p, pte, 0, ptr);
1548 UASM_i_LL(p, pte, 0, ptr);
1550 # ifdef CONFIG_64BIT_PHYS_ADDR
1552 uasm_i_ld(p, pte, 0, ptr);
1555 UASM_i_LW(p, pte, 0, ptr);
1559 static void __cpuinit
1560 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1563 #ifdef CONFIG_64BIT_PHYS_ADDR
1564 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1567 uasm_i_ori(p, pte, pte, mode);
1569 # ifdef CONFIG_64BIT_PHYS_ADDR
1571 uasm_i_scd(p, pte, 0, ptr);
1574 UASM_i_SC(p, pte, 0, ptr);
1576 if (r10000_llsc_war())
1577 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1579 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1581 # ifdef CONFIG_64BIT_PHYS_ADDR
1582 if (!cpu_has_64bits) {
1583 /* no uasm_i_nop needed */
1584 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1585 uasm_i_ori(p, pte, pte, hwmode);
1586 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1587 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1588 /* no uasm_i_nop needed */
1589 uasm_i_lw(p, pte, 0, ptr);
1596 # ifdef CONFIG_64BIT_PHYS_ADDR
1598 uasm_i_sd(p, pte, 0, ptr);
1601 UASM_i_SW(p, pte, 0, ptr);
1603 # ifdef CONFIG_64BIT_PHYS_ADDR
1604 if (!cpu_has_64bits) {
1605 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1606 uasm_i_ori(p, pte, pte, hwmode);
1607 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1608 uasm_i_lw(p, pte, 0, ptr);
1615 * Check if PTE is present, if not then jump to LABEL. PTR points to
1616 * the page table where this PTE is located, PTE will be re-loaded
1617 * with it's original value.
1619 static void __cpuinit
1620 build_pte_present(u32 **p, struct uasm_reloc **r,
1621 int pte, int ptr, int scratch, enum label_id lid)
1623 int t = scratch >= 0 ? scratch : pte;
1626 if (use_bbit_insns()) {
1627 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1630 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1631 uasm_il_beqz(p, r, t, lid);
1633 /* You lose the SMP race :-(*/
1634 iPTE_LW(p, pte, ptr);
1637 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1638 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1639 uasm_il_bnez(p, r, t, lid);
1641 /* You lose the SMP race :-(*/
1642 iPTE_LW(p, pte, ptr);
1646 /* Make PTE valid, store result in PTR. */
1647 static void __cpuinit
1648 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1651 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1653 iPTE_SW(p, r, pte, ptr, mode);
1657 * Check if PTE can be written to, if not branch to LABEL. Regardless
1658 * restore PTE with value from PTR when done.
1660 static void __cpuinit
1661 build_pte_writable(u32 **p, struct uasm_reloc **r,
1662 unsigned int pte, unsigned int ptr, int scratch,
1665 int t = scratch >= 0 ? scratch : pte;
1667 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1668 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1669 uasm_il_bnez(p, r, t, lid);
1671 /* You lose the SMP race :-(*/
1672 iPTE_LW(p, pte, ptr);
1677 /* Make PTE writable, update software status bits as well, then store
1680 static void __cpuinit
1681 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1684 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1687 iPTE_SW(p, r, pte, ptr, mode);
1691 * Check if PTE can be modified, if not branch to LABEL. Regardless
1692 * restore PTE with value from PTR when done.
1694 static void __cpuinit
1695 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1696 unsigned int pte, unsigned int ptr, int scratch,
1699 if (use_bbit_insns()) {
1700 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1703 int t = scratch >= 0 ? scratch : pte;
1704 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1705 uasm_il_beqz(p, r, t, lid);
1707 /* You lose the SMP race :-(*/
1708 iPTE_LW(p, pte, ptr);
1712 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1716 * R3000 style TLB load/store/modify handlers.
1720 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1723 static void __cpuinit
1724 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1726 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1727 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1730 uasm_i_rfe(p); /* branch delay */
1734 * This places the pte into ENTRYLO0 and writes it with tlbwi
1735 * or tlbwr as appropriate. This is because the index register
1736 * may have the probe fail bit set as a result of a trap on a
1737 * kseg2 access, i.e. without refill. Then it returns.
1739 static void __cpuinit
1740 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1741 struct uasm_reloc **r, unsigned int pte,
1744 uasm_i_mfc0(p, tmp, C0_INDEX);
1745 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1746 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1747 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1748 uasm_i_tlbwi(p); /* cp0 delay */
1750 uasm_i_rfe(p); /* branch delay */
1751 uasm_l_r3000_write_probe_fail(l, *p);
1752 uasm_i_tlbwr(p); /* cp0 delay */
1754 uasm_i_rfe(p); /* branch delay */
1757 static void __cpuinit
1758 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1761 long pgdc = (long)pgd_current;
1763 uasm_i_mfc0(p, pte, C0_BADVADDR);
1764 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1765 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1766 uasm_i_srl(p, pte, pte, 22); /* load delay */
1767 uasm_i_sll(p, pte, pte, 2);
1768 uasm_i_addu(p, ptr, ptr, pte);
1769 uasm_i_mfc0(p, pte, C0_CONTEXT);
1770 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1771 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1772 uasm_i_addu(p, ptr, ptr, pte);
1773 uasm_i_lw(p, pte, 0, ptr);
1774 uasm_i_tlbp(p); /* load delay */
1777 static void __cpuinit build_r3000_tlb_load_handler(void)
1779 u32 *p = handle_tlbl;
1780 struct uasm_label *l = labels;
1781 struct uasm_reloc *r = relocs;
1783 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1784 memset(labels, 0, sizeof(labels));
1785 memset(relocs, 0, sizeof(relocs));
1787 build_r3000_tlbchange_handler_head(&p, K0, K1);
1788 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1789 uasm_i_nop(&p); /* load delay */
1790 build_make_valid(&p, &r, K0, K1);
1791 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1793 uasm_l_nopage_tlbl(&l, p);
1794 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1797 if ((p - handle_tlbl) > FASTPATH_SIZE)
1798 panic("TLB load handler fastpath space exceeded");
1800 uasm_resolve_relocs(relocs, labels);
1801 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1802 (unsigned int)(p - handle_tlbl));
1804 dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
1807 static void __cpuinit build_r3000_tlb_store_handler(void)
1809 u32 *p = handle_tlbs;
1810 struct uasm_label *l = labels;
1811 struct uasm_reloc *r = relocs;
1813 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1814 memset(labels, 0, sizeof(labels));
1815 memset(relocs, 0, sizeof(relocs));
1817 build_r3000_tlbchange_handler_head(&p, K0, K1);
1818 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1819 uasm_i_nop(&p); /* load delay */
1820 build_make_write(&p, &r, K0, K1);
1821 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1823 uasm_l_nopage_tlbs(&l, p);
1824 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1827 if ((p - handle_tlbs) > FASTPATH_SIZE)
1828 panic("TLB store handler fastpath space exceeded");
1830 uasm_resolve_relocs(relocs, labels);
1831 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1832 (unsigned int)(p - handle_tlbs));
1834 dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
1837 static void __cpuinit build_r3000_tlb_modify_handler(void)
1839 u32 *p = handle_tlbm;
1840 struct uasm_label *l = labels;
1841 struct uasm_reloc *r = relocs;
1843 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1844 memset(labels, 0, sizeof(labels));
1845 memset(relocs, 0, sizeof(relocs));
1847 build_r3000_tlbchange_handler_head(&p, K0, K1);
1848 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1849 uasm_i_nop(&p); /* load delay */
1850 build_make_write(&p, &r, K0, K1);
1851 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1853 uasm_l_nopage_tlbm(&l, p);
1854 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1857 if ((p - handle_tlbm) > FASTPATH_SIZE)
1858 panic("TLB modify handler fastpath space exceeded");
1860 uasm_resolve_relocs(relocs, labels);
1861 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1862 (unsigned int)(p - handle_tlbm));
1864 dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
1866 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1869 * R4000 style TLB load/store/modify handlers.
1871 static struct work_registers __cpuinit
1872 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1873 struct uasm_reloc **r)
1875 struct work_registers wr = build_get_work_registers(p);
1878 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1880 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1883 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1885 * For huge tlb entries, pmd doesn't contain an address but
1886 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1887 * see if we need to jump to huge tlb processing.
1889 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1892 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1893 UASM_i_LW(p, wr.r2, 0, wr.r2);
1894 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1895 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1896 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1899 uasm_l_smp_pgtable_change(l, *p);
1901 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1902 if (!m4kc_tlbp_war())
1903 build_tlb_probe_entry(p);
1907 static void __cpuinit
1908 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1909 struct uasm_reloc **r, unsigned int tmp,
1912 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1913 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1914 build_update_entries(p, tmp, ptr);
1915 build_tlb_write_entry(p, l, r, tlb_indexed);
1916 uasm_l_leave(l, *p);
1917 build_restore_work_registers(p);
1918 uasm_i_eret(p); /* return from trap */
1921 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1925 static void __cpuinit build_r4000_tlb_load_handler(void)
1927 u32 *p = handle_tlbl;
1928 struct uasm_label *l = labels;
1929 struct uasm_reloc *r = relocs;
1930 struct work_registers wr;
1932 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1933 memset(labels, 0, sizeof(labels));
1934 memset(relocs, 0, sizeof(relocs));
1936 if (bcm1250_m3_war()) {
1937 unsigned int segbits = 44;
1939 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1940 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1941 uasm_i_xor(&p, K0, K0, K1);
1942 uasm_i_dsrl_safe(&p, K1, K0, 62);
1943 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1944 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1945 uasm_i_or(&p, K0, K0, K1);
1946 uasm_il_bnez(&p, &r, K0, label_leave);
1947 /* No need for uasm_i_nop */
1950 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1951 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1952 if (m4kc_tlbp_war())
1953 build_tlb_probe_entry(&p);
1957 * If the page is not _PAGE_VALID, RI or XI could not
1958 * have triggered it. Skip the expensive test..
1960 if (use_bbit_insns()) {
1961 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1962 label_tlbl_goaround1);
1964 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1965 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1970 /* Examine entrylo 0 or 1 based on ptr. */
1971 if (use_bbit_insns()) {
1972 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1974 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1975 uasm_i_beqz(&p, wr.r3, 8);
1977 /* load it in the delay slot*/
1978 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1979 /* load it if ptr is odd */
1980 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1982 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1983 * XI must have triggered it.
1985 if (use_bbit_insns()) {
1986 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1988 uasm_l_tlbl_goaround1(&l, p);
1990 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1991 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1994 uasm_l_tlbl_goaround1(&l, p);
1996 build_make_valid(&p, &r, wr.r1, wr.r2);
1997 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1999 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2001 * This is the entry point when build_r4000_tlbchange_handler_head
2002 * spots a huge page.
2004 uasm_l_tlb_huge_update(&l, p);
2005 iPTE_LW(&p, wr.r1, wr.r2);
2006 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2007 build_tlb_probe_entry(&p);
2011 * If the page is not _PAGE_VALID, RI or XI could not
2012 * have triggered it. Skip the expensive test..
2014 if (use_bbit_insns()) {
2015 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2016 label_tlbl_goaround2);
2018 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2019 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2024 /* Examine entrylo 0 or 1 based on ptr. */
2025 if (use_bbit_insns()) {
2026 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2028 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2029 uasm_i_beqz(&p, wr.r3, 8);
2031 /* load it in the delay slot*/
2032 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2033 /* load it if ptr is odd */
2034 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2036 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2037 * XI must have triggered it.
2039 if (use_bbit_insns()) {
2040 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2042 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2043 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2045 if (PM_DEFAULT_MASK == 0)
2048 * We clobbered C0_PAGEMASK, restore it. On the other branch
2049 * it is restored in build_huge_tlb_write_entry.
2051 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2053 uasm_l_tlbl_goaround2(&l, p);
2055 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2056 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2059 uasm_l_nopage_tlbl(&l, p);
2060 build_restore_work_registers(&p);
2061 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2064 if ((p - handle_tlbl) > FASTPATH_SIZE)
2065 panic("TLB load handler fastpath space exceeded");
2067 uasm_resolve_relocs(relocs, labels);
2068 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2069 (unsigned int)(p - handle_tlbl));
2071 dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
2074 static void __cpuinit build_r4000_tlb_store_handler(void)
2076 u32 *p = handle_tlbs;
2077 struct uasm_label *l = labels;
2078 struct uasm_reloc *r = relocs;
2079 struct work_registers wr;
2081 memset(handle_tlbs, 0, sizeof(handle_tlbs));
2082 memset(labels, 0, sizeof(labels));
2083 memset(relocs, 0, sizeof(relocs));
2085 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2086 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2087 if (m4kc_tlbp_war())
2088 build_tlb_probe_entry(&p);
2089 build_make_write(&p, &r, wr.r1, wr.r2);
2090 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2092 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2094 * This is the entry point when
2095 * build_r4000_tlbchange_handler_head spots a huge page.
2097 uasm_l_tlb_huge_update(&l, p);
2098 iPTE_LW(&p, wr.r1, wr.r2);
2099 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2100 build_tlb_probe_entry(&p);
2101 uasm_i_ori(&p, wr.r1, wr.r1,
2102 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2103 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2106 uasm_l_nopage_tlbs(&l, p);
2107 build_restore_work_registers(&p);
2108 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2111 if ((p - handle_tlbs) > FASTPATH_SIZE)
2112 panic("TLB store handler fastpath space exceeded");
2114 uasm_resolve_relocs(relocs, labels);
2115 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2116 (unsigned int)(p - handle_tlbs));
2118 dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
2121 static void __cpuinit build_r4000_tlb_modify_handler(void)
2123 u32 *p = handle_tlbm;
2124 struct uasm_label *l = labels;
2125 struct uasm_reloc *r = relocs;
2126 struct work_registers wr;
2128 memset(handle_tlbm, 0, sizeof(handle_tlbm));
2129 memset(labels, 0, sizeof(labels));
2130 memset(relocs, 0, sizeof(relocs));
2132 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2133 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2134 if (m4kc_tlbp_war())
2135 build_tlb_probe_entry(&p);
2136 /* Present and writable bits set, set accessed and dirty bits. */
2137 build_make_write(&p, &r, wr.r1, wr.r2);
2138 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2140 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2142 * This is the entry point when
2143 * build_r4000_tlbchange_handler_head spots a huge page.
2145 uasm_l_tlb_huge_update(&l, p);
2146 iPTE_LW(&p, wr.r1, wr.r2);
2147 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2148 build_tlb_probe_entry(&p);
2149 uasm_i_ori(&p, wr.r1, wr.r1,
2150 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2151 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2154 uasm_l_nopage_tlbm(&l, p);
2155 build_restore_work_registers(&p);
2156 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2159 if ((p - handle_tlbm) > FASTPATH_SIZE)
2160 panic("TLB modify handler fastpath space exceeded");
2162 uasm_resolve_relocs(relocs, labels);
2163 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2164 (unsigned int)(p - handle_tlbm));
2166 dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
2169 void __cpuinit build_tlb_refill_handler(void)
2172 * The refill handler is generated per-CPU, multi-node systems
2173 * may have local storage for it. The other handlers are only
2176 static int run_once = 0;
2178 output_pgtable_bits_defines();
2181 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2184 switch (current_cpu_type()) {
2192 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2193 build_r3000_tlb_refill_handler();
2195 build_r3000_tlb_load_handler();
2196 build_r3000_tlb_store_handler();
2197 build_r3000_tlb_modify_handler();
2201 panic("No R3000 TLB refill handler");
2207 panic("No R6000 TLB refill handler yet");
2211 panic("No R8000 TLB refill handler yet");
2216 scratch_reg = allocate_kscratch();
2217 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2218 build_r4000_setup_pgd();
2220 build_r4000_tlb_load_handler();
2221 build_r4000_tlb_store_handler();
2222 build_r4000_tlb_modify_handler();
2225 build_r4000_tlb_refill_handler();
2229 void __cpuinit flush_tlb_handlers(void)
2231 local_flush_icache_range((unsigned long)handle_tlbl,
2232 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
2233 local_flush_icache_range((unsigned long)handle_tlbs,
2234 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
2235 local_flush_icache_range((unsigned long)handle_tlbm,
2236 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
2237 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2238 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2239 (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm));