2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/smp.h>
15 #include <linux/hugetlb.h>
16 #include <linux/module.h>
19 #include <asm/cpu-type.h>
20 #include <asm/bootinfo.h>
21 #include <asm/mmu_context.h>
22 #include <asm/pgtable.h>
24 #include <asm/tlbmisc.h>
26 extern void build_tlb_refill_handler(void);
28 /* Atomicity and interruptability */
29 #ifdef CONFIG_MIPS_MT_SMTC
32 #include <asm/mipsmtregs.h>
34 #define ENTER_CRITICAL(flags) \
36 unsigned int mvpflags; \
37 local_irq_save(flags);\
39 #define EXIT_CRITICAL(flags) \
41 local_irq_restore(flags); \
45 #define ENTER_CRITICAL(flags) local_irq_save(flags)
46 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
48 #endif /* CONFIG_MIPS_MT_SMTC */
51 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
52 * unfortrunately, itlb is not totally transparent to software.
54 static inline void flush_itlb(void)
56 switch (current_cpu_type()) {
65 static inline void flush_itlb_vm(struct vm_area_struct *vma)
67 if (vma->vm_flags & VM_EXEC)
71 void local_flush_tlb_all(void)
74 unsigned long old_ctx;
75 int entry, ftlbhighset;
77 ENTER_CRITICAL(flags);
78 /* Save old context and create impossible VPN2 value */
79 old_ctx = read_c0_entryhi();
83 entry = read_c0_wired();
85 /* Blast 'em all away. */
87 if (current_cpu_data.tlbsizevtlb) {
90 tlbinvf(); /* invalidate VTLB */
92 ftlbhighset = current_cpu_data.tlbsizevtlb +
93 current_cpu_data.tlbsizeftlbsets;
94 for (entry = current_cpu_data.tlbsizevtlb;
97 write_c0_index(entry);
99 tlbinvf(); /* invalidate one FTLB set */
102 while (entry < current_cpu_data.tlbsize) {
103 /* Make sure all entries differ. */
104 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
105 write_c0_index(entry);
112 write_c0_entryhi(old_ctx);
114 EXIT_CRITICAL(flags);
116 EXPORT_SYMBOL(local_flush_tlb_all);
118 /* All entries common to a mm share an asid. To effectively flush
119 these entries, we just bump the asid. */
120 void local_flush_tlb_mm(struct mm_struct *mm)
126 cpu = smp_processor_id();
128 if (cpu_context(cpu, mm) != 0) {
129 drop_mmu_context(mm, cpu);
135 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
138 struct mm_struct *mm = vma->vm_mm;
139 int cpu = smp_processor_id();
141 if (cpu_context(cpu, mm) != 0) {
142 unsigned long size, flags;
144 ENTER_CRITICAL(flags);
145 start = round_down(start, PAGE_SIZE << 1);
146 end = round_up(end, PAGE_SIZE << 1);
147 size = (end - start) >> (PAGE_SHIFT + 1);
148 if (size <= (current_cpu_data.tlbsizeftlbsets ?
149 current_cpu_data.tlbsize / 8 :
150 current_cpu_data.tlbsize / 2)) {
151 int oldpid = read_c0_entryhi();
152 int newpid = cpu_asid(cpu, mm);
154 while (start < end) {
157 write_c0_entryhi(start | newpid);
158 start += (PAGE_SIZE << 1);
162 idx = read_c0_index();
163 write_c0_entrylo0(0);
164 write_c0_entrylo1(0);
167 /* Make sure all entries differ. */
168 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
173 write_c0_entryhi(oldpid);
175 drop_mmu_context(mm, cpu);
178 EXIT_CRITICAL(flags);
182 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
184 unsigned long size, flags;
186 ENTER_CRITICAL(flags);
187 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
188 size = (size + 1) >> 1;
189 if (size <= (current_cpu_data.tlbsizeftlbsets ?
190 current_cpu_data.tlbsize / 8 :
191 current_cpu_data.tlbsize / 2)) {
192 int pid = read_c0_entryhi();
194 start &= (PAGE_MASK << 1);
195 end += ((PAGE_SIZE << 1) - 1);
196 end &= (PAGE_MASK << 1);
198 while (start < end) {
201 write_c0_entryhi(start);
202 start += (PAGE_SIZE << 1);
206 idx = read_c0_index();
207 write_c0_entrylo0(0);
208 write_c0_entrylo1(0);
211 /* Make sure all entries differ. */
212 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
217 write_c0_entryhi(pid);
219 local_flush_tlb_all();
222 EXIT_CRITICAL(flags);
225 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
227 int cpu = smp_processor_id();
229 if (cpu_context(cpu, vma->vm_mm) != 0) {
231 int oldpid, newpid, idx;
233 newpid = cpu_asid(cpu, vma->vm_mm);
234 page &= (PAGE_MASK << 1);
235 ENTER_CRITICAL(flags);
236 oldpid = read_c0_entryhi();
237 write_c0_entryhi(page | newpid);
241 idx = read_c0_index();
242 write_c0_entrylo0(0);
243 write_c0_entrylo1(0);
246 /* Make sure all entries differ. */
247 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
253 write_c0_entryhi(oldpid);
255 EXIT_CRITICAL(flags);
260 * This one is only used for pages with the global bit set so we don't care
261 * much about the ASID.
263 void local_flush_tlb_one(unsigned long page)
268 ENTER_CRITICAL(flags);
269 oldpid = read_c0_entryhi();
270 page &= (PAGE_MASK << 1);
271 write_c0_entryhi(page);
275 idx = read_c0_index();
276 write_c0_entrylo0(0);
277 write_c0_entrylo1(0);
279 /* Make sure all entries differ. */
280 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
285 write_c0_entryhi(oldpid);
287 EXIT_CRITICAL(flags);
291 * We will need multiple versions of update_mmu_cache(), one that just
292 * updates the TLB with the new pte(s), and another which also checks
293 * for the R4k "end of page" hardware bug and does the needy.
295 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
305 * Handle debugger faulting in for debugee.
307 if (current->active_mm != vma->vm_mm)
310 ENTER_CRITICAL(flags);
312 pid = read_c0_entryhi() & ASID_MASK;
313 address &= (PAGE_MASK << 1);
314 write_c0_entryhi(address | pid);
315 pgdp = pgd_offset(vma->vm_mm, address);
319 pudp = pud_offset(pgdp, address);
320 pmdp = pmd_offset(pudp, address);
321 idx = read_c0_index();
322 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
323 /* this could be a huge page */
324 if (pmd_huge(*pmdp)) {
326 write_c0_pagemask(PM_HUGE_MASK);
327 ptep = (pte_t *)pmdp;
328 lo = pte_to_entrylo(pte_val(*ptep));
329 write_c0_entrylo0(lo);
330 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
338 write_c0_pagemask(PM_DEFAULT_MASK);
342 ptep = pte_offset_map(pmdp, address);
344 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
345 write_c0_entrylo0(ptep->pte_high);
347 write_c0_entrylo1(ptep->pte_high);
349 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
350 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
360 EXIT_CRITICAL(flags);
363 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
364 unsigned long entryhi, unsigned long pagemask)
368 unsigned long old_pagemask;
369 unsigned long old_ctx;
371 ENTER_CRITICAL(flags);
372 /* Save old context and create impossible VPN2 value */
373 old_ctx = read_c0_entryhi();
374 old_pagemask = read_c0_pagemask();
375 wired = read_c0_wired();
376 write_c0_wired(wired + 1);
377 write_c0_index(wired);
378 tlbw_use_hazard(); /* What is the hazard here? */
379 write_c0_pagemask(pagemask);
380 write_c0_entryhi(entryhi);
381 write_c0_entrylo0(entrylo0);
382 write_c0_entrylo1(entrylo1);
387 write_c0_entryhi(old_ctx);
388 tlbw_use_hazard(); /* What is the hazard here? */
389 write_c0_pagemask(old_pagemask);
390 local_flush_tlb_all();
391 EXIT_CRITICAL(flags);
394 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
396 int __init has_transparent_hugepage(void)
401 ENTER_CRITICAL(flags);
402 write_c0_pagemask(PM_HUGE_MASK);
403 back_to_back_c0_hazard();
404 mask = read_c0_pagemask();
405 write_c0_pagemask(PM_DEFAULT_MASK);
407 EXIT_CRITICAL(flags);
409 return mask == PM_HUGE_MASK;
412 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
415 static int __init set_ntlb(char *str)
417 get_option(&str, &ntlb);
421 __setup("ntlb=", set_ntlb);
426 * You should never change this register:
427 * - On R4600 1.7 the tlbp never hits for pages smaller than
428 * the value in the c0_pagemask register.
429 * - The entire mm handling assumes the c0_pagemask register to
430 * be set to fixed-size pages.
432 write_c0_pagemask(PM_DEFAULT_MASK);
434 if (current_cpu_type() == CPU_R10000 ||
435 current_cpu_type() == CPU_R12000 ||
436 current_cpu_type() == CPU_R14000)
437 write_c0_framemask(0);
441 * Enable the no read, no exec bits, and enable large virtual
444 u32 pg = PG_RIE | PG_XIE;
448 write_c0_pagegrain(pg);
451 /* From this point on the ARC firmware is dead. */
452 local_flush_tlb_all();
454 /* Did I tell you that ARC SUCKS? */
457 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
458 int wired = current_cpu_data.tlbsize - ntlb;
459 write_c0_wired(wired);
460 write_c0_index(wired-1);
461 printk("Restricting TLB to %d entries\n", ntlb);
463 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
466 build_tlb_refill_handler();