arch/mips/mm/c-tx39.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r2300.c: R2000 and R3000 specific mmu/cache code.
   4  *
   5  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   6  *
   7  * with a lot of changes to make this thing work for R3000s
   8  * Tx39XX R4k style caches added. HK
   9  * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
  10  * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/smp.h>
  16 #include <linux/mm.h>
  17
  18 #include <asm/cacheops.h>
  19 #include <asm/page.h>
  20 #include <asm/mmu_context.h>
  21 #include <asm/isadep.h>
  22 #include <asm/io.h>
  23 #include <asm/bootinfo.h>
  24 #include <asm/cpu.h>
  25
  26 /* For R3000 cores with R4000 style caches */
  27 static unsigned long icache_size, dcache_size;          /* Size in bytes */
  28
  29 #include <asm/r4kcache.h>
  30
  31 /* This sequence is required to ensure icache is disabled immediately */
  32 #define TX39_STOP_STREAMING() \
  33 __asm__ __volatile__( \
  34         ".set    push\n\t" \
  35         ".set    noreorder\n\t" \
  36         "b       1f\n\t" \
  37         "nop\n\t" \
  38         "1:\n\t" \
  39         ".set pop" \
  40         )
  41
  42 /* TX39H-style cache flush routines. */
  43 static void tx39h_flush_icache_all(void)
  44 {
  45         unsigned long flags, config;
  46
  47         /* disable icache (set ICE#) */
  48         local_irq_save(flags);
  49         config = read_c0_conf();
  50         write_c0_conf(config & ~TX39_CONF_ICE);
  51         TX39_STOP_STREAMING();
  52         blast_icache16();
  53         write_c0_conf(config);
  54         local_irq_restore(flags);
  55 }
  56
  57 static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
  58 {
  59         /* Catch bad driver code */
  60         BUG_ON(size == 0);
  61
  62         iob();
  63         blast_inv_dcache_range(addr, addr + size);
  64 }
  65
  66
  67 /* TX39H2,TX39H3 */
  68 static inline void tx39_blast_dcache_page(unsigned long addr)
  69 {
  70         if (current_cpu_type() != CPU_TX3912)
  71                 blast_dcache16_page(addr);
  72 }
  73
  74 static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
  75 {
  76         blast_dcache16_page_indexed(addr);
  77 }
  78
  79 static inline void tx39_blast_dcache(void)
  80 {
  81         blast_dcache16();
  82 }
  83
  84 static inline void tx39_blast_icache_page(unsigned long addr)
  85 {
  86         unsigned long flags, config;
  87         /* disable icache (set ICE#) */
  88         local_irq_save(flags);
  89         config = read_c0_conf();
  90         write_c0_conf(config & ~TX39_CONF_ICE);
  91         TX39_STOP_STREAMING();
  92         blast_icache16_page(addr);
  93         write_c0_conf(config);
  94         local_irq_restore(flags);
  95 }
  96
  97 static inline void tx39_blast_icache_page_indexed(unsigned long addr)
  98 {
  99         unsigned long flags, config;
 100         /* disable icache (set ICE#) */
 101         local_irq_save(flags);
 102         config = read_c0_conf();
 103         write_c0_conf(config & ~TX39_CONF_ICE);
 104         TX39_STOP_STREAMING();
 105         blast_icache16_page_indexed(addr);
 106         write_c0_conf(config);
 107         local_irq_restore(flags);
 108 }
 109
 110 static inline void tx39_blast_icache(void)
 111 {
 112         unsigned long flags, config;
 113         /* disable icache (set ICE#) */
 114         local_irq_save(flags);
 115         config = read_c0_conf();
 116         write_c0_conf(config & ~TX39_CONF_ICE);
 117         TX39_STOP_STREAMING();
 118         blast_icache16();
 119         write_c0_conf(config);
 120         local_irq_restore(flags);
 121 }
 122
 123 static void tx39__flush_cache_vmap(void)
 124 {
 125         tx39_blast_dcache();
 126 }
 127
 128 static void tx39__flush_cache_vunmap(void)
 129 {
 130         tx39_blast_dcache();
 131 }
 132
 133 static inline void tx39_flush_cache_all(void)
 134 {
 135         if (!cpu_has_dc_aliases)
 136                 return;
 137
 138         tx39_blast_dcache();
 139 }
 140
 141 static inline void tx39___flush_cache_all(void)
 142 {
 143         tx39_blast_dcache();
 144         tx39_blast_icache();
 145 }
 146
 147 static void tx39_flush_cache_mm(struct mm_struct *mm)
 148 {
 149         if (!cpu_has_dc_aliases)
 150                 return;
 151
 152         if (cpu_context(smp_processor_id(), mm) != 0)
 153                 tx39_blast_dcache();
 154 }
 155
 156 static void tx39_flush_cache_range(struct vm_area_struct *vma,
 157         unsigned long start, unsigned long end)
 158 {
 159         if (!cpu_has_dc_aliases)
 160                 return;
 161         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 162                 return;
 163
 164         tx39_blast_dcache();
 165 }
 166
 167 static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
 168 {
 169         int exec = vma->vm_flags & VM_EXEC;
 170         struct mm_struct *mm = vma->vm_mm;
 171         pgd_t *pgdp;
 172         p4d_t *p4dp;
 173         pud_t *pudp;
 174         pmd_t *pmdp;
 175         pte_t *ptep;
 176
 177         /*
 178          * If ownes no valid ASID yet, cannot possibly have gotten
 179          * this page into the cache.
 180          */
 181         if (cpu_context(smp_processor_id(), mm) == 0)
 182                 return;
 183
 184         page &= PAGE_MASK;
 185         pgdp = pgd_offset(mm, page);
 186         p4dp = p4d_offset(pgdp, page);
 187         pudp = pud_offset(p4dp, page);
 188         pmdp = pmd_offset(pudp, page);
 189         ptep = pte_offset(pmdp, page);
 190
 191         /*
 192          * If the page isn't marked valid, the page cannot possibly be
 193          * in the cache.
 194          */
 195         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 196                 return;
 197
 198         /*
 199          * Doing flushes for another ASID than the current one is
 200          * too difficult since stupid R4k caches do a TLB translation
 201          * for every cache flush operation.  So we do indexed flushes
 202          * in that case, which doesn't overly flush the cache too much.
 203          */
 204         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 205                 if (cpu_has_dc_aliases || exec)
 206                         tx39_blast_dcache_page(page);
 207                 if (exec)
 208                         tx39_blast_icache_page(page);
 209
 210                 return;
 211         }
 212
 213         /*
 214          * Do indexed flush, too much work to get the (possible) TLB refills
 215          * to work correctly.
 216          */
 217         if (cpu_has_dc_aliases || exec)
 218                 tx39_blast_dcache_page_indexed(page);
 219         if (exec)
 220                 tx39_blast_icache_page_indexed(page);
 221 }
 222
 223 static void local_tx39_flush_data_cache_page(void * addr)
 224 {
 225         tx39_blast_dcache_page((unsigned long)addr);
 226 }
 227
 228 static void tx39_flush_data_cache_page(unsigned long addr)
 229 {
 230         tx39_blast_dcache_page(addr);
 231 }
 232
 233 static void tx39_flush_icache_range(unsigned long start, unsigned long end)
 234 {
 235         if (end - start > dcache_size)
 236                 tx39_blast_dcache();
 237         else
 238                 protected_blast_dcache_range(start, end);
 239
 240         if (end - start > icache_size)
 241                 tx39_blast_icache();
 242         else {
 243                 unsigned long flags, config;
 244                 /* disable icache (set ICE#) */
 245                 local_irq_save(flags);
 246                 config = read_c0_conf();
 247                 write_c0_conf(config & ~TX39_CONF_ICE);
 248                 TX39_STOP_STREAMING();
 249                 protected_blast_icache_range(start, end);
 250                 write_c0_conf(config);
 251                 local_irq_restore(flags);
 252         }
 253 }
 254
 255 static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
 256 {
 257         BUG();
 258 }
 259
 260 static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 261 {
 262         unsigned long end;
 263
 264         if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
 265                 end = addr + size;
 266                 do {
 267                         tx39_blast_dcache_page(addr);
 268                         addr += PAGE_SIZE;
 269                 } while(addr != end);
 270         } else if (size > dcache_size) {
 271                 tx39_blast_dcache();
 272         } else {
 273                 blast_dcache_range(addr, addr + size);
 274         }
 275 }
 276
 277 static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
 278 {
 279         unsigned long end;
 280
 281         if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
 282                 end = addr + size;
 283                 do {
 284                         tx39_blast_dcache_page(addr);
 285                         addr += PAGE_SIZE;
 286                 } while(addr != end);
 287         } else if (size > dcache_size) {
 288                 tx39_blast_dcache();
 289         } else {
 290                 blast_inv_dcache_range(addr, addr + size);
 291         }
 292 }
 293
 294 static __init void tx39_probe_cache(void)
 295 {
 296         unsigned long config;
 297
 298         config = read_c0_conf();
 299
 300         icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
 301                                   TX39_CONF_ICS_SHIFT));
 302         dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
 303                                   TX39_CONF_DCS_SHIFT));
 304
 305         current_cpu_data.icache.linesz = 16;
 306         switch (current_cpu_type()) {
 307         case CPU_TX3912:
 308                 current_cpu_data.icache.ways = 1;
 309                 current_cpu_data.dcache.ways = 1;
 310                 current_cpu_data.dcache.linesz = 4;
 311                 break;
 312
 313         case CPU_TX3927:
 314                 current_cpu_data.icache.ways = 2;
 315                 current_cpu_data.dcache.ways = 2;
 316                 current_cpu_data.dcache.linesz = 16;
 317                 break;
 318
 319         case CPU_TX3922:
 320         default:
 321                 current_cpu_data.icache.ways = 1;
 322                 current_cpu_data.dcache.ways = 1;
 323                 current_cpu_data.dcache.linesz = 16;
 324                 break;
 325         }
 326 }
 327
 328 void tx39_cache_init(void)
 329 {
 330         extern void build_clear_page(void);
 331         extern void build_copy_page(void);
 332         unsigned long config;
 333
 334         config = read_c0_conf();
 335         config &= ~TX39_CONF_WBON;
 336         write_c0_conf(config);
 337
 338         tx39_probe_cache();
 339
 340         switch (current_cpu_type()) {
 341         case CPU_TX3912:
 342                 /* TX39/H core (writethru direct-map cache) */
 343                 __flush_cache_vmap      = tx39__flush_cache_vmap;
 344                 __flush_cache_vunmap    = tx39__flush_cache_vunmap;
 345                 flush_cache_all = tx39h_flush_icache_all;
 346                 __flush_cache_all       = tx39h_flush_icache_all;
 347                 flush_cache_mm          = (void *) tx39h_flush_icache_all;
 348                 flush_cache_range       = (void *) tx39h_flush_icache_all;
 349                 flush_cache_page        = (void *) tx39h_flush_icache_all;
 350                 flush_icache_range      = (void *) tx39h_flush_icache_all;
 351                 local_flush_icache_range = (void *) tx39h_flush_icache_all;
 352
 353                 local_flush_data_cache_page     = (void *) tx39h_flush_icache_all;
 354                 flush_data_cache_page   = (void *) tx39h_flush_icache_all;
 355
 356                 _dma_cache_wback_inv    = tx39h_dma_cache_wback_inv;
 357
 358                 shm_align_mask          = PAGE_SIZE - 1;
 359
 360                 break;
 361
 362         case CPU_TX3922:
 363         case CPU_TX3927:
 364         default:
 365                 /* TX39/H2,H3 core (writeback 2way-set-associative cache) */
 366                 /* board-dependent init code may set WBON */
 367
 368                 __flush_cache_vmap      = tx39__flush_cache_vmap;
 369                 __flush_cache_vunmap    = tx39__flush_cache_vunmap;
 370
 371                 flush_cache_all = tx39_flush_cache_all;
 372                 __flush_cache_all = tx39___flush_cache_all;
 373                 flush_cache_mm = tx39_flush_cache_mm;
 374                 flush_cache_range = tx39_flush_cache_range;
 375                 flush_cache_page = tx39_flush_cache_page;
 376                 flush_icache_range = tx39_flush_icache_range;
 377                 local_flush_icache_range = tx39_flush_icache_range;
 378
 379                 __flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
 380
 381                 local_flush_data_cache_page = local_tx39_flush_data_cache_page;
 382                 flush_data_cache_page = tx39_flush_data_cache_page;
 383
 384                 _dma_cache_wback_inv = tx39_dma_cache_wback_inv;
 385                 _dma_cache_wback = tx39_dma_cache_wback_inv;
 386                 _dma_cache_inv = tx39_dma_cache_inv;
 387
 388                 shm_align_mask = max_t(unsigned long,
 389                                        (dcache_size / current_cpu_data.dcache.ways) - 1,
 390                                        PAGE_SIZE - 1);
 391
 392                 break;
 393         }
 394
 395         __flush_icache_user_range = flush_icache_range;
 396         __local_flush_icache_user_range = local_flush_icache_range;
 397
 398         current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
 399         current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
 400
 401         current_cpu_data.icache.sets =
 402                 current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
 403         current_cpu_data.dcache.sets =
 404                 current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
 405
 406         if (current_cpu_data.dcache.waysize > PAGE_SIZE)
 407                 current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
 408
 409         current_cpu_data.icache.waybit = 0;
 410         current_cpu_data.dcache.waybit = 0;
 411
 412         pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
 413                 icache_size >> 10, current_cpu_data.icache.linesz);
 414         pr_info("Primary data cache %ldkB, linesize %d bytes\n",
 415                 dcache_size >> 10, current_cpu_data.dcache.linesz);
 416
 417         build_clear_page();
 418         build_copy_page();
 419         tx39h_flush_icache_all();
 420 }