arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/export.h>
  21 #include <linux/bitops.h>
  22
  23 #include <asm/bcache.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/cache.h>
  26 #include <asm/cacheops.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpu-features.h>
  29 #include <asm/cpu-type.h>
  30 #include <asm/io.h>
  31 #include <asm/page.h>
  32 #include <asm/r4kcache.h>
  33 #include <asm/sections.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/war.h>
  36 #include <asm/cacheflush.h> /* for run_uncached() */
  37 #include <asm/traps.h>
  38 #include <asm/dma-coherence.h>
  39 #include <asm/mips-cps.h>
  40
  41 /*
  42  * Bits describing what cache ops an SMP callback function may perform.
  43  *
  44  * R4K_HIT   -  Virtual user or kernel address based cache operations. The
  45  *              active_mm must be checked before using user addresses, falling
  46  *              back to kmap.
  47  * R4K_INDEX -  Index based cache operations.
  48  */
  49
  50 #define R4K_HIT         BIT(0)
  51 #define R4K_INDEX       BIT(1)
  52
  53 /**
  54  * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
  55  * @type:       Type of cache operations (R4K_HIT or R4K_INDEX).
  56  *
  57  * Decides whether a cache op needs to be performed on every core in the system.
  58  * This may change depending on the @type of cache operation, as well as the set
  59  * of online CPUs, so preemption should be disabled by the caller to prevent CPU
  60  * hotplug from changing the result.
  61  *
  62  * Returns:     1 if the cache operation @type should be done on every core in
  63  *              the system.
  64  *              0 if the cache operation @type is globalized and only needs to
  65  *              be performed on a simple CPU.
  66  */
  67 static inline bool r4k_op_needs_ipi(unsigned int type)
  68 {
  69         /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
  70         if (type == R4K_HIT && mips_cm_present())
  71                 return false;
  72
  73         /*
  74          * Hardware doesn't globalize the required cache ops, so SMP calls may
  75          * be needed, but only if there are foreign CPUs (non-siblings with
  76          * separate caches).
  77          */
  78         /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
  79 #ifdef CONFIG_SMP
  80         return !cpumask_empty(&cpu_foreign_map[0]);
  81 #else
  82         return false;
  83 #endif
  84 }
  85
  86 /*
  87  * Special Variant of smp_call_function for use by cache functions:
  88  *
  89  *  o No return value
  90  *  o collapses to normal function call on UP kernels
  91  *  o collapses to normal function call on systems with a single shared
  92  *    primary cache.
  93  *  o doesn't disable interrupts on the local CPU
  94  */
  95 static inline void r4k_on_each_cpu(unsigned int type,
  96                                    void (*func)(void *info), void *info)
  97 {
  98         preempt_disable();
  99         if (r4k_op_needs_ipi(type))
 100                 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
 101                                        func, info, 1);
 102         func(info);
 103         preempt_enable();
 104 }
 105
 106 /*
 107  * Must die.
 108  */
 109 static unsigned long icache_size __read_mostly;
 110 static unsigned long dcache_size __read_mostly;
 111 static unsigned long vcache_size __read_mostly;
 112 static unsigned long scache_size __read_mostly;
 113
 114 /*
 115  * Dummy cache handling routines for machines without boardcaches
 116  */
 117 static void cache_noop(void) {}
 118
 119 static struct bcache_ops no_sc_ops = {
 120         .bc_enable = (void *)cache_noop,
 121         .bc_disable = (void *)cache_noop,
 122         .bc_wback_inv = (void *)cache_noop,
 123         .bc_inv = (void *)cache_noop
 124 };
 125
 126 struct bcache_ops *bcops = &no_sc_ops;
 127
 128 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 129 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 130
 131 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
 132 do {                                                                    \
 133         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
 134                 *(volatile unsigned long *)CKSEG1;                      \
 135         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
 136                 __asm__ __volatile__("nop;nop;nop;nop");                \
 137 } while (0)
 138
 139 static void (*r4k_blast_dcache_page)(unsigned long addr);
 140
 141 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 142 {
 143         R4600_HIT_CACHEOP_WAR_IMPL;
 144         blast_dcache32_page(addr);
 145 }
 146
 147 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 148 {
 149         blast_dcache64_page(addr);
 150 }
 151
 152 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 153 {
 154         blast_dcache128_page(addr);
 155 }
 156
 157 static void r4k_blast_dcache_page_setup(void)
 158 {
 159         unsigned long  dc_lsize = cpu_dcache_line_size();
 160
 161         switch (dc_lsize) {
 162         case 0:
 163                 r4k_blast_dcache_page = (void *)cache_noop;
 164                 break;
 165         case 16:
 166                 r4k_blast_dcache_page = blast_dcache16_page;
 167                 break;
 168         case 32:
 169                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 170                 break;
 171         case 64:
 172                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 173                 break;
 174         case 128:
 175                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 176                 break;
 177         default:
 178                 break;
 179         }
 180 }
 181
 182 #ifndef CONFIG_EVA
 183 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 184 #else
 185
 186 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 187
 188 static void r4k_blast_dcache_user_page_setup(void)
 189 {
 190         unsigned long  dc_lsize = cpu_dcache_line_size();
 191
 192         if (dc_lsize == 0)
 193                 r4k_blast_dcache_user_page = (void *)cache_noop;
 194         else if (dc_lsize == 16)
 195                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 196         else if (dc_lsize == 32)
 197                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 198         else if (dc_lsize == 64)
 199                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 200 }
 201
 202 #endif
 203
 204 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 205
 206 static void r4k_blast_dcache_page_indexed_setup(void)
 207 {
 208         unsigned long dc_lsize = cpu_dcache_line_size();
 209
 210         if (dc_lsize == 0)
 211                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 212         else if (dc_lsize == 16)
 213                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 214         else if (dc_lsize == 32)
 215                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 216         else if (dc_lsize == 64)
 217                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 218         else if (dc_lsize == 128)
 219                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 220 }
 221
 222 void (* r4k_blast_dcache)(void);
 223 EXPORT_SYMBOL(r4k_blast_dcache);
 224
 225 static void r4k_blast_dcache_setup(void)
 226 {
 227         unsigned long dc_lsize = cpu_dcache_line_size();
 228
 229         if (dc_lsize == 0)
 230                 r4k_blast_dcache = (void *)cache_noop;
 231         else if (dc_lsize == 16)
 232                 r4k_blast_dcache = blast_dcache16;
 233         else if (dc_lsize == 32)
 234                 r4k_blast_dcache = blast_dcache32;
 235         else if (dc_lsize == 64)
 236                 r4k_blast_dcache = blast_dcache64;
 237         else if (dc_lsize == 128)
 238                 r4k_blast_dcache = blast_dcache128;
 239 }
 240
 241 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 242 #define JUMP_TO_ALIGN(order) \
 243         __asm__ __volatile__( \
 244                 "b\t1f\n\t" \
 245                 ".align\t" #order "\n\t" \
 246                 "1:\n\t" \
 247                 )
 248 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 249 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 250
 251 static inline void blast_r4600_v1_icache32(void)
 252 {
 253         unsigned long flags;
 254
 255         local_irq_save(flags);
 256         blast_icache32();
 257         local_irq_restore(flags);
 258 }
 259
 260 static inline void tx49_blast_icache32(void)
 261 {
 262         unsigned long start = INDEX_BASE;
 263         unsigned long end = start + current_cpu_data.icache.waysize;
 264         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 265         unsigned long ws_end = current_cpu_data.icache.ways <<
 266                                current_cpu_data.icache.waybit;
 267         unsigned long ws, addr;
 268
 269         CACHE32_UNROLL32_ALIGN2;
 270         /* I'm in even chunk.  blast odd chunks */
 271         for (ws = 0; ws < ws_end; ws += ws_inc)
 272                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 273                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 274                                      addr | ws, 32);
 275         CACHE32_UNROLL32_ALIGN;
 276         /* I'm in odd chunk.  blast even chunks */
 277         for (ws = 0; ws < ws_end; ws += ws_inc)
 278                 for (addr = start; addr < end; addr += 0x400 * 2)
 279                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 280                                      addr | ws, 32);
 281 }
 282
 283 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 284 {
 285         unsigned long flags;
 286
 287         local_irq_save(flags);
 288         blast_icache32_page_indexed(page);
 289         local_irq_restore(flags);
 290 }
 291
 292 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 293 {
 294         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 295         unsigned long start = INDEX_BASE + (page & indexmask);
 296         unsigned long end = start + PAGE_SIZE;
 297         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 298         unsigned long ws_end = current_cpu_data.icache.ways <<
 299                                current_cpu_data.icache.waybit;
 300         unsigned long ws, addr;
 301
 302         CACHE32_UNROLL32_ALIGN2;
 303         /* I'm in even chunk.  blast odd chunks */
 304         for (ws = 0; ws < ws_end; ws += ws_inc)
 305                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 306                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 307                                      addr | ws, 32);
 308         CACHE32_UNROLL32_ALIGN;
 309         /* I'm in odd chunk.  blast even chunks */
 310         for (ws = 0; ws < ws_end; ws += ws_inc)
 311                 for (addr = start; addr < end; addr += 0x400 * 2)
 312                         cache_unroll(32, kernel_cache, Index_Invalidate_I,
 313                                      addr | ws, 32);
 314 }
 315
 316 static void (* r4k_blast_icache_page)(unsigned long addr);
 317
 318 static void r4k_blast_icache_page_setup(void)
 319 {
 320         unsigned long ic_lsize = cpu_icache_line_size();
 321
 322         if (ic_lsize == 0)
 323                 r4k_blast_icache_page = (void *)cache_noop;
 324         else if (ic_lsize == 16)
 325                 r4k_blast_icache_page = blast_icache16_page;
 326         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
 327                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 328         else if (ic_lsize == 32)
 329                 r4k_blast_icache_page = blast_icache32_page;
 330         else if (ic_lsize == 64)
 331                 r4k_blast_icache_page = blast_icache64_page;
 332         else if (ic_lsize == 128)
 333                 r4k_blast_icache_page = blast_icache128_page;
 334 }
 335
 336 #ifndef CONFIG_EVA
 337 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 338 #else
 339
 340 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 341
 342 static void r4k_blast_icache_user_page_setup(void)
 343 {
 344         unsigned long ic_lsize = cpu_icache_line_size();
 345
 346         if (ic_lsize == 0)
 347                 r4k_blast_icache_user_page = (void *)cache_noop;
 348         else if (ic_lsize == 16)
 349                 r4k_blast_icache_user_page = blast_icache16_user_page;
 350         else if (ic_lsize == 32)
 351                 r4k_blast_icache_user_page = blast_icache32_user_page;
 352         else if (ic_lsize == 64)
 353                 r4k_blast_icache_user_page = blast_icache64_user_page;
 354 }
 355
 356 #endif
 357
 358 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 359
 360 static void r4k_blast_icache_page_indexed_setup(void)
 361 {
 362         unsigned long ic_lsize = cpu_icache_line_size();
 363
 364         if (ic_lsize == 0)
 365                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 366         else if (ic_lsize == 16)
 367                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 368         else if (ic_lsize == 32) {
 369                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 370                         r4k_blast_icache_page_indexed =
 371                                 blast_icache32_r4600_v1_page_indexed;
 372                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 373                         r4k_blast_icache_page_indexed =
 374                                 tx49_blast_icache32_page_indexed;
 375                 else if (current_cpu_type() == CPU_LOONGSON2EF)
 376                         r4k_blast_icache_page_indexed =
 377                                 loongson2_blast_icache32_page_indexed;
 378                 else
 379                         r4k_blast_icache_page_indexed =
 380                                 blast_icache32_page_indexed;
 381         } else if (ic_lsize == 64)
 382                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 383 }
 384
 385 void (* r4k_blast_icache)(void);
 386 EXPORT_SYMBOL(r4k_blast_icache);
 387
 388 static void r4k_blast_icache_setup(void)
 389 {
 390         unsigned long ic_lsize = cpu_icache_line_size();
 391
 392         if (ic_lsize == 0)
 393                 r4k_blast_icache = (void *)cache_noop;
 394         else if (ic_lsize == 16)
 395                 r4k_blast_icache = blast_icache16;
 396         else if (ic_lsize == 32) {
 397                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 398                         r4k_blast_icache = blast_r4600_v1_icache32;
 399                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 400                         r4k_blast_icache = tx49_blast_icache32;
 401                 else if (current_cpu_type() == CPU_LOONGSON2EF)
 402                         r4k_blast_icache = loongson2_blast_icache32;
 403                 else
 404                         r4k_blast_icache = blast_icache32;
 405         } else if (ic_lsize == 64)
 406                 r4k_blast_icache = blast_icache64;
 407         else if (ic_lsize == 128)
 408                 r4k_blast_icache = blast_icache128;
 409 }
 410
 411 static void (* r4k_blast_scache_page)(unsigned long addr);
 412
 413 static void r4k_blast_scache_page_setup(void)
 414 {
 415         unsigned long sc_lsize = cpu_scache_line_size();
 416
 417         if (scache_size == 0)
 418                 r4k_blast_scache_page = (void *)cache_noop;
 419         else if (sc_lsize == 16)
 420                 r4k_blast_scache_page = blast_scache16_page;
 421         else if (sc_lsize == 32)
 422                 r4k_blast_scache_page = blast_scache32_page;
 423         else if (sc_lsize == 64)
 424                 r4k_blast_scache_page = blast_scache64_page;
 425         else if (sc_lsize == 128)
 426                 r4k_blast_scache_page = blast_scache128_page;
 427 }
 428
 429 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 430
 431 static void r4k_blast_scache_page_indexed_setup(void)
 432 {
 433         unsigned long sc_lsize = cpu_scache_line_size();
 434
 435         if (scache_size == 0)
 436                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 437         else if (sc_lsize == 16)
 438                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 439         else if (sc_lsize == 32)
 440                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 441         else if (sc_lsize == 64)
 442                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 443         else if (sc_lsize == 128)
 444                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 445 }
 446
 447 static void (* r4k_blast_scache)(void);
 448
 449 static void r4k_blast_scache_setup(void)
 450 {
 451         unsigned long sc_lsize = cpu_scache_line_size();
 452
 453         if (scache_size == 0)
 454                 r4k_blast_scache = (void *)cache_noop;
 455         else if (sc_lsize == 16)
 456                 r4k_blast_scache = blast_scache16;
 457         else if (sc_lsize == 32)
 458                 r4k_blast_scache = blast_scache32;
 459         else if (sc_lsize == 64)
 460                 r4k_blast_scache = blast_scache64;
 461         else if (sc_lsize == 128)
 462                 r4k_blast_scache = blast_scache128;
 463 }
 464
 465 static void (*r4k_blast_scache_node)(long node);
 466
 467 static void r4k_blast_scache_node_setup(void)
 468 {
 469         unsigned long sc_lsize = cpu_scache_line_size();
 470
 471         if (current_cpu_type() != CPU_LOONGSON64)
 472                 r4k_blast_scache_node = (void *)cache_noop;
 473         else if (sc_lsize == 16)
 474                 r4k_blast_scache_node = blast_scache16_node;
 475         else if (sc_lsize == 32)
 476                 r4k_blast_scache_node = blast_scache32_node;
 477         else if (sc_lsize == 64)
 478                 r4k_blast_scache_node = blast_scache64_node;
 479         else if (sc_lsize == 128)
 480                 r4k_blast_scache_node = blast_scache128_node;
 481 }
 482
 483 static inline void local_r4k___flush_cache_all(void * args)
 484 {
 485         switch (current_cpu_type()) {
 486         case CPU_LOONGSON2EF:
 487         case CPU_R4000SC:
 488         case CPU_R4000MC:
 489         case CPU_R4400SC:
 490         case CPU_R4400MC:
 491         case CPU_R10000:
 492         case CPU_R12000:
 493         case CPU_R14000:
 494         case CPU_R16000:
 495                 /*
 496                  * These caches are inclusive caches, that is, if something
 497                  * is not cached in the S-cache, we know it also won't be
 498                  * in one of the primary caches.
 499                  */
 500                 r4k_blast_scache();
 501                 break;
 502
 503         case CPU_LOONGSON64:
 504                 /* Use get_ebase_cpunum() for both NUMA=y/n */
 505                 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
 506                 break;
 507
 508         case CPU_BMIPS5000:
 509                 r4k_blast_scache();
 510                 __sync();
 511                 break;
 512
 513         default:
 514                 r4k_blast_dcache();
 515                 r4k_blast_icache();
 516                 break;
 517         }
 518 }
 519
 520 static void r4k___flush_cache_all(void)
 521 {
 522         r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
 523 }
 524
 525 /**
 526  * has_valid_asid() - Determine if an mm already has an ASID.
 527  * @mm:         Memory map.
 528  * @type:       R4K_HIT or R4K_INDEX, type of cache op.
 529  *
 530  * Determines whether @mm already has an ASID on any of the CPUs which cache ops
 531  * of type @type within an r4k_on_each_cpu() call will affect. If
 532  * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
 533  * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
 534  * will need to be checked.
 535  *
 536  * Must be called in non-preemptive context.
 537  *
 538  * Returns:     1 if the CPUs affected by @type cache ops have an ASID for @mm.
 539  *              0 otherwise.
 540  */
 541 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
 542 {
 543         unsigned int i;
 544         const cpumask_t *mask = cpu_present_mask;
 545
 546         if (cpu_has_mmid)
 547                 return cpu_context(0, mm) != 0;
 548
 549         /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
 550 #ifdef CONFIG_SMP
 551         /*
 552          * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
 553          * each foreign core, so we only need to worry about siblings.
 554          * Otherwise we need to worry about all present CPUs.
 555          */
 556         if (r4k_op_needs_ipi(type))
 557                 mask = &cpu_sibling_map[smp_processor_id()];
 558 #endif
 559         for_each_cpu(i, mask)
 560                 if (cpu_context(i, mm))
 561                         return 1;
 562         return 0;
 563 }
 564
 565 static void r4k__flush_cache_vmap(void)
 566 {
 567         r4k_blast_dcache();
 568 }
 569
 570 static void r4k__flush_cache_vunmap(void)
 571 {
 572         r4k_blast_dcache();
 573 }
 574
 575 /*
 576  * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
 577  * whole caches when vma is executable.
 578  */
 579 static inline void local_r4k_flush_cache_range(void * args)
 580 {
 581         struct vm_area_struct *vma = args;
 582         int exec = vma->vm_flags & VM_EXEC;
 583
 584         if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
 585                 return;
 586
 587         /*
 588          * If dcache can alias, we must blast it since mapping is changing.
 589          * If executable, we must ensure any dirty lines are written back far
 590          * enough to be visible to icache.
 591          */
 592         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 593                 r4k_blast_dcache();
 594         /* If executable, blast stale lines from icache */
 595         if (exec)
 596                 r4k_blast_icache();
 597 }
 598
 599 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 600         unsigned long start, unsigned long end)
 601 {
 602         int exec = vma->vm_flags & VM_EXEC;
 603
 604         if (cpu_has_dc_aliases || exec)
 605                 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
 606 }
 607
 608 static inline void local_r4k_flush_cache_mm(void * args)
 609 {
 610         struct mm_struct *mm = args;
 611
 612         if (!has_valid_asid(mm, R4K_INDEX))
 613                 return;
 614
 615         /*
 616          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 617          * only flush the primary caches but R1x000 behave sane ...
 618          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 619          * caches, so we can bail out early.
 620          */
 621         if (current_cpu_type() == CPU_R4000SC ||
 622             current_cpu_type() == CPU_R4000MC ||
 623             current_cpu_type() == CPU_R4400SC ||
 624             current_cpu_type() == CPU_R4400MC) {
 625                 r4k_blast_scache();
 626                 return;
 627         }
 628
 629         r4k_blast_dcache();
 630 }
 631
 632 static void r4k_flush_cache_mm(struct mm_struct *mm)
 633 {
 634         if (!cpu_has_dc_aliases)
 635                 return;
 636
 637         r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
 638 }
 639
 640 struct flush_cache_page_args {
 641         struct vm_area_struct *vma;
 642         unsigned long addr;
 643         unsigned long pfn;
 644 };
 645
 646 static inline void local_r4k_flush_cache_page(void *args)
 647 {
 648         struct flush_cache_page_args *fcp_args = args;
 649         struct vm_area_struct *vma = fcp_args->vma;
 650         unsigned long addr = fcp_args->addr;
 651         struct page *page = pfn_to_page(fcp_args->pfn);
 652         int exec = vma->vm_flags & VM_EXEC;
 653         struct mm_struct *mm = vma->vm_mm;
 654         int map_coherent = 0;
 655         pgd_t *pgdp;
 656         p4d_t *p4dp;
 657         pud_t *pudp;
 658         pmd_t *pmdp;
 659         pte_t *ptep;
 660         void *vaddr;
 661
 662         /*
 663          * If owns no valid ASID yet, cannot possibly have gotten
 664          * this page into the cache.
 665          */
 666         if (!has_valid_asid(mm, R4K_HIT))
 667                 return;
 668
 669         addr &= PAGE_MASK;
 670         pgdp = pgd_offset(mm, addr);
 671         p4dp = p4d_offset(pgdp, addr);
 672         pudp = pud_offset(p4dp, addr);
 673         pmdp = pmd_offset(pudp, addr);
 674         ptep = pte_offset(pmdp, addr);
 675
 676         /*
 677          * If the page isn't marked valid, the page cannot possibly be
 678          * in the cache.
 679          */
 680         if (!(pte_present(*ptep)))
 681                 return;
 682
 683         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 684                 vaddr = NULL;
 685         else {
 686                 /*
 687                  * Use kmap_coherent or kmap_atomic to do flushes for
 688                  * another ASID than the current one.
 689                  */
 690                 map_coherent = (cpu_has_dc_aliases &&
 691                                 page_mapcount(page) &&
 692                                 !Page_dcache_dirty(page));
 693                 if (map_coherent)
 694                         vaddr = kmap_coherent(page, addr);
 695                 else
 696                         vaddr = kmap_atomic(page);
 697                 addr = (unsigned long)vaddr;
 698         }
 699
 700         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 701                 vaddr ? r4k_blast_dcache_page(addr) :
 702                         r4k_blast_dcache_user_page(addr);
 703                 if (exec && !cpu_icache_snoops_remote_store)
 704                         r4k_blast_scache_page(addr);
 705         }
 706         if (exec) {
 707                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 708                         drop_mmu_context(mm);
 709                 } else
 710                         vaddr ? r4k_blast_icache_page(addr) :
 711                                 r4k_blast_icache_user_page(addr);
 712         }
 713
 714         if (vaddr) {
 715                 if (map_coherent)
 716                         kunmap_coherent();
 717                 else
 718                         kunmap_atomic(vaddr);
 719         }
 720 }
 721
 722 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 723         unsigned long addr, unsigned long pfn)
 724 {
 725         struct flush_cache_page_args args;
 726
 727         args.vma = vma;
 728         args.addr = addr;
 729         args.pfn = pfn;
 730
 731         r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
 732 }
 733
 734 static inline void local_r4k_flush_data_cache_page(void * addr)
 735 {
 736         r4k_blast_dcache_page((unsigned long) addr);
 737 }
 738
 739 static void r4k_flush_data_cache_page(unsigned long addr)
 740 {
 741         if (in_atomic())
 742                 local_r4k_flush_data_cache_page((void *)addr);
 743         else
 744                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
 745                                 (void *) addr);
 746 }
 747
 748 struct flush_icache_range_args {
 749         unsigned long start;
 750         unsigned long end;
 751         unsigned int type;
 752         bool user;
 753 };
 754
 755 static inline void __local_r4k_flush_icache_range(unsigned long start,
 756                                                   unsigned long end,
 757                                                   unsigned int type,
 758                                                   bool user)
 759 {
 760         if (!cpu_has_ic_fills_f_dc) {
 761                 if (type == R4K_INDEX ||
 762                     (type & R4K_INDEX && end - start >= dcache_size)) {
 763                         r4k_blast_dcache();
 764                 } else {
 765                         R4600_HIT_CACHEOP_WAR_IMPL;
 766                         if (user)
 767                                 protected_blast_dcache_range(start, end);
 768                         else
 769                                 blast_dcache_range(start, end);
 770                 }
 771         }
 772
 773         if (type == R4K_INDEX ||
 774             (type & R4K_INDEX && end - start > icache_size))
 775                 r4k_blast_icache();
 776         else {
 777                 switch (boot_cpu_type()) {
 778                 case CPU_LOONGSON2EF:
 779                         protected_loongson2_blast_icache_range(start, end);
 780                         break;
 781
 782                 default:
 783                         if (user)
 784                                 protected_blast_icache_range(start, end);
 785                         else
 786                                 blast_icache_range(start, end);
 787                         break;
 788                 }
 789         }
 790 }
 791
 792 static inline void local_r4k_flush_icache_range(unsigned long start,
 793                                                 unsigned long end)
 794 {
 795         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
 796 }
 797
 798 static inline void local_r4k_flush_icache_user_range(unsigned long start,
 799                                                      unsigned long end)
 800 {
 801         __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
 802 }
 803
 804 static inline void local_r4k_flush_icache_range_ipi(void *args)
 805 {
 806         struct flush_icache_range_args *fir_args = args;
 807         unsigned long start = fir_args->start;
 808         unsigned long end = fir_args->end;
 809         unsigned int type = fir_args->type;
 810         bool user = fir_args->user;
 811
 812         __local_r4k_flush_icache_range(start, end, type, user);
 813 }
 814
 815 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
 816                                      bool user)
 817 {
 818         struct flush_icache_range_args args;
 819         unsigned long size, cache_size;
 820
 821         args.start = start;
 822         args.end = end;
 823         args.type = R4K_HIT | R4K_INDEX;
 824         args.user = user;
 825
 826         /*
 827          * Indexed cache ops require an SMP call.
 828          * Consider if that can or should be avoided.
 829          */
 830         preempt_disable();
 831         if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
 832                 /*
 833                  * If address-based cache ops don't require an SMP call, then
 834                  * use them exclusively for small flushes.
 835                  */
 836                 size = end - start;
 837                 cache_size = icache_size;
 838                 if (!cpu_has_ic_fills_f_dc) {
 839                         size *= 2;
 840                         cache_size += dcache_size;
 841                 }
 842                 if (size <= cache_size)
 843                         args.type &= ~R4K_INDEX;
 844         }
 845         r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
 846         preempt_enable();
 847         instruction_hazard();
 848 }
 849
 850 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 851 {
 852         return __r4k_flush_icache_range(start, end, false);
 853 }
 854
 855 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
 856 {
 857         return __r4k_flush_icache_range(start, end, true);
 858 }
 859
 860 #ifdef CONFIG_DMA_NONCOHERENT
 861
 862 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 863 {
 864         /* Catch bad driver code */
 865         if (WARN_ON(size == 0))
 866                 return;
 867
 868         preempt_disable();
 869         if (cpu_has_inclusive_pcaches) {
 870                 if (size >= scache_size) {
 871                         if (current_cpu_type() != CPU_LOONGSON64)
 872                                 r4k_blast_scache();
 873                         else
 874                                 r4k_blast_scache_node(pa_to_nid(addr));
 875                 } else {
 876                         blast_scache_range(addr, addr + size);
 877                 }
 878                 preempt_enable();
 879                 __sync();
 880                 return;
 881         }
 882
 883         /*
 884          * Either no secondary cache or the available caches don't have the
 885          * subset property so we have to flush the primary caches
 886          * explicitly.
 887          * If we would need IPI to perform an INDEX-type operation, then
 888          * we have to use the HIT-type alternative as IPI cannot be used
 889          * here due to interrupts possibly being disabled.
 890          */
 891         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 892                 r4k_blast_dcache();
 893         } else {
 894                 R4600_HIT_CACHEOP_WAR_IMPL;
 895                 blast_dcache_range(addr, addr + size);
 896         }
 897         preempt_enable();
 898
 899         bc_wback_inv(addr, size);
 900         __sync();
 901 }
 902
 903 static void prefetch_cache_inv(unsigned long addr, unsigned long size)
 904 {
 905         unsigned int linesz = cpu_scache_line_size();
 906         unsigned long addr0 = addr, addr1;
 907
 908         addr0 &= ~(linesz - 1);
 909         addr1 = (addr0 + size - 1) & ~(linesz - 1);
 910
 911         protected_writeback_scache_line(addr0);
 912         if (likely(addr1 != addr0))
 913                 protected_writeback_scache_line(addr1);
 914         else
 915                 return;
 916
 917         addr0 += linesz;
 918         if (likely(addr1 != addr0))
 919                 protected_writeback_scache_line(addr0);
 920         else
 921                 return;
 922
 923         addr1 -= linesz;
 924         if (likely(addr1 > addr0))
 925                 protected_writeback_scache_line(addr0);
 926 }
 927
 928 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 929 {
 930         /* Catch bad driver code */
 931         if (WARN_ON(size == 0))
 932                 return;
 933
 934         preempt_disable();
 935
 936         if (current_cpu_type() == CPU_BMIPS5000)
 937                 prefetch_cache_inv(addr, size);
 938
 939         if (cpu_has_inclusive_pcaches) {
 940                 if (size >= scache_size) {
 941                         if (current_cpu_type() != CPU_LOONGSON64)
 942                                 r4k_blast_scache();
 943                         else
 944                                 r4k_blast_scache_node(pa_to_nid(addr));
 945                 } else {
 946                         /*
 947                          * There is no clearly documented alignment requirement
 948                          * for the cache instruction on MIPS processors and
 949                          * some processors, among them the RM5200 and RM7000
 950                          * QED processors will throw an address error for cache
 951                          * hit ops with insufficient alignment.  Solved by
 952                          * aligning the address to cache line size.
 953                          */
 954                         blast_inv_scache_range(addr, addr + size);
 955                 }
 956                 preempt_enable();
 957                 __sync();
 958                 return;
 959         }
 960
 961         if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
 962                 r4k_blast_dcache();
 963         } else {
 964                 R4600_HIT_CACHEOP_WAR_IMPL;
 965                 blast_inv_dcache_range(addr, addr + size);
 966         }
 967         preempt_enable();
 968
 969         bc_inv(addr, size);
 970         __sync();
 971 }
 972 #endif /* CONFIG_DMA_NONCOHERENT */
 973
 974 static void r4k_flush_icache_all(void)
 975 {
 976         if (cpu_has_vtag_icache)
 977                 r4k_blast_icache();
 978 }
 979
 980 struct flush_kernel_vmap_range_args {
 981         unsigned long   vaddr;
 982         int             size;
 983 };
 984
 985 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
 986 {
 987         /*
 988          * Aliases only affect the primary caches so don't bother with
 989          * S-caches or T-caches.
 990          */
 991         r4k_blast_dcache();
 992 }
 993
 994 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 995 {
 996         struct flush_kernel_vmap_range_args *vmra = args;
 997         unsigned long vaddr = vmra->vaddr;
 998         int size = vmra->size;
 999
1000         /*
1001          * Aliases only affect the primary caches so don't bother with
1002          * S-caches or T-caches.
1003          */
1004         R4600_HIT_CACHEOP_WAR_IMPL;
1005         blast_dcache_range(vaddr, vaddr + size);
1006 }
1007
1008 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1009 {
1010         struct flush_kernel_vmap_range_args args;
1011
1012         args.vaddr = (unsigned long) vaddr;
1013         args.size = size;
1014
1015         if (size >= dcache_size)
1016                 r4k_on_each_cpu(R4K_INDEX,
1017                                 local_r4k_flush_kernel_vmap_range_index, NULL);
1018         else
1019                 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1020                                 &args);
1021 }
1022
1023 static inline void rm7k_erratum31(void)
1024 {
1025         const unsigned long ic_lsize = 32;
1026         unsigned long addr;
1027
1028         /* RM7000 erratum #31. The icache is screwed at startup. */
1029         write_c0_taglo(0);
1030         write_c0_taghi(0);
1031
1032         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1033                 __asm__ __volatile__ (
1034                         ".set push\n\t"
1035                         ".set noreorder\n\t"
1036                         ".set mips3\n\t"
1037                         "cache\t%1, 0(%0)\n\t"
1038                         "cache\t%1, 0x1000(%0)\n\t"
1039                         "cache\t%1, 0x2000(%0)\n\t"
1040                         "cache\t%1, 0x3000(%0)\n\t"
1041                         "cache\t%2, 0(%0)\n\t"
1042                         "cache\t%2, 0x1000(%0)\n\t"
1043                         "cache\t%2, 0x2000(%0)\n\t"
1044                         "cache\t%2, 0x3000(%0)\n\t"
1045                         "cache\t%1, 0(%0)\n\t"
1046                         "cache\t%1, 0x1000(%0)\n\t"
1047                         "cache\t%1, 0x2000(%0)\n\t"
1048                         "cache\t%1, 0x3000(%0)\n\t"
1049                         ".set pop\n"
1050                         :
1051                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
1052         }
1053 }
1054
1055 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1056 {
1057         unsigned int imp = c->processor_id & PRID_IMP_MASK;
1058         unsigned int rev = c->processor_id & PRID_REV_MASK;
1059         int present = 0;
1060
1061         /*
1062          * Early versions of the 74K do not update the cache tags on a
1063          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1064          * aliases.  In this case it is better to treat the cache as always
1065          * having aliases.  Also disable the synonym tag update feature
1066          * where available.  In this case no opportunistic tag update will
1067          * happen where a load causes a virtual address miss but a physical
1068          * address hit during a D-cache look-up.
1069          */
1070         switch (imp) {
1071         case PRID_IMP_74K:
1072                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1073                         present = 1;
1074                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1075                         write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
1076                 break;
1077         case PRID_IMP_1074K:
1078                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1079                         present = 1;
1080                         write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
1081                 }
1082                 break;
1083         default:
1084                 BUG();
1085         }
1086
1087         return present;
1088 }
1089
1090 static void b5k_instruction_hazard(void)
1091 {
1092         __sync();
1093         __sync();
1094         __asm__ __volatile__(
1095         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1096         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1097         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1098         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
1099         : : : "memory");
1100 }
1101
1102 static char *way_string[] = { NULL, "direct mapped", "2-way",
1103         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1104         "9-way", "10-way", "11-way", "12-way",
1105         "13-way", "14-way", "15-way", "16-way",
1106 };
1107
1108 static void probe_pcache(void)
1109 {
1110         struct cpuinfo_mips *c = &current_cpu_data;
1111         unsigned int config = read_c0_config();
1112         unsigned int prid = read_c0_prid();
1113         int has_74k_erratum = 0;
1114         unsigned long config1;
1115         unsigned int lsize;
1116
1117         switch (current_cpu_type()) {
1118         case CPU_R4600:                 /* QED style two way caches? */
1119         case CPU_R4700:
1120         case CPU_R5000:
1121         case CPU_NEVADA:
1122                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1123                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1124                 c->icache.ways = 2;
1125                 c->icache.waybit = __ffs(icache_size/2);
1126
1127                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1128                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1129                 c->dcache.ways = 2;
1130                 c->dcache.waybit= __ffs(dcache_size/2);
1131
1132                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1133                 break;
1134
1135         case CPU_R5500:
1136                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1137                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1138                 c->icache.ways = 2;
1139                 c->icache.waybit= 0;
1140
1141                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1142                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1143                 c->dcache.ways = 2;
1144                 c->dcache.waybit = 0;
1145
1146                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1147                 break;
1148
1149         case CPU_TX49XX:
1150                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1151                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1152                 c->icache.ways = 4;
1153                 c->icache.waybit= 0;
1154
1155                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1156                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1157                 c->dcache.ways = 4;
1158                 c->dcache.waybit = 0;
1159
1160                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1161                 c->options |= MIPS_CPU_PREFETCH;
1162                 break;
1163
1164         case CPU_R4000PC:
1165         case CPU_R4000SC:
1166         case CPU_R4000MC:
1167         case CPU_R4400PC:
1168         case CPU_R4400SC:
1169         case CPU_R4400MC:
1170                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1171                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1172                 c->icache.ways = 1;
1173                 c->icache.waybit = 0;   /* doesn't matter */
1174
1175                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1176                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1177                 c->dcache.ways = 1;
1178                 c->dcache.waybit = 0;   /* does not matter */
1179
1180                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1181                 break;
1182
1183         case CPU_R10000:
1184         case CPU_R12000:
1185         case CPU_R14000:
1186         case CPU_R16000:
1187                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1188                 c->icache.linesz = 64;
1189                 c->icache.ways = 2;
1190                 c->icache.waybit = 0;
1191
1192                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1193                 c->dcache.linesz = 32;
1194                 c->dcache.ways = 2;
1195                 c->dcache.waybit = 0;
1196
1197                 c->options |= MIPS_CPU_PREFETCH;
1198                 break;
1199
1200         case CPU_VR4133:
1201                 write_c0_config(config & ~VR41_CONF_P4K);
1202                 fallthrough;
1203         case CPU_VR4131:
1204                 /* Workaround for cache instruction bug of VR4131 */
1205                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1206                     c->processor_id == 0x0c82U) {
1207                         config |= 0x00400000U;
1208                         if (c->processor_id == 0x0c80U)
1209                                 config |= VR41_CONF_BP;
1210                         write_c0_config(config);
1211                 } else
1212                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1213
1214                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1215                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1216                 c->icache.ways = 2;
1217                 c->icache.waybit = __ffs(icache_size/2);
1218
1219                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1220                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1221                 c->dcache.ways = 2;
1222                 c->dcache.waybit = __ffs(dcache_size/2);
1223                 break;
1224
1225         case CPU_VR41XX:
1226         case CPU_VR4111:
1227         case CPU_VR4121:
1228         case CPU_VR4122:
1229         case CPU_VR4181:
1230         case CPU_VR4181A:
1231                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1232                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1233                 c->icache.ways = 1;
1234                 c->icache.waybit = 0;   /* doesn't matter */
1235
1236                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1237                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1238                 c->dcache.ways = 1;
1239                 c->dcache.waybit = 0;   /* does not matter */
1240
1241                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1242                 break;
1243
1244         case CPU_RM7000:
1245                 rm7k_erratum31();
1246
1247                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1248                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1249                 c->icache.ways = 4;
1250                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1251
1252                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1253                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1254                 c->dcache.ways = 4;
1255                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1256
1257                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1258                 c->options |= MIPS_CPU_PREFETCH;
1259                 break;
1260
1261         case CPU_LOONGSON2EF:
1262                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1263                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1264                 if (prid & 0x3)
1265                         c->icache.ways = 4;
1266                 else
1267                         c->icache.ways = 2;
1268                 c->icache.waybit = 0;
1269
1270                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1271                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1272                 if (prid & 0x3)
1273                         c->dcache.ways = 4;
1274                 else
1275                         c->dcache.ways = 2;
1276                 c->dcache.waybit = 0;
1277                 break;
1278
1279         case CPU_LOONGSON64:
1280                 config1 = read_c0_config1();
1281                 lsize = (config1 >> 19) & 7;
1282                 if (lsize)
1283                         c->icache.linesz = 2 << lsize;
1284                 else
1285                         c->icache.linesz = 0;
1286                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1287                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1288                 icache_size = c->icache.sets *
1289                                           c->icache.ways *
1290                                           c->icache.linesz;
1291                 c->icache.waybit = 0;
1292
1293                 lsize = (config1 >> 10) & 7;
1294                 if (lsize)
1295                         c->dcache.linesz = 2 << lsize;
1296                 else
1297                         c->dcache.linesz = 0;
1298                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1299                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1300                 dcache_size = c->dcache.sets *
1301                                           c->dcache.ways *
1302                                           c->dcache.linesz;
1303                 c->dcache.waybit = 0;
1304                 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1305                                 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1306                                 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1307                         c->options |= MIPS_CPU_PREFETCH;
1308                 break;
1309
1310         case CPU_CAVIUM_OCTEON3:
1311                 /* For now lie about the number of ways. */
1312                 c->icache.linesz = 128;
1313                 c->icache.sets = 16;
1314                 c->icache.ways = 8;
1315                 c->icache.flags |= MIPS_CACHE_VTAG;
1316                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1317
1318                 c->dcache.linesz = 128;
1319                 c->dcache.ways = 8;
1320                 c->dcache.sets = 8;
1321                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1322                 c->options |= MIPS_CPU_PREFETCH;
1323                 break;
1324
1325         default:
1326                 if (!(config & MIPS_CONF_M))
1327                         panic("Don't know how to probe P-caches on this cpu.");
1328
1329                 /*
1330                  * So we seem to be a MIPS32 or MIPS64 CPU
1331                  * So let's probe the I-cache ...
1332                  */
1333                 config1 = read_c0_config1();
1334
1335                 lsize = (config1 >> 19) & 7;
1336
1337                 /* IL == 7 is reserved */
1338                 if (lsize == 7)
1339                         panic("Invalid icache line size");
1340
1341                 c->icache.linesz = lsize ? 2 << lsize : 0;
1342
1343                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1344                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1345
1346                 icache_size = c->icache.sets *
1347                               c->icache.ways *
1348                               c->icache.linesz;
1349                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1350
1351                 if (config & MIPS_CONF_VI)
1352                         c->icache.flags |= MIPS_CACHE_VTAG;
1353
1354                 /*
1355                  * Now probe the MIPS32 / MIPS64 data cache.
1356                  */
1357                 c->dcache.flags = 0;
1358
1359                 lsize = (config1 >> 10) & 7;
1360
1361                 /* DL == 7 is reserved */
1362                 if (lsize == 7)
1363                         panic("Invalid dcache line size");
1364
1365                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1366
1367                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1368                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1369
1370                 dcache_size = c->dcache.sets *
1371                               c->dcache.ways *
1372                               c->dcache.linesz;
1373                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1374
1375                 c->options |= MIPS_CPU_PREFETCH;
1376                 break;
1377         }
1378
1379         /*
1380          * Processor configuration sanity check for the R4000SC erratum
1381          * #5.  With page sizes larger than 32kB there is no possibility
1382          * to get a VCE exception anymore so we don't care about this
1383          * misconfiguration.  The case is rather theoretical anyway;
1384          * presumably no vendor is shipping his hardware in the "bad"
1385          * configuration.
1386          */
1387         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1388             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1389             !(config & CONF_SC) && c->icache.linesz != 16 &&
1390             PAGE_SIZE <= 0x8000)
1391                 panic("Improper R4000SC processor configuration detected");
1392
1393         /* compute a couple of other cache variables */
1394         c->icache.waysize = icache_size / c->icache.ways;
1395         c->dcache.waysize = dcache_size / c->dcache.ways;
1396
1397         c->icache.sets = c->icache.linesz ?
1398                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1399         c->dcache.sets = c->dcache.linesz ?
1400                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1401
1402         /*
1403          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1404          * virtually indexed so normally would suffer from aliases.  So
1405          * normally they'd suffer from aliases but magic in the hardware deals
1406          * with that for us so we don't need to take care ourselves.
1407          */
1408         switch (current_cpu_type()) {
1409         case CPU_20KC:
1410         case CPU_25KF:
1411         case CPU_I6400:
1412         case CPU_I6500:
1413         case CPU_SB1:
1414         case CPU_SB1A:
1415         case CPU_XLR:
1416                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1417                 break;
1418
1419         case CPU_R10000:
1420         case CPU_R12000:
1421         case CPU_R14000:
1422         case CPU_R16000:
1423                 break;
1424
1425         case CPU_74K:
1426         case CPU_1074K:
1427                 has_74k_erratum = alias_74k_erratum(c);
1428                 fallthrough;
1429         case CPU_M14KC:
1430         case CPU_M14KEC:
1431         case CPU_24K:
1432         case CPU_34K:
1433         case CPU_1004K:
1434         case CPU_INTERAPTIV:
1435         case CPU_P5600:
1436         case CPU_PROAPTIV:
1437         case CPU_M5150:
1438         case CPU_QEMU_GENERIC:
1439         case CPU_P6600:
1440         case CPU_M6250:
1441                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1442                     (c->icache.waysize > PAGE_SIZE))
1443                         c->icache.flags |= MIPS_CACHE_ALIASES;
1444                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1445                         /*
1446                          * Effectively physically indexed dcache,
1447                          * thus no virtual aliases.
1448                         */
1449                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1450                         break;
1451                 }
1452                 fallthrough;
1453         default:
1454                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1455                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1456         }
1457
1458         /* Physically indexed caches don't suffer from virtual aliasing */
1459         if (c->dcache.flags & MIPS_CACHE_PINDEX)
1460                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1461
1462         /*
1463          * In systems with CM the icache fills from L2 or closer caches, and
1464          * thus sees remote stores without needing to write them back any
1465          * further than that.
1466          */
1467         if (mips_cm_present())
1468                 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1469
1470         switch (current_cpu_type()) {
1471         case CPU_20KC:
1472                 /*
1473                  * Some older 20Kc chips doesn't have the 'VI' bit in
1474                  * the config register.
1475                  */
1476                 c->icache.flags |= MIPS_CACHE_VTAG;
1477                 break;
1478
1479         case CPU_ALCHEMY:
1480         case CPU_I6400:
1481         case CPU_I6500:
1482                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1483                 break;
1484
1485         case CPU_BMIPS5000:
1486                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1487                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1488                 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1489                 break;
1490
1491         case CPU_LOONGSON2EF:
1492                 /*
1493                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1494                  * one op will act on all 4 ways
1495                  */
1496                 c->icache.ways = 1;
1497         }
1498
1499         pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1500                 icache_size >> 10,
1501                 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1502                 way_string[c->icache.ways], c->icache.linesz);
1503
1504         pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1505                 dcache_size >> 10, way_string[c->dcache.ways],
1506                 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1507                 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1508                         "cache aliases" : "no aliases",
1509                 c->dcache.linesz);
1510 }
1511
1512 static void probe_vcache(void)
1513 {
1514         struct cpuinfo_mips *c = &current_cpu_data;
1515         unsigned int config2, lsize;
1516
1517         if (current_cpu_type() != CPU_LOONGSON64)
1518                 return;
1519
1520         config2 = read_c0_config2();
1521         if ((lsize = ((config2 >> 20) & 15)))
1522                 c->vcache.linesz = 2 << lsize;
1523         else
1524                 c->vcache.linesz = lsize;
1525
1526         c->vcache.sets = 64 << ((config2 >> 24) & 15);
1527         c->vcache.ways = 1 + ((config2 >> 16) & 15);
1528
1529         vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1530
1531         c->vcache.waybit = 0;
1532         c->vcache.waysize = vcache_size / c->vcache.ways;
1533
1534         pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1535                 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1536 }
1537
1538 /*
1539  * If you even _breathe_ on this function, look at the gcc output and make sure
1540  * it does not pop things on and off the stack for the cache sizing loop that
1541  * executes in KSEG1 space or else you will crash and burn badly.  You have
1542  * been warned.
1543  */
1544 static int probe_scache(void)
1545 {
1546         unsigned long flags, addr, begin, end, pow2;
1547         unsigned int config = read_c0_config();
1548         struct cpuinfo_mips *c = &current_cpu_data;
1549
1550         if (config & CONF_SC)
1551                 return 0;
1552
1553         begin = (unsigned long) &_stext;
1554         begin &= ~((4 * 1024 * 1024) - 1);
1555         end = begin + (4 * 1024 * 1024);
1556
1557         /*
1558          * This is such a bitch, you'd think they would make it easy to do
1559          * this.  Away you daemons of stupidity!
1560          */
1561         local_irq_save(flags);
1562
1563         /* Fill each size-multiple cache line with a valid tag. */
1564         pow2 = (64 * 1024);
1565         for (addr = begin; addr < end; addr = (begin + pow2)) {
1566                 unsigned long *p = (unsigned long *) addr;
1567                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1568                 pow2 <<= 1;
1569         }
1570
1571         /* Load first line with zero (therefore invalid) tag. */
1572         write_c0_taglo(0);
1573         write_c0_taghi(0);
1574         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1575         cache_op(Index_Store_Tag_I, begin);
1576         cache_op(Index_Store_Tag_D, begin);
1577         cache_op(Index_Store_Tag_SD, begin);
1578
1579         /* Now search for the wrap around point. */
1580         pow2 = (128 * 1024);
1581         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1582                 cache_op(Index_Load_Tag_SD, addr);
1583                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1584                 if (!read_c0_taglo())
1585                         break;
1586                 pow2 <<= 1;
1587         }
1588         local_irq_restore(flags);
1589         addr -= begin;
1590
1591         scache_size = addr;
1592         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1593         c->scache.ways = 1;
1594         c->scache.waybit = 0;           /* does not matter */
1595
1596         return 1;
1597 }
1598
1599 static void __init loongson2_sc_init(void)
1600 {
1601         struct cpuinfo_mips *c = &current_cpu_data;
1602
1603         scache_size = 512*1024;
1604         c->scache.linesz = 32;
1605         c->scache.ways = 4;
1606         c->scache.waybit = 0;
1607         c->scache.waysize = scache_size / (c->scache.ways);
1608         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1609         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1610                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1611
1612         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1613 }
1614
1615 static void __init loongson3_sc_init(void)
1616 {
1617         struct cpuinfo_mips *c = &current_cpu_data;
1618         unsigned int config2, lsize;
1619
1620         config2 = read_c0_config2();
1621         lsize = (config2 >> 4) & 15;
1622         if (lsize)
1623                 c->scache.linesz = 2 << lsize;
1624         else
1625                 c->scache.linesz = 0;
1626         c->scache.sets = 64 << ((config2 >> 8) & 15);
1627         c->scache.ways = 1 + (config2 & 15);
1628
1629         scache_size = c->scache.sets *
1630                                   c->scache.ways *
1631                                   c->scache.linesz;
1632
1633         /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1634         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1635                 scache_size *= 2;
1636         else
1637                 scache_size *= 4;
1638
1639         c->scache.waybit = 0;
1640         c->scache.waysize = scache_size / c->scache.ways;
1641         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1642                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1643         if (scache_size)
1644                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1645         return;
1646 }
1647
1648 extern int r5k_sc_init(void);
1649 extern int rm7k_sc_init(void);
1650 extern int mips_sc_init(void);
1651
1652 static void setup_scache(void)
1653 {
1654         struct cpuinfo_mips *c = &current_cpu_data;
1655         unsigned int config = read_c0_config();
1656         int sc_present = 0;
1657
1658         /*
1659          * Do the probing thing on R4000SC and R4400SC processors.  Other
1660          * processors don't have a S-cache that would be relevant to the
1661          * Linux memory management.
1662          */
1663         switch (current_cpu_type()) {
1664         case CPU_R4000SC:
1665         case CPU_R4000MC:
1666         case CPU_R4400SC:
1667         case CPU_R4400MC:
1668                 sc_present = run_uncached(probe_scache);
1669                 if (sc_present)
1670                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1671                 break;
1672
1673         case CPU_R10000:
1674         case CPU_R12000:
1675         case CPU_R14000:
1676         case CPU_R16000:
1677                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1678                 c->scache.linesz = 64 << ((config >> 13) & 1);
1679                 c->scache.ways = 2;
1680                 c->scache.waybit= 0;
1681                 sc_present = 1;
1682                 break;
1683
1684         case CPU_R5000:
1685         case CPU_NEVADA:
1686 #ifdef CONFIG_R5000_CPU_SCACHE
1687                 r5k_sc_init();
1688 #endif
1689                 return;
1690
1691         case CPU_RM7000:
1692 #ifdef CONFIG_RM7000_CPU_SCACHE
1693                 rm7k_sc_init();
1694 #endif
1695                 return;
1696
1697         case CPU_LOONGSON2EF:
1698                 loongson2_sc_init();
1699                 return;
1700
1701         case CPU_LOONGSON64:
1702                 loongson3_sc_init();
1703                 return;
1704
1705         case CPU_CAVIUM_OCTEON3:
1706         case CPU_XLP:
1707                 /* don't need to worry about L2, fully coherent */
1708                 return;
1709
1710         default:
1711                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1712                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1713                                     MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1714                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1715 #ifdef CONFIG_MIPS_CPU_SCACHE
1716                         if (mips_sc_init ()) {
1717                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1718                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1719                                        scache_size >> 10,
1720                                        way_string[c->scache.ways], c->scache.linesz);
1721                         }
1722 #else
1723                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1724                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1725 #endif
1726                         return;
1727                 }
1728                 sc_present = 0;
1729         }
1730
1731         if (!sc_present)
1732                 return;
1733
1734         /* compute a couple of other cache variables */
1735         c->scache.waysize = scache_size / c->scache.ways;
1736
1737         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1738
1739         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1740                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1741
1742         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1743 }
1744
1745 void au1x00_fixup_config_od(void)
1746 {
1747         /*
1748          * c0_config.od (bit 19) was write only (and read as 0)
1749          * on the early revisions of Alchemy SOCs.  It disables the bus
1750          * transaction overlapping and needs to be set to fix various errata.
1751          */
1752         switch (read_c0_prid()) {
1753         case 0x00030100: /* Au1000 DA */
1754         case 0x00030201: /* Au1000 HA */
1755         case 0x00030202: /* Au1000 HB */
1756         case 0x01030200: /* Au1500 AB */
1757         /*
1758          * Au1100 errata actually keeps silence about this bit, so we set it
1759          * just in case for those revisions that require it to be set according
1760          * to the (now gone) cpu table.
1761          */
1762         case 0x02030200: /* Au1100 AB */
1763         case 0x02030201: /* Au1100 BA */
1764         case 0x02030202: /* Au1100 BC */
1765                 set_c0_config(1 << 19);
1766                 break;
1767         }
1768 }
1769
1770 /* CP0 hazard avoidance. */
1771 #define NXP_BARRIER()                                                   \
1772          __asm__ __volatile__(                                          \
1773         ".set noreorder\n\t"                                            \
1774         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1775         ".set reorder\n\t")
1776
1777 static void nxp_pr4450_fixup_config(void)
1778 {
1779         unsigned long config0;
1780
1781         config0 = read_c0_config();
1782
1783         /* clear all three cache coherency fields */
1784         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1785         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1786                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1787                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1788         write_c0_config(config0);
1789         NXP_BARRIER();
1790 }
1791
1792 static int cca = -1;
1793
1794 static int __init cca_setup(char *str)
1795 {
1796         get_option(&str, &cca);
1797
1798         return 0;
1799 }
1800
1801 early_param("cca", cca_setup);
1802
1803 static void coherency_setup(void)
1804 {
1805         if (cca < 0 || cca > 7)
1806                 cca = read_c0_config() & CONF_CM_CMASK;
1807         _page_cachable_default = cca << _CACHE_SHIFT;
1808
1809         pr_debug("Using cache attribute %d\n", cca);
1810         change_c0_config(CONF_CM_CMASK, cca);
1811
1812         /*
1813          * c0_status.cu=0 specifies that updates by the sc instruction use
1814          * the coherency mode specified by the TLB; 1 means cachable
1815          * coherent update on write will be used.  Not all processors have
1816          * this bit and; some wire it to zero, others like Toshiba had the
1817          * silly idea of putting something else there ...
1818          */
1819         switch (current_cpu_type()) {
1820         case CPU_R4000PC:
1821         case CPU_R4000SC:
1822         case CPU_R4000MC:
1823         case CPU_R4400PC:
1824         case CPU_R4400SC:
1825         case CPU_R4400MC:
1826                 clear_c0_config(CONF_CU);
1827                 break;
1828         /*
1829          * We need to catch the early Alchemy SOCs with
1830          * the write-only co_config.od bit and set it back to one on:
1831          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1832          */
1833         case CPU_ALCHEMY:
1834                 au1x00_fixup_config_od();
1835                 break;
1836
1837         case PRID_IMP_PR4450:
1838                 nxp_pr4450_fixup_config();
1839                 break;
1840         }
1841 }
1842
1843 static void r4k_cache_error_setup(void)
1844 {
1845         extern char __weak except_vec2_generic;
1846         extern char __weak except_vec2_sb1;
1847
1848         switch (current_cpu_type()) {
1849         case CPU_SB1:
1850         case CPU_SB1A:
1851                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1852                 break;
1853
1854         default:
1855                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1856                 break;
1857         }
1858 }
1859
1860 void r4k_cache_init(void)
1861 {
1862         extern void build_clear_page(void);
1863         extern void build_copy_page(void);
1864         struct cpuinfo_mips *c = &current_cpu_data;
1865
1866         probe_pcache();
1867         probe_vcache();
1868         setup_scache();
1869
1870         r4k_blast_dcache_page_setup();
1871         r4k_blast_dcache_page_indexed_setup();
1872         r4k_blast_dcache_setup();
1873         r4k_blast_icache_page_setup();
1874         r4k_blast_icache_page_indexed_setup();
1875         r4k_blast_icache_setup();
1876         r4k_blast_scache_page_setup();
1877         r4k_blast_scache_page_indexed_setup();
1878         r4k_blast_scache_setup();
1879         r4k_blast_scache_node_setup();
1880 #ifdef CONFIG_EVA
1881         r4k_blast_dcache_user_page_setup();
1882         r4k_blast_icache_user_page_setup();
1883 #endif
1884
1885         /*
1886          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1887          * This code supports virtually indexed processors and will be
1888          * unnecessarily inefficient on physically indexed processors.
1889          */
1890         if (c->dcache.linesz && cpu_has_dc_aliases)
1891                 shm_align_mask = max_t( unsigned long,
1892                                         c->dcache.sets * c->dcache.linesz - 1,
1893                                         PAGE_SIZE - 1);
1894         else
1895                 shm_align_mask = PAGE_SIZE-1;
1896
1897         __flush_cache_vmap      = r4k__flush_cache_vmap;
1898         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1899
1900         flush_cache_all         = cache_noop;
1901         __flush_cache_all       = r4k___flush_cache_all;
1902         flush_cache_mm          = r4k_flush_cache_mm;
1903         flush_cache_page        = r4k_flush_cache_page;
1904         flush_cache_range       = r4k_flush_cache_range;
1905
1906         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1907
1908         flush_icache_all        = r4k_flush_icache_all;
1909         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1910         flush_data_cache_page   = r4k_flush_data_cache_page;
1911         flush_icache_range      = r4k_flush_icache_range;
1912         local_flush_icache_range        = local_r4k_flush_icache_range;
1913         __flush_icache_user_range       = r4k_flush_icache_user_range;
1914         __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1915
1916 #ifdef CONFIG_DMA_NONCOHERENT
1917 #ifdef CONFIG_DMA_MAYBE_COHERENT
1918         if (coherentio == IO_COHERENCE_ENABLED ||
1919             (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
1920                 _dma_cache_wback_inv    = (void *)cache_noop;
1921                 _dma_cache_wback        = (void *)cache_noop;
1922                 _dma_cache_inv          = (void *)cache_noop;
1923         } else
1924 #endif /* CONFIG_DMA_MAYBE_COHERENT */
1925         {
1926                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1927                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1928                 _dma_cache_inv          = r4k_dma_cache_inv;
1929         }
1930 #endif /* CONFIG_DMA_NONCOHERENT */
1931
1932         build_clear_page();
1933         build_copy_page();
1934
1935         /*
1936          * We want to run CMP kernels on core with and without coherent
1937          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1938          * or not to flush caches.
1939          */
1940         local_r4k___flush_cache_all(NULL);
1941
1942         coherency_setup();
1943         board_cache_error_setup = r4k_cache_error_setup;
1944
1945         /*
1946          * Per-CPU overrides
1947          */
1948         switch (current_cpu_type()) {
1949         case CPU_BMIPS4350:
1950         case CPU_BMIPS4380:
1951                 /* No IPI is needed because all CPUs share the same D$ */
1952                 flush_data_cache_page = r4k_blast_dcache_page;
1953                 break;
1954         case CPU_BMIPS5000:
1955                 /* We lose our superpowers if L2 is disabled */
1956                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1957                         break;
1958
1959                 /* I$ fills from D$ just by emptying the write buffers */
1960                 flush_cache_page = (void *)b5k_instruction_hazard;
1961                 flush_cache_range = (void *)b5k_instruction_hazard;
1962                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1963                 flush_data_cache_page = (void *)b5k_instruction_hazard;
1964                 flush_icache_range = (void *)b5k_instruction_hazard;
1965                 local_flush_icache_range = (void *)b5k_instruction_hazard;
1966
1967
1968                 /* Optimization: an L2 flush implicitly flushes the L1 */
1969                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1970                 break;
1971         case CPU_LOONGSON64:
1972                 /* Loongson-3 maintains cache coherency by hardware */
1973                 __flush_cache_all       = cache_noop;
1974                 __flush_cache_vmap      = cache_noop;
1975                 __flush_cache_vunmap    = cache_noop;
1976                 __flush_kernel_vmap_range = (void *)cache_noop;
1977                 flush_cache_mm          = (void *)cache_noop;
1978                 flush_cache_page        = (void *)cache_noop;
1979                 flush_cache_range       = (void *)cache_noop;
1980                 flush_icache_all        = (void *)cache_noop;
1981                 flush_data_cache_page   = (void *)cache_noop;
1982                 local_flush_data_cache_page     = (void *)cache_noop;
1983                 break;
1984         }
1985 }
1986
1987 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1988                                void *v)
1989 {
1990         switch (cmd) {
1991         case CPU_PM_ENTER_FAILED:
1992         case CPU_PM_EXIT:
1993                 coherency_setup();
1994                 break;
1995         }
1996
1997         return NOTIFY_OK;
1998 }
1999
2000 static struct notifier_block r4k_cache_pm_notifier_block = {
2001         .notifier_call = r4k_cache_pm_notifier,
2002 };
2003
2004 int __init r4k_cache_init_pm(void)
2005 {
2006         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2007 }
2008 arch_initcall(r4k_cache_init_pm);