arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/hardirq.h>
  11 #include <linux/init.h>
  12 #include <linux/highmem.h>
  13 #include <linux/kernel.h>
  14 #include <linux/linkage.h>
  15 #include <linux/preempt.h>
  16 #include <linux/sched.h>
  17 #include <linux/smp.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/bitops.h>
  21
  22 #include <asm/bcache.h>
  23 #include <asm/bootinfo.h>
  24 #include <asm/cache.h>
  25 #include <asm/cacheops.h>
  26 #include <asm/cpu.h>
  27 #include <asm/cpu-features.h>
  28 #include <asm/io.h>
  29 #include <asm/page.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/r4kcache.h>
  32 #include <asm/sections.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/war.h>
  35 #include <asm/cacheflush.h> /* for run_uncached() */
  36 #include <asm/traps.h>
  37 #include <asm/dma-coherence.h>
  38
  39 /*
  40  * Special Variant of smp_call_function for use by cache functions:
  41  *
  42  *  o No return value
  43  *  o collapses to normal function call on UP kernels
  44  *  o collapses to normal function call on systems with a single shared
  45  *    primary cache.
  46  *  o doesn't disable interrupts on the local CPU
  47  */
  48 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  49 {
  50         preempt_disable();
  51
  52 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
  53         smp_call_function(func, info, 1);
  54 #endif
  55         func(info);
  56         preempt_enable();
  57 }
  58
  59 #if defined(CONFIG_MIPS_CMP)
  60 #define cpu_has_safe_index_cacheops 0
  61 #else
  62 #define cpu_has_safe_index_cacheops 1
  63 #endif
  64
  65 /*
  66  * Must die.
  67  */
  68 static unsigned long icache_size __read_mostly;
  69 static unsigned long dcache_size __read_mostly;
  70 static unsigned long scache_size __read_mostly;
  71
  72 /*
  73  * Dummy cache handling routines for machines without boardcaches
  74  */
  75 static void cache_noop(void) {}
  76
  77 static struct bcache_ops no_sc_ops = {
  78         .bc_enable = (void *)cache_noop,
  79         .bc_disable = (void *)cache_noop,
  80         .bc_wback_inv = (void *)cache_noop,
  81         .bc_inv = (void *)cache_noop
  82 };
  83
  84 struct bcache_ops *bcops = &no_sc_ops;
  85
  86 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  87 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  88
  89 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  90 do {                                                                    \
  91         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  92                 *(volatile unsigned long *)CKSEG1;                      \
  93         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  94                 __asm__ __volatile__("nop;nop;nop;nop");                \
  95 } while (0)
  96
  97 static void (*r4k_blast_dcache_page)(unsigned long addr);
  98
  99 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 100 {
 101         R4600_HIT_CACHEOP_WAR_IMPL;
 102         blast_dcache32_page(addr);
 103 }
 104
 105 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 106 {
 107         R4600_HIT_CACHEOP_WAR_IMPL;
 108         blast_dcache64_page(addr);
 109 }
 110
 111 static void __cpuinit r4k_blast_dcache_page_setup(void)
 112 {
 113         unsigned long  dc_lsize = cpu_dcache_line_size();
 114
 115         if (dc_lsize == 0)
 116                 r4k_blast_dcache_page = (void *)cache_noop;
 117         else if (dc_lsize == 16)
 118                 r4k_blast_dcache_page = blast_dcache16_page;
 119         else if (dc_lsize == 32)
 120                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 121         else if (dc_lsize == 64)
 122                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 123 }
 124
 125 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 126
 127 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
 128 {
 129         unsigned long dc_lsize = cpu_dcache_line_size();
 130
 131         if (dc_lsize == 0)
 132                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 133         else if (dc_lsize == 16)
 134                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 135         else if (dc_lsize == 32)
 136                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 137         else if (dc_lsize == 64)
 138                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 139 }
 140
 141 void (* r4k_blast_dcache)(void);
 142 EXPORT_SYMBOL(r4k_blast_dcache);
 143
 144 static void __cpuinit r4k_blast_dcache_setup(void)
 145 {
 146         unsigned long dc_lsize = cpu_dcache_line_size();
 147
 148         if (dc_lsize == 0)
 149                 r4k_blast_dcache = (void *)cache_noop;
 150         else if (dc_lsize == 16)
 151                 r4k_blast_dcache = blast_dcache16;
 152         else if (dc_lsize == 32)
 153                 r4k_blast_dcache = blast_dcache32;
 154         else if (dc_lsize == 64)
 155                 r4k_blast_dcache = blast_dcache64;
 156 }
 157
 158 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 159 #define JUMP_TO_ALIGN(order) \
 160         __asm__ __volatile__( \
 161                 "b\t1f\n\t" \
 162                 ".align\t" #order "\n\t" \
 163                 "1:\n\t" \
 164                 )
 165 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 166 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 167
 168 static inline void blast_r4600_v1_icache32(void)
 169 {
 170         unsigned long flags;
 171
 172         local_irq_save(flags);
 173         blast_icache32();
 174         local_irq_restore(flags);
 175 }
 176
 177 static inline void tx49_blast_icache32(void)
 178 {
 179         unsigned long start = INDEX_BASE;
 180         unsigned long end = start + current_cpu_data.icache.waysize;
 181         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 182         unsigned long ws_end = current_cpu_data.icache.ways <<
 183                                current_cpu_data.icache.waybit;
 184         unsigned long ws, addr;
 185
 186         CACHE32_UNROLL32_ALIGN2;
 187         /* I'm in even chunk.  blast odd chunks */
 188         for (ws = 0; ws < ws_end; ws += ws_inc)
 189                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 190                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 191         CACHE32_UNROLL32_ALIGN;
 192         /* I'm in odd chunk.  blast even chunks */
 193         for (ws = 0; ws < ws_end; ws += ws_inc)
 194                 for (addr = start; addr < end; addr += 0x400 * 2)
 195                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 196 }
 197
 198 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 199 {
 200         unsigned long flags;
 201
 202         local_irq_save(flags);
 203         blast_icache32_page_indexed(page);
 204         local_irq_restore(flags);
 205 }
 206
 207 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 208 {
 209         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 210         unsigned long start = INDEX_BASE + (page & indexmask);
 211         unsigned long end = start + PAGE_SIZE;
 212         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 213         unsigned long ws_end = current_cpu_data.icache.ways <<
 214                                current_cpu_data.icache.waybit;
 215         unsigned long ws, addr;
 216
 217         CACHE32_UNROLL32_ALIGN2;
 218         /* I'm in even chunk.  blast odd chunks */
 219         for (ws = 0; ws < ws_end; ws += ws_inc)
 220                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 221                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 222         CACHE32_UNROLL32_ALIGN;
 223         /* I'm in odd chunk.  blast even chunks */
 224         for (ws = 0; ws < ws_end; ws += ws_inc)
 225                 for (addr = start; addr < end; addr += 0x400 * 2)
 226                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 227 }
 228
 229 static void (* r4k_blast_icache_page)(unsigned long addr);
 230
 231 static void __cpuinit r4k_blast_icache_page_setup(void)
 232 {
 233         unsigned long ic_lsize = cpu_icache_line_size();
 234
 235         if (ic_lsize == 0)
 236                 r4k_blast_icache_page = (void *)cache_noop;
 237         else if (ic_lsize == 16)
 238                 r4k_blast_icache_page = blast_icache16_page;
 239         else if (ic_lsize == 32)
 240                 r4k_blast_icache_page = blast_icache32_page;
 241         else if (ic_lsize == 64)
 242                 r4k_blast_icache_page = blast_icache64_page;
 243 }
 244
 245
 246 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 247
 248 static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
 249 {
 250         unsigned long ic_lsize = cpu_icache_line_size();
 251
 252         if (ic_lsize == 0)
 253                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 254         else if (ic_lsize == 16)
 255                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 256         else if (ic_lsize == 32) {
 257                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 258                         r4k_blast_icache_page_indexed =
 259                                 blast_icache32_r4600_v1_page_indexed;
 260                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 261                         r4k_blast_icache_page_indexed =
 262                                 tx49_blast_icache32_page_indexed;
 263                 else
 264                         r4k_blast_icache_page_indexed =
 265                                 blast_icache32_page_indexed;
 266         } else if (ic_lsize == 64)
 267                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 268 }
 269
 270 void (* r4k_blast_icache)(void);
 271 EXPORT_SYMBOL(r4k_blast_icache);
 272
 273 static void __cpuinit r4k_blast_icache_setup(void)
 274 {
 275         unsigned long ic_lsize = cpu_icache_line_size();
 276
 277         if (ic_lsize == 0)
 278                 r4k_blast_icache = (void *)cache_noop;
 279         else if (ic_lsize == 16)
 280                 r4k_blast_icache = blast_icache16;
 281         else if (ic_lsize == 32) {
 282                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 283                         r4k_blast_icache = blast_r4600_v1_icache32;
 284                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 285                         r4k_blast_icache = tx49_blast_icache32;
 286                 else
 287                         r4k_blast_icache = blast_icache32;
 288         } else if (ic_lsize == 64)
 289                 r4k_blast_icache = blast_icache64;
 290 }
 291
 292 static void (* r4k_blast_scache_page)(unsigned long addr);
 293
 294 static void __cpuinit r4k_blast_scache_page_setup(void)
 295 {
 296         unsigned long sc_lsize = cpu_scache_line_size();
 297
 298         if (scache_size == 0)
 299                 r4k_blast_scache_page = (void *)cache_noop;
 300         else if (sc_lsize == 16)
 301                 r4k_blast_scache_page = blast_scache16_page;
 302         else if (sc_lsize == 32)
 303                 r4k_blast_scache_page = blast_scache32_page;
 304         else if (sc_lsize == 64)
 305                 r4k_blast_scache_page = blast_scache64_page;
 306         else if (sc_lsize == 128)
 307                 r4k_blast_scache_page = blast_scache128_page;
 308 }
 309
 310 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 311
 312 static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
 313 {
 314         unsigned long sc_lsize = cpu_scache_line_size();
 315
 316         if (scache_size == 0)
 317                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 318         else if (sc_lsize == 16)
 319                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 320         else if (sc_lsize == 32)
 321                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 322         else if (sc_lsize == 64)
 323                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 324         else if (sc_lsize == 128)
 325                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 326 }
 327
 328 static void (* r4k_blast_scache)(void);
 329
 330 static void __cpuinit r4k_blast_scache_setup(void)
 331 {
 332         unsigned long sc_lsize = cpu_scache_line_size();
 333
 334         if (scache_size == 0)
 335                 r4k_blast_scache = (void *)cache_noop;
 336         else if (sc_lsize == 16)
 337                 r4k_blast_scache = blast_scache16;
 338         else if (sc_lsize == 32)
 339                 r4k_blast_scache = blast_scache32;
 340         else if (sc_lsize == 64)
 341                 r4k_blast_scache = blast_scache64;
 342         else if (sc_lsize == 128)
 343                 r4k_blast_scache = blast_scache128;
 344 }
 345
 346 static inline void local_r4k___flush_cache_all(void * args)
 347 {
 348 #if defined(CONFIG_CPU_LOONGSON2)
 349         r4k_blast_scache();
 350         return;
 351 #endif
 352         r4k_blast_dcache();
 353         r4k_blast_icache();
 354
 355         switch (current_cpu_type()) {
 356         case CPU_R4000SC:
 357         case CPU_R4000MC:
 358         case CPU_R4400SC:
 359         case CPU_R4400MC:
 360         case CPU_R10000:
 361         case CPU_R12000:
 362         case CPU_R14000:
 363                 r4k_blast_scache();
 364         }
 365 }
 366
 367 static void r4k___flush_cache_all(void)
 368 {
 369         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 370 }
 371
 372 static inline int has_valid_asid(const struct mm_struct *mm)
 373 {
 374 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 375         int i;
 376
 377         for_each_online_cpu(i)
 378                 if (cpu_context(i, mm))
 379                         return 1;
 380
 381         return 0;
 382 #else
 383         return cpu_context(smp_processor_id(), mm);
 384 #endif
 385 }
 386
 387 static void r4k__flush_cache_vmap(void)
 388 {
 389         r4k_blast_dcache();
 390 }
 391
 392 static void r4k__flush_cache_vunmap(void)
 393 {
 394         r4k_blast_dcache();
 395 }
 396
 397 static inline void local_r4k_flush_cache_range(void * args)
 398 {
 399         struct vm_area_struct *vma = args;
 400         int exec = vma->vm_flags & VM_EXEC;
 401
 402         if (!(has_valid_asid(vma->vm_mm)))
 403                 return;
 404
 405         r4k_blast_dcache();
 406         if (exec)
 407                 r4k_blast_icache();
 408 }
 409
 410 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 411         unsigned long start, unsigned long end)
 412 {
 413         int exec = vma->vm_flags & VM_EXEC;
 414
 415         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 416                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 417 }
 418
 419 static inline void local_r4k_flush_cache_mm(void * args)
 420 {
 421         struct mm_struct *mm = args;
 422
 423         if (!has_valid_asid(mm))
 424                 return;
 425
 426         /*
 427          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 428          * only flush the primary caches but R10000 and R12000 behave sane ...
 429          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 430          * caches, so we can bail out early.
 431          */
 432         if (current_cpu_type() == CPU_R4000SC ||
 433             current_cpu_type() == CPU_R4000MC ||
 434             current_cpu_type() == CPU_R4400SC ||
 435             current_cpu_type() == CPU_R4400MC) {
 436                 r4k_blast_scache();
 437                 return;
 438         }
 439
 440         r4k_blast_dcache();
 441 }
 442
 443 static void r4k_flush_cache_mm(struct mm_struct *mm)
 444 {
 445         if (!cpu_has_dc_aliases)
 446                 return;
 447
 448         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 449 }
 450
 451 struct flush_cache_page_args {
 452         struct vm_area_struct *vma;
 453         unsigned long addr;
 454         unsigned long pfn;
 455 };
 456
 457 static inline void local_r4k_flush_cache_page(void *args)
 458 {
 459         struct flush_cache_page_args *fcp_args = args;
 460         struct vm_area_struct *vma = fcp_args->vma;
 461         unsigned long addr = fcp_args->addr;
 462         struct page *page = pfn_to_page(fcp_args->pfn);
 463         int exec = vma->vm_flags & VM_EXEC;
 464         struct mm_struct *mm = vma->vm_mm;
 465         int map_coherent = 0;
 466         pgd_t *pgdp;
 467         pud_t *pudp;
 468         pmd_t *pmdp;
 469         pte_t *ptep;
 470         void *vaddr;
 471
 472         /*
 473          * If ownes no valid ASID yet, cannot possibly have gotten
 474          * this page into the cache.
 475          */
 476         if (!has_valid_asid(mm))
 477                 return;
 478
 479         addr &= PAGE_MASK;
 480         pgdp = pgd_offset(mm, addr);
 481         pudp = pud_offset(pgdp, addr);
 482         pmdp = pmd_offset(pudp, addr);
 483         ptep = pte_offset(pmdp, addr);
 484
 485         /*
 486          * If the page isn't marked valid, the page cannot possibly be
 487          * in the cache.
 488          */
 489         if (!(pte_present(*ptep)))
 490                 return;
 491
 492         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 493                 vaddr = NULL;
 494         else {
 495                 /*
 496                  * Use kmap_coherent or kmap_atomic to do flushes for
 497                  * another ASID than the current one.
 498                  */
 499                 map_coherent = (cpu_has_dc_aliases &&
 500                                 page_mapped(page) && !Page_dcache_dirty(page));
 501                 if (map_coherent)
 502                         vaddr = kmap_coherent(page, addr);
 503                 else
 504                         vaddr = kmap_atomic(page);
 505                 addr = (unsigned long)vaddr;
 506         }
 507
 508         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 509                 r4k_blast_dcache_page(addr);
 510                 if (exec && !cpu_icache_snoops_remote_store)
 511                         r4k_blast_scache_page(addr);
 512         }
 513         if (exec) {
 514                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 515                         int cpu = smp_processor_id();
 516
 517                         if (cpu_context(cpu, mm) != 0)
 518                                 drop_mmu_context(mm, cpu);
 519                 } else
 520                         r4k_blast_icache_page(addr);
 521         }
 522
 523         if (vaddr) {
 524                 if (map_coherent)
 525                         kunmap_coherent();
 526                 else
 527                         kunmap_atomic(vaddr);
 528         }
 529 }
 530
 531 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 532         unsigned long addr, unsigned long pfn)
 533 {
 534         struct flush_cache_page_args args;
 535
 536         args.vma = vma;
 537         args.addr = addr;
 538         args.pfn = pfn;
 539
 540         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 541 }
 542
 543 static inline void local_r4k_flush_data_cache_page(void * addr)
 544 {
 545         r4k_blast_dcache_page((unsigned long) addr);
 546 }
 547
 548 static void r4k_flush_data_cache_page(unsigned long addr)
 549 {
 550         if (in_atomic())
 551                 local_r4k_flush_data_cache_page((void *)addr);
 552         else
 553                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 554 }
 555
 556 struct flush_icache_range_args {
 557         unsigned long start;
 558         unsigned long end;
 559 };
 560
 561 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 562 {
 563         if (!cpu_has_ic_fills_f_dc) {
 564                 if (end - start >= dcache_size) {
 565                         r4k_blast_dcache();
 566                 } else {
 567                         R4600_HIT_CACHEOP_WAR_IMPL;
 568                         protected_blast_dcache_range(start, end);
 569                 }
 570         }
 571
 572         if (end - start > icache_size)
 573                 r4k_blast_icache();
 574         else
 575                 protected_blast_icache_range(start, end);
 576 }
 577
 578 static inline void local_r4k_flush_icache_range_ipi(void *args)
 579 {
 580         struct flush_icache_range_args *fir_args = args;
 581         unsigned long start = fir_args->start;
 582         unsigned long end = fir_args->end;
 583
 584         local_r4k_flush_icache_range(start, end);
 585 }
 586
 587 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 588 {
 589         struct flush_icache_range_args args;
 590
 591         args.start = start;
 592         args.end = end;
 593
 594         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
 595         instruction_hazard();
 596 }
 597
 598 #ifdef CONFIG_DMA_NONCOHERENT
 599
 600 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 601 {
 602         /* Catch bad driver code */
 603         BUG_ON(size == 0);
 604
 605         preempt_disable();
 606         if (cpu_has_inclusive_pcaches) {
 607                 if (size >= scache_size)
 608                         r4k_blast_scache();
 609                 else
 610                         blast_scache_range(addr, addr + size);
 611                 preempt_enable();
 612                 __sync();
 613                 return;
 614         }
 615
 616         /*
 617          * Either no secondary cache or the available caches don't have the
 618          * subset property so we have to flush the primary caches
 619          * explicitly
 620          */
 621         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 622                 r4k_blast_dcache();
 623         } else {
 624                 R4600_HIT_CACHEOP_WAR_IMPL;
 625                 blast_dcache_range(addr, addr + size);
 626         }
 627         preempt_enable();
 628
 629         bc_wback_inv(addr, size);
 630         __sync();
 631 }
 632
 633 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 634 {
 635         /* Catch bad driver code */
 636         BUG_ON(size == 0);
 637
 638         preempt_disable();
 639         if (cpu_has_inclusive_pcaches) {
 640                 if (size >= scache_size)
 641                         r4k_blast_scache();
 642                 else {
 643                         /*
 644                          * There is no clearly documented alignment requirement
 645                          * for the cache instruction on MIPS processors and
 646                          * some processors, among them the RM5200 and RM7000
 647                          * QED processors will throw an address error for cache
 648                          * hit ops with insufficient alignment.  Solved by
 649                          * aligning the address to cache line size.
 650                          */
 651                         blast_inv_scache_range(addr, addr + size);
 652                 }
 653                 preempt_enable();
 654                 __sync();
 655                 return;
 656         }
 657
 658         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 659                 r4k_blast_dcache();
 660         } else {
 661                 R4600_HIT_CACHEOP_WAR_IMPL;
 662                 blast_inv_dcache_range(addr, addr + size);
 663         }
 664         preempt_enable();
 665
 666         bc_inv(addr, size);
 667         __sync();
 668 }
 669 #endif /* CONFIG_DMA_NONCOHERENT */
 670
 671 /*
 672  * While we're protected against bad userland addresses we don't care
 673  * very much about what happens in that case.  Usually a segmentation
 674  * fault will dump the process later on anyway ...
 675  */
 676 static void local_r4k_flush_cache_sigtramp(void * arg)
 677 {
 678         unsigned long ic_lsize = cpu_icache_line_size();
 679         unsigned long dc_lsize = cpu_dcache_line_size();
 680         unsigned long sc_lsize = cpu_scache_line_size();
 681         unsigned long addr = (unsigned long) arg;
 682
 683         R4600_HIT_CACHEOP_WAR_IMPL;
 684         if (dc_lsize)
 685                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 686         if (!cpu_icache_snoops_remote_store && scache_size)
 687                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 688         if (ic_lsize)
 689                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 690         if (MIPS4K_ICACHE_REFILL_WAR) {
 691                 __asm__ __volatile__ (
 692                         ".set push\n\t"
 693                         ".set noat\n\t"
 694                         ".set mips3\n\t"
 695 #ifdef CONFIG_32BIT
 696                         "la     $at,1f\n\t"
 697 #endif
 698 #ifdef CONFIG_64BIT
 699                         "dla    $at,1f\n\t"
 700 #endif
 701                         "cache  %0,($at)\n\t"
 702                         "nop; nop; nop\n"
 703                         "1:\n\t"
 704                         ".set pop"
 705                         :
 706                         : "i" (Hit_Invalidate_I));
 707         }
 708         if (MIPS_CACHE_SYNC_WAR)
 709                 __asm__ __volatile__ ("sync");
 710 }
 711
 712 static void r4k_flush_cache_sigtramp(unsigned long addr)
 713 {
 714         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 715 }
 716
 717 static void r4k_flush_icache_all(void)
 718 {
 719         if (cpu_has_vtag_icache)
 720                 r4k_blast_icache();
 721 }
 722
 723 struct flush_kernel_vmap_range_args {
 724         unsigned long   vaddr;
 725         int             size;
 726 };
 727
 728 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 729 {
 730         struct flush_kernel_vmap_range_args *vmra = args;
 731         unsigned long vaddr = vmra->vaddr;
 732         int size = vmra->size;
 733
 734         /*
 735          * Aliases only affect the primary caches so don't bother with
 736          * S-caches or T-caches.
 737          */
 738         if (cpu_has_safe_index_cacheops && size >= dcache_size)
 739                 r4k_blast_dcache();
 740         else {
 741                 R4600_HIT_CACHEOP_WAR_IMPL;
 742                 blast_dcache_range(vaddr, vaddr + size);
 743         }
 744 }
 745
 746 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 747 {
 748         struct flush_kernel_vmap_range_args args;
 749
 750         args.vaddr = (unsigned long) vaddr;
 751         args.size = size;
 752
 753         r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
 754 }
 755
 756 static inline void rm7k_erratum31(void)
 757 {
 758         const unsigned long ic_lsize = 32;
 759         unsigned long addr;
 760
 761         /* RM7000 erratum #31. The icache is screwed at startup. */
 762         write_c0_taglo(0);
 763         write_c0_taghi(0);
 764
 765         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 766                 __asm__ __volatile__ (
 767                         ".set push\n\t"
 768                         ".set noreorder\n\t"
 769                         ".set mips3\n\t"
 770                         "cache\t%1, 0(%0)\n\t"
 771                         "cache\t%1, 0x1000(%0)\n\t"
 772                         "cache\t%1, 0x2000(%0)\n\t"
 773                         "cache\t%1, 0x3000(%0)\n\t"
 774                         "cache\t%2, 0(%0)\n\t"
 775                         "cache\t%2, 0x1000(%0)\n\t"
 776                         "cache\t%2, 0x2000(%0)\n\t"
 777                         "cache\t%2, 0x3000(%0)\n\t"
 778                         "cache\t%1, 0(%0)\n\t"
 779                         "cache\t%1, 0x1000(%0)\n\t"
 780                         "cache\t%1, 0x2000(%0)\n\t"
 781                         "cache\t%1, 0x3000(%0)\n\t"
 782                         ".set pop\n"
 783                         :
 784                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 785         }
 786 }
 787
 788 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 789 {
 790         /*
 791          * Early versions of the 74K do not update the cache tags on a
 792          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 793          * aliases. In this case it is better to treat the cache as always
 794          * having aliases.
 795          */
 796         if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
 797                 c->dcache.flags |= MIPS_CACHE_VTAG;
 798         if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
 799                 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 800         if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
 801             ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
 802                 c->dcache.flags |= MIPS_CACHE_VTAG;
 803                 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 804         }
 805 }
 806
 807 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
 808         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 809 };
 810
 811 static void __cpuinit probe_pcache(void)
 812 {
 813         struct cpuinfo_mips *c = &current_cpu_data;
 814         unsigned int config = read_c0_config();
 815         unsigned int prid = read_c0_prid();
 816         unsigned long config1;
 817         unsigned int lsize;
 818
 819         switch (c->cputype) {
 820         case CPU_R4600:                 /* QED style two way caches? */
 821         case CPU_R4700:
 822         case CPU_R5000:
 823         case CPU_NEVADA:
 824                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 825                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 826                 c->icache.ways = 2;
 827                 c->icache.waybit = __ffs(icache_size/2);
 828
 829                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 830                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 831                 c->dcache.ways = 2;
 832                 c->dcache.waybit= __ffs(dcache_size/2);
 833
 834                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 835                 break;
 836
 837         case CPU_R5432:
 838         case CPU_R5500:
 839                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 840                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 841                 c->icache.ways = 2;
 842                 c->icache.waybit= 0;
 843
 844                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 845                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 846                 c->dcache.ways = 2;
 847                 c->dcache.waybit = 0;
 848
 849                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
 850                 break;
 851
 852         case CPU_TX49XX:
 853                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 854                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 855                 c->icache.ways = 4;
 856                 c->icache.waybit= 0;
 857
 858                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 859                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 860                 c->dcache.ways = 4;
 861                 c->dcache.waybit = 0;
 862
 863                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 864                 c->options |= MIPS_CPU_PREFETCH;
 865                 break;
 866
 867         case CPU_R4000PC:
 868         case CPU_R4000SC:
 869         case CPU_R4000MC:
 870         case CPU_R4400PC:
 871         case CPU_R4400SC:
 872         case CPU_R4400MC:
 873         case CPU_R4300:
 874                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 875                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 876                 c->icache.ways = 1;
 877                 c->icache.waybit = 0;   /* doesn't matter */
 878
 879                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 880                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 881                 c->dcache.ways = 1;
 882                 c->dcache.waybit = 0;   /* does not matter */
 883
 884                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 885                 break;
 886
 887         case CPU_R10000:
 888         case CPU_R12000:
 889         case CPU_R14000:
 890                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 891                 c->icache.linesz = 64;
 892                 c->icache.ways = 2;
 893                 c->icache.waybit = 0;
 894
 895                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 896                 c->dcache.linesz = 32;
 897                 c->dcache.ways = 2;
 898                 c->dcache.waybit = 0;
 899
 900                 c->options |= MIPS_CPU_PREFETCH;
 901                 break;
 902
 903         case CPU_VR4133:
 904                 write_c0_config(config & ~VR41_CONF_P4K);
 905         case CPU_VR4131:
 906                 /* Workaround for cache instruction bug of VR4131 */
 907                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 908                     c->processor_id == 0x0c82U) {
 909                         config |= 0x00400000U;
 910                         if (c->processor_id == 0x0c80U)
 911                                 config |= VR41_CONF_BP;
 912                         write_c0_config(config);
 913                 } else
 914                         c->options |= MIPS_CPU_CACHE_CDEX_P;
 915
 916                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 917                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 918                 c->icache.ways = 2;
 919                 c->icache.waybit = __ffs(icache_size/2);
 920
 921                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 922                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 923                 c->dcache.ways = 2;
 924                 c->dcache.waybit = __ffs(dcache_size/2);
 925                 break;
 926
 927         case CPU_VR41XX:
 928         case CPU_VR4111:
 929         case CPU_VR4121:
 930         case CPU_VR4122:
 931         case CPU_VR4181:
 932         case CPU_VR4181A:
 933                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 934                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 935                 c->icache.ways = 1;
 936                 c->icache.waybit = 0;   /* doesn't matter */
 937
 938                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 939                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 940                 c->dcache.ways = 1;
 941                 c->dcache.waybit = 0;   /* does not matter */
 942
 943                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 944                 break;
 945
 946         case CPU_RM7000:
 947                 rm7k_erratum31();
 948
 949                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 950                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 951                 c->icache.ways = 4;
 952                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
 953
 954                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 955                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 956                 c->dcache.ways = 4;
 957                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 958
 959                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 960                 c->options |= MIPS_CPU_PREFETCH;
 961                 break;
 962
 963         case CPU_LOONGSON2:
 964                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 965                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 966                 if (prid & 0x3)
 967                         c->icache.ways = 4;
 968                 else
 969                         c->icache.ways = 2;
 970                 c->icache.waybit = 0;
 971
 972                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 973                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 974                 if (prid & 0x3)
 975                         c->dcache.ways = 4;
 976                 else
 977                         c->dcache.ways = 2;
 978                 c->dcache.waybit = 0;
 979                 break;
 980
 981         default:
 982                 if (!(config & MIPS_CONF_M))
 983                         panic("Don't know how to probe P-caches on this cpu.");
 984
 985                 /*
 986                  * So we seem to be a MIPS32 or MIPS64 CPU
 987                  * So let's probe the I-cache ...
 988                  */
 989                 config1 = read_c0_config1();
 990
 991                 if ((lsize = ((config1 >> 19) & 7)))
 992                         c->icache.linesz = 2 << lsize;
 993                 else
 994                         c->icache.linesz = lsize;
 995                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
 996                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 997
 998                 icache_size = c->icache.sets *
 999                               c->icache.ways *
1000                               c->icache.linesz;
1001                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1002
1003                 if (config & 0x8)               /* VI bit */
1004                         c->icache.flags |= MIPS_CACHE_VTAG;
1005
1006                 /*
1007                  * Now probe the MIPS32 / MIPS64 data cache.
1008                  */
1009                 c->dcache.flags = 0;
1010
1011                 if ((lsize = ((config1 >> 10) & 7)))
1012                         c->dcache.linesz = 2 << lsize;
1013                 else
1014                         c->dcache.linesz= lsize;
1015                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1016                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1017
1018                 dcache_size = c->dcache.sets *
1019                               c->dcache.ways *
1020                               c->dcache.linesz;
1021                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1022
1023                 c->options |= MIPS_CPU_PREFETCH;
1024                 break;
1025         }
1026
1027         /*
1028          * Processor configuration sanity check for the R4000SC erratum
1029          * #5.  With page sizes larger than 32kB there is no possibility
1030          * to get a VCE exception anymore so we don't care about this
1031          * misconfiguration.  The case is rather theoretical anyway;
1032          * presumably no vendor is shipping his hardware in the "bad"
1033          * configuration.
1034          */
1035         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1036             !(config & CONF_SC) && c->icache.linesz != 16 &&
1037             PAGE_SIZE <= 0x8000)
1038                 panic("Improper R4000SC processor configuration detected");
1039
1040         /* compute a couple of other cache variables */
1041         c->icache.waysize = icache_size / c->icache.ways;
1042         c->dcache.waysize = dcache_size / c->dcache.ways;
1043
1044         c->icache.sets = c->icache.linesz ?
1045                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1046         c->dcache.sets = c->dcache.linesz ?
1047                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1048
1049         /*
1050          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1051          * 2-way virtually indexed so normally would suffer from aliases.  So
1052          * normally they'd suffer from aliases but magic in the hardware deals
1053          * with that for us so we don't need to take care ourselves.
1054          */
1055         switch (c->cputype) {
1056         case CPU_20KC:
1057         case CPU_25KF:
1058         case CPU_SB1:
1059         case CPU_SB1A:
1060         case CPU_XLR:
1061                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1062                 break;
1063
1064         case CPU_R10000:
1065         case CPU_R12000:
1066         case CPU_R14000:
1067                 break;
1068
1069         case CPU_M14KC:
1070         case CPU_M14KEC:
1071         case CPU_24K:
1072         case CPU_34K:
1073         case CPU_74K:
1074         case CPU_1004K:
1075                 if (c->cputype == CPU_74K)
1076                         alias_74k_erratum(c);
1077                 if ((read_c0_config7() & (1 << 16))) {
1078                         /* effectively physically indexed dcache,
1079                            thus no virtual aliases. */
1080                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1081                         break;
1082                 }
1083         default:
1084                 if (c->dcache.waysize > PAGE_SIZE)
1085                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1086         }
1087
1088         switch (c->cputype) {
1089         case CPU_20KC:
1090                 /*
1091                  * Some older 20Kc chips doesn't have the 'VI' bit in
1092                  * the config register.
1093                  */
1094                 c->icache.flags |= MIPS_CACHE_VTAG;
1095                 break;
1096
1097         case CPU_ALCHEMY:
1098                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1099                 break;
1100         }
1101
1102 #ifdef  CONFIG_CPU_LOONGSON2
1103         /*
1104          * LOONGSON2 has 4 way icache, but when using indexed cache op,
1105          * one op will act on all 4 ways
1106          */
1107         c->icache.ways = 1;
1108 #endif
1109
1110         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1111                icache_size >> 10,
1112                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1113                way_string[c->icache.ways], c->icache.linesz);
1114
1115         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1116                dcache_size >> 10, way_string[c->dcache.ways],
1117                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1118                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1119                         "cache aliases" : "no aliases",
1120                c->dcache.linesz);
1121 }
1122
1123 /*
1124  * If you even _breathe_ on this function, look at the gcc output and make sure
1125  * it does not pop things on and off the stack for the cache sizing loop that
1126  * executes in KSEG1 space or else you will crash and burn badly.  You have
1127  * been warned.
1128  */
1129 static int __cpuinit probe_scache(void)
1130 {
1131         unsigned long flags, addr, begin, end, pow2;
1132         unsigned int config = read_c0_config();
1133         struct cpuinfo_mips *c = &current_cpu_data;
1134
1135         if (config & CONF_SC)
1136                 return 0;
1137
1138         begin = (unsigned long) &_stext;
1139         begin &= ~((4 * 1024 * 1024) - 1);
1140         end = begin + (4 * 1024 * 1024);
1141
1142         /*
1143          * This is such a bitch, you'd think they would make it easy to do
1144          * this.  Away you daemons of stupidity!
1145          */
1146         local_irq_save(flags);
1147
1148         /* Fill each size-multiple cache line with a valid tag. */
1149         pow2 = (64 * 1024);
1150         for (addr = begin; addr < end; addr = (begin + pow2)) {
1151                 unsigned long *p = (unsigned long *) addr;
1152                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1153                 pow2 <<= 1;
1154         }
1155
1156         /* Load first line with zero (therefore invalid) tag. */
1157         write_c0_taglo(0);
1158         write_c0_taghi(0);
1159         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1160         cache_op(Index_Store_Tag_I, begin);
1161         cache_op(Index_Store_Tag_D, begin);
1162         cache_op(Index_Store_Tag_SD, begin);
1163
1164         /* Now search for the wrap around point. */
1165         pow2 = (128 * 1024);
1166         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1167                 cache_op(Index_Load_Tag_SD, addr);
1168                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1169                 if (!read_c0_taglo())
1170                         break;
1171                 pow2 <<= 1;
1172         }
1173         local_irq_restore(flags);
1174         addr -= begin;
1175
1176         scache_size = addr;
1177         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1178         c->scache.ways = 1;
1179         c->dcache.waybit = 0;           /* does not matter */
1180
1181         return 1;
1182 }
1183
1184 #if defined(CONFIG_CPU_LOONGSON2)
1185 static void __init loongson2_sc_init(void)
1186 {
1187         struct cpuinfo_mips *c = &current_cpu_data;
1188
1189         scache_size = 512*1024;
1190         c->scache.linesz = 32;
1191         c->scache.ways = 4;
1192         c->scache.waybit = 0;
1193         c->scache.waysize = scache_size / (c->scache.ways);
1194         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1195         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1196                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1197
1198         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1199 }
1200 #endif
1201
1202 extern int r5k_sc_init(void);
1203 extern int rm7k_sc_init(void);
1204 extern int mips_sc_init(void);
1205
1206 static void __cpuinit setup_scache(void)
1207 {
1208         struct cpuinfo_mips *c = &current_cpu_data;
1209         unsigned int config = read_c0_config();
1210         int sc_present = 0;
1211
1212         /*
1213          * Do the probing thing on R4000SC and R4400SC processors.  Other
1214          * processors don't have a S-cache that would be relevant to the
1215          * Linux memory management.
1216          */
1217         switch (c->cputype) {
1218         case CPU_R4000SC:
1219         case CPU_R4000MC:
1220         case CPU_R4400SC:
1221         case CPU_R4400MC:
1222                 sc_present = run_uncached(probe_scache);
1223                 if (sc_present)
1224                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1225                 break;
1226
1227         case CPU_R10000:
1228         case CPU_R12000:
1229         case CPU_R14000:
1230                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1231                 c->scache.linesz = 64 << ((config >> 13) & 1);
1232                 c->scache.ways = 2;
1233                 c->scache.waybit= 0;
1234                 sc_present = 1;
1235                 break;
1236
1237         case CPU_R5000:
1238         case CPU_NEVADA:
1239 #ifdef CONFIG_R5000_CPU_SCACHE
1240                 r5k_sc_init();
1241 #endif
1242                 return;
1243
1244         case CPU_RM7000:
1245 #ifdef CONFIG_RM7000_CPU_SCACHE
1246                 rm7k_sc_init();
1247 #endif
1248                 return;
1249
1250 #if defined(CONFIG_CPU_LOONGSON2)
1251         case CPU_LOONGSON2:
1252                 loongson2_sc_init();
1253                 return;
1254 #endif
1255         case CPU_XLP:
1256                 /* don't need to worry about L2, fully coherent */
1257                 return;
1258
1259         default:
1260                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1261                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1262 #ifdef CONFIG_MIPS_CPU_SCACHE
1263                         if (mips_sc_init ()) {
1264                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1265                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1266                                        scache_size >> 10,
1267                                        way_string[c->scache.ways], c->scache.linesz);
1268                         }
1269 #else
1270                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1271                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1272 #endif
1273                         return;
1274                 }
1275                 sc_present = 0;
1276         }
1277
1278         if (!sc_present)
1279                 return;
1280
1281         /* compute a couple of other cache variables */
1282         c->scache.waysize = scache_size / c->scache.ways;
1283
1284         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1285
1286         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1287                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1288
1289         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1290 }
1291
1292 void au1x00_fixup_config_od(void)
1293 {
1294         /*
1295          * c0_config.od (bit 19) was write only (and read as 0)
1296          * on the early revisions of Alchemy SOCs.  It disables the bus
1297          * transaction overlapping and needs to be set to fix various errata.
1298          */
1299         switch (read_c0_prid()) {
1300         case 0x00030100: /* Au1000 DA */
1301         case 0x00030201: /* Au1000 HA */
1302         case 0x00030202: /* Au1000 HB */
1303         case 0x01030200: /* Au1500 AB */
1304         /*
1305          * Au1100 errata actually keeps silence about this bit, so we set it
1306          * just in case for those revisions that require it to be set according
1307          * to the (now gone) cpu table.
1308          */
1309         case 0x02030200: /* Au1100 AB */
1310         case 0x02030201: /* Au1100 BA */
1311         case 0x02030202: /* Au1100 BC */
1312                 set_c0_config(1 << 19);
1313                 break;
1314         }
1315 }
1316
1317 /* CP0 hazard avoidance. */
1318 #define NXP_BARRIER()                                                   \
1319          __asm__ __volatile__(                                          \
1320         ".set noreorder\n\t"                                            \
1321         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1322         ".set reorder\n\t")
1323
1324 static void nxp_pr4450_fixup_config(void)
1325 {
1326         unsigned long config0;
1327
1328         config0 = read_c0_config();
1329
1330         /* clear all three cache coherency fields */
1331         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1332         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1333                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1334                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1335         write_c0_config(config0);
1336         NXP_BARRIER();
1337 }
1338
1339 static int __cpuinitdata cca = -1;
1340
1341 static int __init cca_setup(char *str)
1342 {
1343         get_option(&str, &cca);
1344
1345         return 0;
1346 }
1347
1348 early_param("cca", cca_setup);
1349
1350 static void __cpuinit coherency_setup(void)
1351 {
1352         if (cca < 0 || cca > 7)
1353                 cca = read_c0_config() & CONF_CM_CMASK;
1354         _page_cachable_default = cca << _CACHE_SHIFT;
1355
1356         pr_debug("Using cache attribute %d\n", cca);
1357         change_c0_config(CONF_CM_CMASK, cca);
1358
1359         /*
1360          * c0_status.cu=0 specifies that updates by the sc instruction use
1361          * the coherency mode specified by the TLB; 1 means cachable
1362          * coherent update on write will be used.  Not all processors have
1363          * this bit and; some wire it to zero, others like Toshiba had the
1364          * silly idea of putting something else there ...
1365          */
1366         switch (current_cpu_type()) {
1367         case CPU_R4000PC:
1368         case CPU_R4000SC:
1369         case CPU_R4000MC:
1370         case CPU_R4400PC:
1371         case CPU_R4400SC:
1372         case CPU_R4400MC:
1373                 clear_c0_config(CONF_CU);
1374                 break;
1375         /*
1376          * We need to catch the early Alchemy SOCs with
1377          * the write-only co_config.od bit and set it back to one on:
1378          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1379          */
1380         case CPU_ALCHEMY:
1381                 au1x00_fixup_config_od();
1382                 break;
1383
1384         case PRID_IMP_PR4450:
1385                 nxp_pr4450_fixup_config();
1386                 break;
1387         }
1388 }
1389
1390 static void __cpuinit r4k_cache_error_setup(void)
1391 {
1392         extern char __weak except_vec2_generic;
1393         extern char __weak except_vec2_sb1;
1394         struct cpuinfo_mips *c = &current_cpu_data;
1395
1396         switch (c->cputype) {
1397         case CPU_SB1:
1398         case CPU_SB1A:
1399                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1400                 break;
1401
1402         default:
1403                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1404                 break;
1405         }
1406 }
1407
1408 void __cpuinit r4k_cache_init(void)
1409 {
1410         extern void build_clear_page(void);
1411         extern void build_copy_page(void);
1412         struct cpuinfo_mips *c = &current_cpu_data;
1413
1414         probe_pcache();
1415         setup_scache();
1416
1417         r4k_blast_dcache_page_setup();
1418         r4k_blast_dcache_page_indexed_setup();
1419         r4k_blast_dcache_setup();
1420         r4k_blast_icache_page_setup();
1421         r4k_blast_icache_page_indexed_setup();
1422         r4k_blast_icache_setup();
1423         r4k_blast_scache_page_setup();
1424         r4k_blast_scache_page_indexed_setup();
1425         r4k_blast_scache_setup();
1426
1427         /*
1428          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1429          * This code supports virtually indexed processors and will be
1430          * unnecessarily inefficient on physically indexed processors.
1431          */
1432         if (c->dcache.linesz)
1433                 shm_align_mask = max_t( unsigned long,
1434                                         c->dcache.sets * c->dcache.linesz - 1,
1435                                         PAGE_SIZE - 1);
1436         else
1437                 shm_align_mask = PAGE_SIZE-1;
1438
1439         __flush_cache_vmap      = r4k__flush_cache_vmap;
1440         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1441
1442         flush_cache_all         = cache_noop;
1443         __flush_cache_all       = r4k___flush_cache_all;
1444         flush_cache_mm          = r4k_flush_cache_mm;
1445         flush_cache_page        = r4k_flush_cache_page;
1446         flush_cache_range       = r4k_flush_cache_range;
1447
1448         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1449
1450         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1451         flush_icache_all        = r4k_flush_icache_all;
1452         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1453         flush_data_cache_page   = r4k_flush_data_cache_page;
1454         flush_icache_range      = r4k_flush_icache_range;
1455         local_flush_icache_range        = local_r4k_flush_icache_range;
1456
1457 #if defined(CONFIG_DMA_NONCOHERENT)
1458         if (coherentio) {
1459                 _dma_cache_wback_inv    = (void *)cache_noop;
1460                 _dma_cache_wback        = (void *)cache_noop;
1461                 _dma_cache_inv          = (void *)cache_noop;
1462         } else {
1463                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1464                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1465                 _dma_cache_inv          = r4k_dma_cache_inv;
1466         }
1467 #endif
1468
1469         build_clear_page();
1470         build_copy_page();
1471
1472         /*
1473          * We want to run CMP kernels on core with and without coherent
1474          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1475          * or not to flush caches.
1476          */
1477         local_r4k___flush_cache_all(NULL);
1478
1479         coherency_setup();
1480         board_cache_error_setup = r4k_cache_error_setup;
1481 }