1 // SPDX-License-Identifier: GPL-2.0-only
2 /* IEEE754 floating point arithmetic
6 * MIPS floating point support
7 * Copyright (C) 1994-2000 Algorithmics Ltd.
10 #include "ieee754sp.h"
12 union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
27 switch (CLPAIR(xc, yc)) {
28 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
29 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
30 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
31 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
32 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
33 return ieee754sp_nanxcpt(y);
35 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
36 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
37 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
38 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
39 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
41 return ieee754sp_nanxcpt(x);
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
50 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
51 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
52 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
53 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
60 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
63 ieee754_setcx(IEEE754_INVALID_OPERATION);
64 return ieee754sp_indef();
66 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
67 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
68 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
69 return ieee754sp_inf(ys ^ 1);
71 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
72 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
73 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
79 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
83 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
85 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
86 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
89 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
90 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
95 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
98 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
102 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
106 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
109 /* flip sign of y and handle as add */
112 assert(xm & SP_HIDDEN_BIT);
113 assert(ym & SP_HIDDEN_BIT);
116 /* provide guard,round and stick bit space */
122 * have to shift y fraction right to align
127 } else if (ye > xe) {
129 * have to shift x fraction right to align
136 assert(xe <= SP_EMAX);
139 /* generate 28 bit result of adding two 27 bit numbers
143 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
144 SPXSRSX1(); /* shift preserving sticky */
154 if (ieee754_csr.rm == FPU_CSR_RD)
155 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */
157 return ieee754sp_zero(0); /* other round modes => sign = 1 */
159 /* normalize to rounding precision
161 while ((xm >> (SP_FBITS + 3)) == 0) {
167 return ieee754sp_format(xs, xe, xm);