1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020 Marvell International Ltd.
6 #ifndef __OCTEON_QLM_H__
7 #define __OCTEON_QLM_H__
9 /* Reference clock selector values for ref_clk_sel */
10 #define OCTEON_QLM_REF_CLK_100MHZ 0 /** 100 MHz */
11 #define OCTEON_QLM_REF_CLK_125MHZ 1 /** 125 MHz */
12 #define OCTEON_QLM_REF_CLK_156MHZ 2 /** 156.25 MHz */
13 #define OCTEON_QLM_REF_CLK_161MHZ 3 /** 161.1328125 MHz */
16 * Configure qlm/dlm speed and mode.
17 * @param qlm The QLM or DLM to configure
18 * @param speed The speed the QLM needs to be configured in Mhz.
19 * @param mode The QLM to be configured as SGMII/XAUI/PCIe.
20 * @param rc Only used for PCIe, rc = 1 for root complex mode, 0 for EP
22 * @param pcie_mode Only used when qlm/dlm are in pcie mode.
23 * @param ref_clk_sel Reference clock to use for 70XX where:
27 * 3: 161.1328125MHz (CN73XX and CN78XX only)
28 * @param ref_clk_input This selects which reference clock input to use. For
34 * cn78xx/cn76xx/cn73xx:
35 * 0: Internal clock (QLM[0-7]_REF_CLK)
39 * @return Return 0 on success or -1.
41 * @note When the 161MHz clock is used it can only be used for
42 * XLAUI mode with a 6316 speed or XFI mode with a 103125 speed.
43 * This rate is also only supported for CN73XX and CN78XX.
45 int octeon_configure_qlm(int qlm, int speed, int mode, int rc, int pcie_mode, int ref_clk_sel,
48 int octeon_configure_qlm_cn78xx(int node, int qlm, int speed, int mode, int rc, int pcie_mode,
49 int ref_clk_sel, int ref_clk_input);
52 * Some QLM speeds need to override the default tuning parameters
54 * @param node Node to configure
55 * @param qlm QLM to configure
56 * @param baud_mhz Desired speed in MHz
57 * @param lane Lane the apply the tuning parameters
58 * @param tx_swing Voltage swing. The higher the value the lower the voltage,
59 * the default value is 7.
60 * @param tx_pre pre-cursor pre-emphasis
61 * @param tx_post post-cursor pre-emphasis.
62 * @param tx_gain Transmit gain. Range 0-7
63 * @param tx_vboost Transmit voltage boost. Range 0-1
65 void octeon_qlm_tune_per_lane_v3(int node, int qlm, int baud_mhz, int lane, int tx_swing,
66 int tx_pre, int tx_post, int tx_gain, int tx_vboost);
69 * Some QLM speeds need to override the default tuning parameters
71 * @param node Node to configure
72 * @param qlm QLM to configure
73 * @param baud_mhz Desired speed in MHz
74 * @param tx_swing Voltage swing. The higher the value the lower the voltage,
75 * the default value is 7.
76 * @param tx_premptap bits [0:3] pre-cursor pre-emphasis, bits[4:8] post-cursor
78 * @param tx_gain Transmit gain. Range 0-7
79 * @param tx_vboost Transmit voltage boost. Range 0-1
81 void octeon_qlm_tune_v3(int node, int qlm, int baud_mhz, int tx_swing, int tx_premptap, int tx_gain,
85 * Disables DFE for the specified QLM lane(s).
86 * This function should only be called for low-loss channels.
88 * @param node Node to configure
89 * @param qlm QLM to configure
90 * @param lane Lane to configure, or -1 all lanes
91 * @param baud_mhz The speed the QLM needs to be configured in Mhz.
92 * @param mode The QLM to be configured as SGMII/XAUI/PCIe.
94 void octeon_qlm_dfe_disable(int node, int qlm, int lane, int baud_mhz, int mode);
97 * Some QLMs need to override the default pre-ctle for low loss channels.
99 * @param node Node to configure
100 * @param qlm QLM to configure
101 * @param pre_ctle pre-ctle settings for low loss channels
103 void octeon_qlm_set_channel_v3(int node, int qlm, int pre_ctle);
105 void octeon_init_qlm(int node);
107 int octeon_mcu_probe(int node);
109 #endif /* __OCTEON_QLM_H__ */