arch/mips/mach-octeon/include/mach/octeon_ddr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020 Marvell International Ltd.
   4  */
   5
   6 #ifndef __OCTEON_DDR_H_
   7 #define __OCTEON_DDR_H_
   8
   9 #include <env.h>
  10 #include <linux/compat.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <mach/octeon-model.h>
  14 #include <mach/cvmx/cvmx-lmcx-defs.h>
  15
  16 /* Mapping is done starting from 0x11800.80000000 */
  17 #define CVMX_L2C_CTL            0x00800000
  18 #define CVMX_L2C_BIG_CTL        0x00800030
  19 #define CVMX_L2C_TADX_INT(i)    (0x00a00028 + (((i) & 7) * 0x40000))
  20 #define CVMX_L2C_MCIX_INT(i)    (0x00c00028 + (((i) & 3) * 0x40000))
  21
  22 /* Some "external" (non-LMC) registers */
  23 #define CVMX_IPD_CLK_COUNT              0x00014F0000000338
  24 #define CVMX_FPA_CLK_COUNT              0x00012800000000F0
  25
  26 #define CVMX_NODE_MEM_SHIFT     40
  27
  28 #define DDR_INTERFACE_MAX       4
  29
  30 /* Private data struct */
  31 struct ddr_priv {
  32         void __iomem *lmc_base;
  33         void __iomem *l2c_base;
  34
  35         bool ddr_clock_initialized[DDR_INTERFACE_MAX];
  36         bool ddr_memory_preserved;
  37         u32 flags;
  38
  39         struct ram_info info;
  40 };
  41
  42 /* Short cut to convert a number to megabytes */
  43 #define MB(X)                   ((u64)(X) * (u64)(1024 * 1024))
  44
  45 #define octeon_is_cpuid(x)      (__OCTEON_IS_MODEL_COMPILE__(x, read_c0_prid()))
  46
  47 #define strtoull                simple_strtoull
  48
  49 /* Access LMC registers */
  50 static inline u64 lmc_rd(struct ddr_priv *priv, u64 addr)
  51 {
  52         return ioread64(priv->lmc_base + addr);
  53 }
  54
  55 static inline void lmc_wr(struct ddr_priv *priv, u64 addr, u64 val)
  56 {
  57         iowrite64(val, priv->lmc_base + addr);
  58 }
  59
  60 /* Access L2C registers */
  61 static inline u64 l2c_rd(struct ddr_priv *priv, u64 addr)
  62 {
  63         return ioread64(priv->l2c_base + addr);
  64 }
  65
  66 static inline void l2c_wr(struct ddr_priv *priv, u64 addr, u64 val)
  67 {
  68         iowrite64(val, priv->l2c_base + addr);
  69 }
  70
  71 /* Access other CSR registers not located inside the LMC address space */
  72 static inline u64 csr_rd(u64 addr)
  73 {
  74         void __iomem *base;
  75
  76         base = ioremap_nocache(addr, 0x100);
  77         return ioread64(base);
  78 }
  79
  80 static inline void csr_wr(u64 addr, u64 val)
  81 {
  82         void __iomem *base;
  83
  84         base = ioremap_nocache(addr, 0x100);
  85         return iowrite64(val, base);
  86 }
  87
  88 /* "Normal" access, without any offsets and/or mapping */
  89 static inline u64 cvmx_read64_uint64(u64 addr)
  90 {
  91         return readq((void *)addr);
  92 }
  93
  94 static inline void cvmx_write64_uint64(u64 addr, u64 val)
  95 {
  96         writeq(val, (void *)addr);
  97 }
  98
  99 /* Failsafe mode */
 100 #define FLAG_FAILSAFE_MODE              0x01000
 101 /* Note that the DDR clock initialized flags must be contiguous */
 102 /* Clock for DDR 0 initialized */
 103 #define FLAG_DDR0_CLK_INITIALIZED       0x02000
 104 /* Clock for DDR 1 initialized */
 105 #define FLAG_DDR1_CLK_INITIALIZED       0x04000
 106 /* Clock for DDR 2 initialized */
 107 #define FLAG_DDR2_CLK_INITIALIZED       0x08000
 108 /* Clock for DDR 3 initialized */
 109 #define FLAG_DDR3_CLK_INITIALIZED       0x10000
 110 /* Loaded into RAM externally */
 111 #define FLAG_RAM_RESIDENT               0x20000
 112 /* Verbose DDR information */
 113 #define FLAG_DDR_VERBOSE                0x40000
 114 /* Check env. for DDR variables */
 115 #define FLAG_DDR_DEBUG                  0x80000
 116 #define FLAG_DDR_TRACE_INIT             0x100000
 117 #define FLAG_MEMORY_PRESERVED           0x200000
 118 #define FLAG_DFM_VERBOSE                0x400000
 119 #define FLAG_DFM_TRACE_INIT             0x800000
 120 /* DFM memory clock initialized */
 121 #define FLAG_DFM_CLK_INITIALIZED        0x1000000
 122 /* EEPROM clock descr. missing */
 123 #define FLAG_CLOCK_DESC_MISSING         0x2000000
 124 /* EEPROM board descr. missing */
 125 #define FLAG_BOARD_DESC_MISSING         0x4000000
 126 #define FLAG_DDR_PROMPT                 0x8000000
 127
 128 #ifndef DDR_NO_DEBUG
 129 static inline int ddr_verbose(struct ddr_priv *priv)
 130 {
 131         return !!(priv->flags & FLAG_DDR_VERBOSE);
 132 }
 133
 134 static inline char *ddr_getenv_debug(struct ddr_priv *priv, char *name)
 135 {
 136         if (priv->flags & FLAG_FAILSAFE_MODE)
 137                 return NULL;
 138
 139         if (priv->flags & FLAG_DDR_DEBUG)
 140                 return env_get(name);
 141
 142         return NULL;
 143 }
 144 #else
 145 static inline int ddr_verbose(void)
 146 {
 147         return 0;
 148 }
 149 #endif
 150
 151 /* turn the variable name into a string */
 152 #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
 153 #define CVMX_TMP_STR2(x) #x
 154
 155 #define CVMX_SYNC asm volatile ("sync" : : : "memory")
 156
 157 #define CVMX_CACHE(op, address, offset)                                 \
 158         asm volatile ("cache " CVMX_TMP_STR(op) ", "                    \
 159                       CVMX_TMP_STR(offset) "(%[rbase])"                 \
 160                       : : [rbase] "d" (address))
 161
 162 /* unlock the state */
 163 #define CVMX_CACHE_WBIL2(address, offset)       \
 164         CVMX_CACHE(23, address, offset)
 165
 166 /* complete prefetches, invalidate entire dcache */
 167 #define CVMX_DCACHE_INVALIDATE                                  \
 168         { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
 169
 170 /**
 171  * cvmx_l2c_cfg
 172  *
 173  * Specify the RSL base addresses for the block
 174  *
 175  *                  L2C_CFG = L2C Configuration
 176  *
 177  * Description:
 178  */
 179 union cvmx_l2c_cfg {
 180         u64 u64;
 181         struct cvmx_l2c_cfg_s {
 182                 uint64_t reserved_20_63:44;
 183                 uint64_t bstrun:1;
 184                 uint64_t lbist:1;
 185                 uint64_t xor_bank:1;
 186                 uint64_t dpres1:1;
 187                 uint64_t dpres0:1;
 188                 uint64_t dfill_dis:1;
 189                 uint64_t fpexp:4;
 190                 uint64_t fpempty:1;
 191                 uint64_t fpen:1;
 192                 uint64_t idxalias:1;
 193                 uint64_t mwf_crd:4;
 194                 uint64_t rsp_arb_mode:1;
 195                 uint64_t rfb_arb_mode:1;
 196                 uint64_t lrf_arb_mode:1;
 197         } s;
 198 };
 199
 200 /**
 201  * cvmx_l2c_ctl
 202  *
 203  * L2C_CTL = L2C Control
 204  *
 205  *
 206  * Notes:
 207  * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.
 208  *
 209  * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE,
 210  * and VBFDBE errors for the purposes of testing error handling code.  When
 211  * one (or both) of these bits are set a PL2 which misses in the L2 will fill
 212  * with the appropriate error in the first 2 OWs of the fill. Software can
 213  * determine which OW pair gets the error by choosing the desired fill order
 214  * (address<6:5>).  A PL2 which hits in the L2 will not inject any errors.
 215  * Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss
 216  * likely (if multiple processors are involved software must be careful to be
 217  * sure no other processor or IO device can bring the block into the L2).
 218  *
 219  * To generate a VBFSBE or VBFDBE, software must first get the cache block
 220  * into the cache with an error using a PL2 which misses the L2.  Then a
 221  * store partial to a portion of the cache block without the error must
 222  * change the block to dirty.  Then, a subsequent WBL2/WBIL2/victim will
 223  * trigger the VBFSBE/VBFDBE error.
 224  */
 225 union cvmx_l2c_ctl {
 226         u64 u64;
 227         struct cvmx_l2c_ctl_s {
 228                 uint64_t reserved_29_63:35;
 229                 uint64_t rdf_fast:1;
 230                 uint64_t disstgl2i:1;
 231                 uint64_t l2dfsbe:1;
 232                 uint64_t l2dfdbe:1;
 233                 uint64_t discclk:1;
 234                 uint64_t maxvab:4;
 235                 uint64_t maxlfb:4;
 236                 uint64_t rsp_arb_mode:1;
 237                 uint64_t xmc_arb_mode:1;
 238                 uint64_t reserved_2_13:12;
 239                 uint64_t disecc:1;
 240                 uint64_t disidxalias:1;
 241         } s;
 242
 243         struct cvmx_l2c_ctl_cn73xx {
 244                 uint64_t reserved_32_63:32;
 245                 uint64_t ocla_qos:3;
 246                 uint64_t reserved_28_28:1;
 247                 uint64_t disstgl2i:1;
 248                 uint64_t reserved_25_26:2;
 249                 uint64_t discclk:1;
 250                 uint64_t reserved_16_23:8;
 251                 uint64_t rsp_arb_mode:1;
 252                 uint64_t xmc_arb_mode:1;
 253                 uint64_t rdf_cnt:8;
 254                 uint64_t reserved_4_5:2;
 255                 uint64_t disldwb:1;
 256                 uint64_t dissblkdty:1;
 257                 uint64_t disecc:1;
 258                 uint64_t disidxalias:1;
 259         } cn73xx;
 260
 261         struct cvmx_l2c_ctl_cn73xx cn78xx;
 262 };
 263
 264 /**
 265  * cvmx_l2c_big_ctl
 266  *
 267  * L2C_BIG_CTL = L2C Big memory control register
 268  *
 269  *
 270  * Notes:
 271  * (1) BIGRD interrupts can occur during normal operation as the PP's are
 272  * allowed to prefetch to non-existent memory locations.  Therefore,
 273  * BIGRD is for informational purposes only.
 274  *
 275  * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB,
 276  * and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR.
 277  * Additionally, L2C_ERR_XMC will be loaded.
 278  */
 279 union cvmx_l2c_big_ctl {
 280         u64 u64;
 281         struct cvmx_l2c_big_ctl_s {
 282                 uint64_t reserved_8_63:56;
 283                 uint64_t maxdram:4;
 284                 uint64_t reserved_0_3:4;
 285         } s;
 286         struct cvmx_l2c_big_ctl_cn61xx {
 287                 uint64_t reserved_8_63:56;
 288                 uint64_t maxdram:4;
 289                 uint64_t reserved_1_3:3;
 290                 uint64_t disable:1;
 291         } cn61xx;
 292         struct cvmx_l2c_big_ctl_cn61xx cn63xx;
 293         struct cvmx_l2c_big_ctl_cn61xx cn66xx;
 294         struct cvmx_l2c_big_ctl_cn61xx cn68xx;
 295         struct cvmx_l2c_big_ctl_cn61xx cn68xxp1;
 296         struct cvmx_l2c_big_ctl_cn70xx {
 297                 uint64_t reserved_8_63:56;
 298                 uint64_t maxdram:4;
 299                 uint64_t reserved_1_3:3;
 300                 uint64_t disbig:1;
 301         } cn70xx;
 302         struct cvmx_l2c_big_ctl_cn70xx cn70xxp1;
 303         struct cvmx_l2c_big_ctl_cn70xx cn73xx;
 304         struct cvmx_l2c_big_ctl_cn70xx cn78xx;
 305         struct cvmx_l2c_big_ctl_cn70xx cn78xxp1;
 306         struct cvmx_l2c_big_ctl_cn61xx cnf71xx;
 307         struct cvmx_l2c_big_ctl_cn70xx cnf75xx;
 308 };
 309
 310 struct rlevel_byte_data {
 311         int delay;
 312         int loop_total;
 313         int loop_count;
 314         int best;
 315         u64 bm;
 316         int bmerrs;
 317         int sqerrs;
 318         int bestsq;
 319 };
 320
 321 #define DEBUG_VALIDATE_BITMASK 0
 322 #if DEBUG_VALIDATE_BITMASK
 323 #define debug_bitmask_print printf
 324 #else
 325 #define debug_bitmask_print(...)
 326 #endif
 327
 328 #define RLEVEL_BITMASK_TRAILING_BITS_ERROR      5
 329 // FIXME? now less than TOOLONG
 330 #define RLEVEL_BITMASK_BUBBLE_BITS_ERROR        11
 331 #define RLEVEL_BITMASK_NARROW_ERROR             6
 332 #define RLEVEL_BITMASK_BLANK_ERROR              100
 333 #define RLEVEL_BITMASK_TOOLONG_ERROR            12
 334 #define RLEVEL_NONSEQUENTIAL_DELAY_ERROR        50
 335 #define RLEVEL_ADJACENT_DELAY_ERROR             30
 336
 337 /*
 338  * Apply a filter to the BITMASK results returned from Octeon
 339  * read-leveling to determine the most likely delay result.  This
 340  * computed delay may be used to qualify the delay result returned by
 341  * Octeon. Accumulate an error penalty for invalid characteristics of
 342  * the bitmask so that they can be used to select the most reliable
 343  * results.
 344  *
 345  * The algorithm searches for the largest contiguous MASK within a
 346  * maximum RANGE of bits beginning with the MSB.
 347  *
 348  * 1. a MASK with a WIDTH less than 4 will be penalized
 349  * 2. Bubbles in the bitmask that occur before or after the MASK
 350  *    will be penalized
 351  * 3. If there are no trailing bubbles then extra bits that occur
 352  *    beyond the maximum RANGE will be penalized.
 353  *
 354  *   +++++++++++++++++++++++++++++++++++++++++++++++++++
 355  *   +                                                 +
 356  *   +   e.g. bitmask = 27B00                          +
 357  *   +                                                 +
 358  *   +   63                  +--- mstart           0   +
 359  *   +   |                   |                     |   +
 360  *   +   |         +---------+     +--- fb         |   +
 361  *   +   |         |  range  |     |               |   +
 362  *   +   V         V         V     V               V   +
 363  *   +                                                 +
 364  *   +   0 0 ... 1 0 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0   +
 365  *   +                                                 +
 366  *   +           ^     ^     ^                         +
 367  *   +           |     | mask|                         +
 368  *   +     lb ---+     +-----+                         +
 369  *   +                  width                          +
 370  *   +                                                 +
 371  *   +++++++++++++++++++++++++++++++++++++++++++++++++++
 372  */
 373
 374 struct rlevel_bitmask {
 375         u64 bm;
 376         u8 mstart;
 377         u8 width;
 378         int errs;
 379 };
 380
 381 #define MASKRANGE_BITS  6
 382 #define MASKRANGE       ((1 << MASKRANGE_BITS) - 1)
 383
 384 /* data field addresses in the DDR2 SPD eeprom */
 385 enum ddr2_spd_addrs {
 386         DDR2_SPD_BYTES_PROGRAMMED       = 0,
 387         DDR2_SPD_TOTAL_BYTES            = 1,
 388         DDR2_SPD_MEM_TYPE               = 2,
 389         DDR2_SPD_NUM_ROW_BITS           = 3,
 390         DDR2_SPD_NUM_COL_BITS           = 4,
 391         DDR2_SPD_NUM_RANKS              = 5,
 392         DDR2_SPD_CYCLE_CLX              = 9,
 393         DDR2_SPD_CONFIG_TYPE            = 11,
 394         DDR2_SPD_REFRESH                = 12,
 395         DDR2_SPD_SDRAM_WIDTH            = 13,
 396         DDR2_SPD_BURST_LENGTH           = 16,
 397         DDR2_SPD_NUM_BANKS              = 17,
 398         DDR2_SPD_CAS_LATENCY            = 18,
 399         DDR2_SPD_DIMM_TYPE              = 20,
 400         DDR2_SPD_CYCLE_CLX1             = 23,
 401         DDR2_SPD_CYCLE_CLX2             = 25,
 402         DDR2_SPD_TRP                    = 27,
 403         DDR2_SPD_TRRD                   = 28,
 404         DDR2_SPD_TRCD                   = 29,
 405         DDR2_SPD_TRAS                   = 30,
 406         DDR2_SPD_TWR                    = 36,
 407         DDR2_SPD_TWTR                   = 37,
 408         DDR2_SPD_TRFC_EXT               = 40,
 409         DDR2_SPD_TRFC                   = 42,
 410         DDR2_SPD_CHECKSUM               = 63,
 411         DDR2_SPD_MFR_ID                 = 64
 412 };
 413
 414 /* data field addresses in the DDR2 SPD eeprom */
 415 enum ddr3_spd_addrs {
 416         DDR3_SPD_BYTES_PROGRAMMED                       =  0,
 417         DDR3_SPD_REVISION                               =  1,
 418         DDR3_SPD_KEY_BYTE_DEVICE_TYPE                   =  2,
 419         DDR3_SPD_KEY_BYTE_MODULE_TYPE                   =  3,
 420         DDR3_SPD_DENSITY_BANKS                          =  4,
 421         DDR3_SPD_ADDRESSING_ROW_COL_BITS                =  5,
 422         DDR3_SPD_NOMINAL_VOLTAGE                        =  6,
 423         DDR3_SPD_MODULE_ORGANIZATION                    =  7,
 424         DDR3_SPD_MEMORY_BUS_WIDTH                       =  8,
 425         DDR3_SPD_FINE_TIMEBASE_DIVIDEND_DIVISOR         =  9,
 426         DDR3_SPD_MEDIUM_TIMEBASE_DIVIDEND               = 10,
 427         DDR3_SPD_MEDIUM_TIMEBASE_DIVISOR                = 11,
 428         DDR3_SPD_MINIMUM_CYCLE_TIME_TCKMIN              = 12,
 429         DDR3_SPD_CAS_LATENCIES_LSB                      = 14,
 430         DDR3_SPD_CAS_LATENCIES_MSB                      = 15,
 431         DDR3_SPD_MIN_CAS_LATENCY_TAAMIN                 = 16,
 432         DDR3_SPD_MIN_WRITE_RECOVERY_TWRMIN              = 17,
 433         DDR3_SPD_MIN_RAS_CAS_DELAY_TRCDMIN              = 18,
 434         DDR3_SPD_MIN_ROW_ACTIVE_DELAY_TRRDMIN           = 19,
 435         DDR3_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN         = 20,
 436         DDR3_SPD_UPPER_NIBBLES_TRAS_TRC                 = 21,
 437         DDR3_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN       = 22,
 438         DDR3_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN          = 23,
 439         DDR3_SPD_MIN_REFRESH_RECOVERY_LSB_TRFCMIN       = 24,
 440         DDR3_SPD_MIN_REFRESH_RECOVERY_MSB_TRFCMIN       = 25,
 441         DDR3_SPD_MIN_INTERNAL_WRITE_READ_CMD_TWTRMIN    = 26,
 442         DDR3_SPD_MIN_INTERNAL_READ_PRECHARGE_CMD_TRTPMIN = 27,
 443         DDR3_SPD_UPPER_NIBBLE_TFAW                      = 28,
 444         DDR3_SPD_MIN_FOUR_ACTIVE_WINDOW_TFAWMIN         = 29,
 445         DDR3_SPD_SDRAM_OPTIONAL_FEATURES                = 30,
 446         DDR3_SPD_SDRAM_THERMAL_REFRESH_OPTIONS          = 31,
 447         DDR3_SPD_MODULE_THERMAL_SENSOR                  = 32,
 448         DDR3_SPD_SDRAM_DEVICE_TYPE                      = 33,
 449         DDR3_SPD_MINIMUM_CYCLE_TIME_FINE_TCKMIN         = 34,
 450         DDR3_SPD_MIN_CAS_LATENCY_FINE_TAAMIN            = 35,
 451         DDR3_SPD_MIN_RAS_CAS_DELAY_FINE_TRCDMIN         = 36,
 452         DDR3_SPD_MIN_ROW_PRECHARGE_DELAY_FINE_TRPMIN    = 37,
 453         DDR3_SPD_MIN_ACTIVE_REFRESH_LSB_FINE_TRCMIN     = 38,
 454         DDR3_SPD_REFERENCE_RAW_CARD                     = 62,
 455         DDR3_SPD_ADDRESS_MAPPING                        = 63,
 456         DDR3_SPD_REGISTER_MANUFACTURER_ID_LSB           = 65,
 457         DDR3_SPD_REGISTER_MANUFACTURER_ID_MSB           = 66,
 458         DDR3_SPD_REGISTER_REVISION_NUMBER               = 67,
 459         DDR3_SPD_MODULE_SERIAL_NUMBER                   = 122,
 460         DDR3_SPD_CYCLICAL_REDUNDANCY_CODE_LOWER_NIBBLE  = 126,
 461         DDR3_SPD_CYCLICAL_REDUNDANCY_CODE_UPPER_NIBBLE  = 127,
 462         DDR3_SPD_MODULE_PART_NUMBER                     = 128
 463 };
 464
 465 /* data field addresses in the DDR4 SPD eeprom */
 466 enum ddr4_spd_addrs {
 467         DDR4_SPD_BYTES_PROGRAMMED                       =  0,
 468         DDR4_SPD_REVISION                               =  1,
 469         DDR4_SPD_KEY_BYTE_DEVICE_TYPE                   =  2,
 470         DDR4_SPD_KEY_BYTE_MODULE_TYPE                   =  3,
 471         DDR4_SPD_DENSITY_BANKS                          =  4,
 472         DDR4_SPD_ADDRESSING_ROW_COL_BITS                =  5,
 473         DDR4_SPD_PACKAGE_TYPE                           =  6,
 474         DDR4_SPD_OPTIONAL_FEATURES                      =  7,
 475         DDR4_SPD_THERMAL_REFRESH_OPTIONS                =  8,
 476         DDR4_SPD_OTHER_OPTIONAL_FEATURES                =  9,
 477         DDR4_SPD_SECONDARY_PACKAGE_TYPE                 = 10,
 478         DDR4_SPD_MODULE_NOMINAL_VOLTAGE                 = 11,
 479         DDR4_SPD_MODULE_ORGANIZATION                    = 12,
 480         DDR4_SPD_MODULE_MEMORY_BUS_WIDTH                = 13,
 481         DDR4_SPD_MODULE_THERMAL_SENSOR                  = 14,
 482         DDR4_SPD_RESERVED_BYTE15                        = 15,
 483         DDR4_SPD_RESERVED_BYTE16                        = 16,
 484         DDR4_SPD_TIMEBASES                              = 17,
 485         DDR4_SPD_MINIMUM_CYCLE_TIME_TCKAVGMIN           = 18,
 486         DDR4_SPD_MAXIMUM_CYCLE_TIME_TCKAVGMAX           = 19,
 487         DDR4_SPD_CAS_LATENCIES_BYTE0                    = 20,
 488         DDR4_SPD_CAS_LATENCIES_BYTE1                    = 21,
 489         DDR4_SPD_CAS_LATENCIES_BYTE2                    = 22,
 490         DDR4_SPD_CAS_LATENCIES_BYTE3                    = 23,
 491         DDR4_SPD_MIN_CAS_LATENCY_TAAMIN                 = 24,
 492         DDR4_SPD_MIN_RAS_CAS_DELAY_TRCDMIN              = 25,
 493         DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN         = 26,
 494         DDR4_SPD_UPPER_NIBBLES_TRAS_TRC                 = 27,
 495         DDR4_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN       = 28,
 496         DDR4_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN          = 29,
 497         DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC1MIN      = 30,
 498         DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC1MIN      = 31,
 499         DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC2MIN      = 32,
 500         DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC2MIN      = 33,
 501         DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC4MIN      = 34,
 502         DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC4MIN      = 35,
 503         DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_MSN_TFAWMIN     = 36,
 504         DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_LSB_TFAWMIN     = 37,
 505         DDR4_SPD_MIN_ROW_ACTIVE_DELAY_SAME_TRRD_SMIN    = 38,
 506         DDR4_SPD_MIN_ROW_ACTIVE_DELAY_DIFF_TRRD_LMIN    = 39,
 507         DDR4_SPD_MIN_CAS_TO_CAS_DELAY_TCCD_LMIN         = 40,
 508         DDR4_SPD_MIN_CAS_TO_CAS_DELAY_FINE_TCCD_LMIN    = 117,
 509         DDR4_SPD_MIN_ACT_TO_ACT_DELAY_SAME_FINE_TRRD_LMIN = 118,
 510         DDR4_SPD_MIN_ACT_TO_ACT_DELAY_DIFF_FINE_TRRD_SMIN = 119,
 511         DDR4_SPD_MIN_ACT_TO_ACT_REFRESH_DELAY_FINE_TRCMIN = 120,
 512         DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_FINE_TRPMIN    = 121,
 513         DDR4_SPD_MIN_RAS_TO_CAS_DELAY_FINE_TRCDMIN      = 122,
 514         DDR4_SPD_MIN_CAS_LATENCY_FINE_TAAMIN            = 123,
 515         DDR4_SPD_MAX_CYCLE_TIME_FINE_TCKAVGMAX          = 124,
 516         DDR4_SPD_MIN_CYCLE_TIME_FINE_TCKAVGMIN          = 125,
 517         DDR4_SPD_CYCLICAL_REDUNDANCY_CODE_LOWER_NIBBLE  = 126,
 518         DDR4_SPD_CYCLICAL_REDUNDANCY_CODE_UPPER_NIBBLE  = 127,
 519         DDR4_SPD_REFERENCE_RAW_CARD                     = 130,
 520         DDR4_SPD_UDIMM_ADDR_MAPPING_FROM_EDGE           = 131,
 521         DDR4_SPD_REGISTER_MANUFACTURER_ID_LSB           = 133,
 522         DDR4_SPD_REGISTER_MANUFACTURER_ID_MSB           = 134,
 523         DDR4_SPD_REGISTER_REVISION_NUMBER               = 135,
 524         DDR4_SPD_RDIMM_ADDR_MAPPING_FROM_REGISTER_TO_DRAM = 136,
 525         DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CTL      = 137,
 526         DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CK       = 138,
 527 };
 528
 529 #define SPD_EEPROM_SIZE         (DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CK + 1)
 530
 531 struct impedence_values {
 532         unsigned char *rodt_ohms;
 533         unsigned char *rtt_nom_ohms;
 534         unsigned char *rtt_nom_table;
 535         unsigned char *rtt_wr_ohms;
 536         unsigned char *dic_ohms;
 537         short *drive_strength;
 538         short *dqx_strength;
 539 };
 540
 541 #define RODT_OHMS_COUNT        8
 542 #define RTT_NOM_OHMS_COUNT     8
 543 #define RTT_NOM_TABLE_COUNT    8
 544 #define RTT_WR_OHMS_COUNT      8
 545 #define DIC_OHMS_COUNT         3
 546 #define DRIVE_STRENGTH_COUNT  15
 547
 548 /*
 549  * Structure that provides DIMM information, either in the form of an SPD
 550  * TWSI address, or a pointer to an array that contains SPD data. One of
 551  * the two fields must be valid.
 552  */
 553 struct dimm_config {
 554         u16 spd_addrs[2]; /* TWSI address of SPD, 0 if not used */
 555         u8 *spd_ptrs[2]; /* pointer to SPD data array, NULL if not used */
 556         int spd_cached[2];
 557         u8 spd_data[2][SPD_EEPROM_SIZE];
 558 };
 559
 560 struct dimm_odt_config {
 561         u8 odt_ena;            /* FIX: dqx_ctl for Octeon 3 DDR4 */
 562         u64 odt_mask;          /* FIX: wodt_mask for Octeon 3 */
 563         union cvmx_lmcx_modereg_params1 modereg_params1;
 564         union cvmx_lmcx_modereg_params2 modereg_params2;
 565         u8 qs_dic;             /* FIX: rodt_ctl for Octeon 3 */
 566         u64 rodt_ctl;          /* FIX: rodt_mask for Octeon 3 */
 567         u8 dic;
 568 };
 569
 570 struct ddr_delay_config {
 571         u32 ddr_board_delay;
 572         u8 lmc_delay_clk;
 573         u8 lmc_delay_cmd;
 574         u8 lmc_delay_dq;
 575 };
 576
 577 /*
 578  * The parameters below make up the custom_lmc_config data structure.
 579  * This structure is used to customize the way that the LMC DRAM
 580  * Controller is configured for a particular board design.
 581  *
 582  * The HRM describes LMC Read Leveling which supports automatic
 583  * selection of per byte-lane delays.  When measuring the read delays
 584  * the LMC configuration software sweeps through a range of settings
 585  * for LMC0_COMP_CTL2[RODT_CTL], the Octeon II on-die-termination
 586  * resistance and LMC0_MODEREG_PARAMS1[RTT_NOM_XX], the DRAM
 587  * on-die-termination resistance.  The minimum and maximum parameters
 588  * for rtt_nom_idx and rodt_ctl listed below determine the ranges of
 589  * ODT settings used for the measurements.  Note that for rtt_nom an
 590  * index is used into a sorted table rather than the direct csr setting
 591  * in order to optimize the sweep.
 592  *
 593  * .min_rtt_nom_idx: 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms
 594  * .max_rtt_nom_idx: 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms
 595  * .min_rodt_ctl: 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms
 596  * .max_rodt_ctl: 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms
 597  *
 598  * The settings below control the Octeon II drive strength for the CK,
 599  * ADD/CMD, and DQ/DQS signals.  1=24ohms, 2=26.67ohms, 3=30ohms,
 600  * 4=34.3ohms, 5=40ohms, 6=48ohms, 6=60ohms.
 601  *
 602  * .dqx_ctl: Drive strength control for DDR_DQX/DDR_DQS_X_P/N drivers.
 603  * .ck_ctl: Drive strength control for
 604  * DDR_CK_X_P/DDR_DIMMX_CSX_L/DDR_DIMMX_ODT_X drivers.
 605  * .cmd_ctl: Drive strength control for CMD/A/RESET_L/CKEX drivers.
 606  *
 607  * The LMC controller software selects the most optimal CAS Latency
 608  * that complies with the appropriate SPD values and the frequency
 609  * that the DRAMS are being operated.  When operating the DRAMs at
 610  * frequencies substantially lower than their rated frequencies it
 611  * might be necessary to limit the minimum CAS Latency the LMC
 612  * controller software is allowed to select in order to make the DRAM
 613  * work reliably.
 614  *
 615  * .min_cas_latency: Minimum allowed CAS Latency
 616  *
 617  * The value used for LMC0_RLEVEL_CTL[OFFSET_EN] determine how the
 618  * read-leveling information that the Octeon II gathers is interpreted
 619  * to determine the per-byte read delays.
 620  *
 621  * .offset_en: Value used for LMC0_RLEVEL_CTL[OFFSET_EN].
 622  * .offset_udimm: Value used for LMC0_RLEVEL_CTL[OFFSET] for UDIMMS.
 623  * .offset_rdimm: Value used for LMC0_RLEVEL_CTL[OFFSET] for RDIMMS.
 624  *
 625  * The LMC configuration software sweeps through a range of ODT
 626  * settings while measuring the per-byte read delays.  During those
 627  * measurements the software makes an assessment of the quality of the
 628  * measurements in order to determine which measurements provide the
 629  * most accurate delays.  The automatic settings provide the option to
 630  * allow that same assessment to determine the most optimal RODT_CTL
 631  * and/or RTT_NOM settings.
 632  *
 633  * The automatic approach might provide the best means to determine
 634  * the settings used for initial poweron of a new design.  However,
 635  * the final settings should be determined by board analysis, testing,
 636  * and experience.
 637  *
 638  * .ddr_rtt_nom_auto: 1 means automatically set RTT_NOM value.
 639  * .ddr_rodt_ctl_auto: 1 means automatically set RODT_CTL value.
 640  *
 641  * .rlevel_compute: Enables software interpretation of per-byte read
 642  * delays using the measurements collected by the
 643  * Octeon II rather than completely relying on the
 644  * Octeon II to determine the delays.  1=software
 645  * computation is recomended since a more complete
 646  * analysis is implemented in software.
 647  *
 648  * .rlevel_comp_offset: Set to 2 unless instructed differently by Cavium.
 649  *
 650  * .rlevel_average_loops: Determines the number of times the read-leveling
 651  * sequence is run for each rank.  The results is
 652  * then averaged across the number of loops. The
 653  * default setting is 1.
 654  *
 655  * .ddr2t_udimm:
 656  * .ddr2t_rdimm: Turn on the DDR 2T mode. 2-cycle window for CMD and
 657  * address. This mode helps relieve setup time pressure
 658  * on the address and command bus. Please refer to
 659  * Micron's tech note tn_47_01 titled DDR2-533 Memory
 660  * Design Guide for Two Dimm Unbuffered Systems for
 661  * physical details.
 662  *
 663  * .disable_sequential_delay_check: As result of the flyby topology
 664  * prescribed in the JEDEC specifications the byte delays should
 665  * maintain a consistent increasing or decreasing trend across
 666  * the bytes on standard dimms.  This setting can be used disable
 667  * that check for unusual circumstances where the check is not
 668  * useful.
 669  *
 670  * .maximum_adjacent_rlevel_delay_increment: An additional sequential
 671  * delay check for the delays that result from the flyby
 672  * topology. This value specifies the maximum difference between
 673  * the delays of adjacent bytes.  A value of 0 disables this
 674  * check.
 675  *
 676  * .fprch2 Front Porch Enable: When set, the turn-off
 677  * time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
 678  * 00 = 0 CKs
 679  * 01 = 1 CKs
 680  * 10 = 2 CKs
 681  *
 682  * .parity: The parity input signal PAR_IN on each dimm must be
 683  * strapped high or low on the board.  This bit is programmed
 684  * into LMC0_DIMM_CTL[PARITY] and it must be set to match the
 685  * board strapping.  This signal is typically strapped low.
 686  *
 687  * .mode32b: Enable 32-bit datapath mode.  Set to 1 if only 32 DQ pins
 688  * are used. (cn61xx, cn71xx)
 689  *
 690  * .measured_vref: Set to 1 to measure VREF; set to 0 to compute VREF.
 691  *
 692  * .dram_connection: Set to 1 if discrete DRAMs; set to 0 if using DIMMs.
 693  * This changes the algorithms used to compute VREF.
 694  *
 695  * .dll_write_offset: FIXME: Add description
 696  * .dll_read_offset:  FIXME: Add description
 697  */
 698
 699 struct rlevel_table {
 700         const char part[20];
 701         int speed;
 702         u64 rl_rank[4][4];
 703 };
 704
 705 struct ddr3_custom_config {
 706         u8 min_rtt_nom_idx;
 707         u8 max_rtt_nom_idx;
 708         u8 min_rodt_ctl;
 709         u8 max_rodt_ctl;
 710         u8 dqx_ctl;
 711         u8 ck_ctl;
 712         u8 cmd_ctl;
 713         u8 ctl_ctl;
 714         u8 min_cas_latency;
 715         u8 offset_en;
 716         u8 offset_udimm;
 717         u8 offset_rdimm;
 718         u8 rlevel_compute;
 719         u8 ddr_rtt_nom_auto;
 720         u8 ddr_rodt_ctl_auto;
 721         u8 rlevel_comp_offset_udimm;
 722         u8 rlevel_comp_offset_rdimm;
 723         int8_t ptune_offset;
 724         int8_t ntune_offset;
 725         u8 rlevel_average_loops;
 726         u8 ddr2t_udimm;
 727         u8 ddr2t_rdimm;
 728         u8 disable_sequential_delay_check;
 729         u8 maximum_adjacent_rlevel_delay_increment;
 730         u8 parity;
 731         u8 fprch2;
 732         u8 mode32b;
 733         u8 measured_vref;
 734         u8 dram_connection;
 735         const int8_t *dll_write_offset;
 736         const int8_t *dll_read_offset;
 737         struct rlevel_table *rl_tbl;
 738 };
 739
 740 #define DDR_CFG_T_MAX_DIMMS     5
 741
 742 struct ddr_conf {
 743         struct dimm_config dimm_config_table[DDR_CFG_T_MAX_DIMMS];
 744         struct dimm_odt_config odt_1rank_config[4];
 745         struct dimm_odt_config odt_2rank_config[4];
 746         struct dimm_odt_config odt_4rank_config[4];
 747         struct ddr_delay_config unbuffered;
 748         struct ddr_delay_config registered;
 749         struct ddr3_custom_config custom_lmc_config;
 750 };
 751
 752 /* Divide and round results to the nearest integer. */
 753 static inline u64 divide_nint(u64 dividend, u64 divisor)
 754 {
 755         u64 quotent, remainder;
 756
 757         quotent   = dividend / divisor;
 758         remainder = dividend % divisor;
 759         return (quotent + ((remainder * 2) >= divisor));
 760 }
 761
 762 /* Divide and round results up to the next higher integer. */
 763 static inline u64 divide_roundup(u64 dividend, u64 divisor)
 764 {
 765         return ((dividend + divisor - 1) / divisor);
 766 }
 767
 768 enum ddr_type {
 769         DDR3_DRAM = 3,
 770         DDR4_DRAM = 4,
 771 };
 772
 773 #define rttnom_none   0         /* Rtt_Nom disabled */
 774 #define rttnom_60ohm  1         /* RZQ/4  = 240/4  =  60 ohms */
 775 #define rttnom_120ohm 2         /* RZQ/2  = 240/2  = 120 ohms */
 776 #define rttnom_40ohm  3         /* RZQ/6  = 240/6  =  40 ohms */
 777 #define rttnom_20ohm  4         /* RZQ/12 = 240/12 =  20 ohms */
 778 #define rttnom_30ohm  5         /* RZQ/8  = 240/8  =  30 ohms */
 779 #define rttnom_rsrv1  6         /* Reserved */
 780 #define rttnom_rsrv2  7         /* Reserved */
 781
 782 #define rttwr_none    0         /* Dynamic ODT off */
 783 #define rttwr_60ohm   1         /* RZQ/4  = 240/4  =  60 ohms */
 784 #define rttwr_120ohm  2         /* RZQ/2  = 240/2  = 120 ohms */
 785 #define rttwr_rsrv1   3         /* Reserved */
 786
 787 #define dic_40ohm     0         /* RZQ/6  = 240/6  =  40 ohms */
 788 #define dic_34ohm     1         /* RZQ/7  = 240/7  =  34 ohms */
 789
 790 #define driver_24_ohm   1
 791 #define driver_27_ohm   2
 792 #define driver_30_ohm   3
 793 #define driver_34_ohm   4
 794 #define driver_40_ohm   5
 795 #define driver_48_ohm   6
 796 #define driver_60_ohm   7
 797
 798 #define rodt_ctl_none     0
 799 #define rodt_ctl_20_ohm   1
 800 #define rodt_ctl_30_ohm   2
 801 #define rodt_ctl_40_ohm   3
 802 #define rodt_ctl_60_ohm   4
 803 #define rodt_ctl_120_ohm  5
 804
 805 #define ddr4_rttnom_none   0         /* Rtt_Nom disabled */
 806 #define ddr4_rttnom_60ohm  1         /* RZQ/4  = 240/4  =  60 ohms */
 807 #define ddr4_rttnom_120ohm 2         /* RZQ/2  = 240/2  = 120 ohms */
 808 #define ddr4_rttnom_40ohm  3         /* RZQ/6  = 240/6  =  40 ohms */
 809 #define ddr4_rttnom_240ohm 4         /* RZQ/1  = 240/1  = 240 ohms */
 810 #define ddr4_rttnom_48ohm  5         /* RZQ/5  = 240/5  =  48 ohms */
 811 #define ddr4_rttnom_80ohm  6         /* RZQ/3  = 240/3  =  80 ohms */
 812 #define ddr4_rttnom_34ohm  7         /* RZQ/7  = 240/7  =  34 ohms */
 813
 814 #define ddr4_rttwr_none    0         /* Dynamic ODT off */
 815 #define ddr4_rttwr_120ohm  1         /* RZQ/2  = 240/2  = 120 ohms */
 816 #define ddr4_rttwr_240ohm  2         /* RZQ/1  = 240/1  = 240 ohms */
 817 #define ddr4_rttwr_hiz     3         /* HiZ */
 818 /* This setting is available for cn78xx pass 2, and cn73xx & cnf75xx pass 1 */
 819 #define ddr4_rttwr_80ohm   4         /* RZQ/3  = 240/3  =  80 ohms */
 820
 821 #define ddr4_dic_34ohm     0         /* RZQ/7  = 240/7  =  34 ohms */
 822 #define ddr4_dic_48ohm     1         /* RZQ/5  = 240/5  =  48 ohms */
 823
 824 #define ddr4_rttpark_none   0         /* Rtt_Park disabled */
 825 #define ddr4_rttpark_60ohm  1         /* RZQ/4  = 240/4  =  60 ohms */
 826 #define ddr4_rttpark_120ohm 2         /* RZQ/2  = 240/2  = 120 ohms */
 827 #define ddr4_rttpark_40ohm  3         /* RZQ/6  = 240/6  =  40 ohms */
 828 #define ddr4_rttpark_240ohm 4         /* RZQ/1  = 240/1  = 240 ohms */
 829 #define ddr4_rttpark_48ohm  5         /* RZQ/5  = 240/5  =  48 ohms */
 830 #define ddr4_rttpark_80ohm  6         /* RZQ/3  = 240/3  =  80 ohms */
 831 #define ddr4_rttpark_34ohm  7         /* RZQ/7  = 240/7  =  34 ohms */
 832
 833 #define ddr4_driver_26_ohm   2
 834 #define ddr4_driver_30_ohm   3
 835 #define ddr4_driver_34_ohm   4
 836 #define ddr4_driver_40_ohm   5
 837 #define ddr4_driver_48_ohm   6
 838
 839 #define ddr4_dqx_driver_24_ohm   1
 840 #define ddr4_dqx_driver_27_ohm   2
 841 #define ddr4_dqx_driver_30_ohm   3
 842 #define ddr4_dqx_driver_34_ohm   4
 843 #define ddr4_dqx_driver_40_ohm   5
 844 #define ddr4_dqx_driver_48_ohm   6
 845 #define ddr4_dqx_driver_60_ohm   7
 846
 847 #define ddr4_rodt_ctl_none     0
 848 #define ddr4_rodt_ctl_40_ohm   1
 849 #define ddr4_rodt_ctl_60_ohm   2
 850 #define ddr4_rodt_ctl_80_ohm   3
 851 #define ddr4_rodt_ctl_120_ohm  4
 852 #define ddr4_rodt_ctl_240_ohm  5
 853 #define ddr4_rodt_ctl_34_ohm   6
 854 #define ddr4_rodt_ctl_48_ohm   7
 855
 856 #define DIMM_CONFIG_TERMINATOR  { {0, 0}, {NULL, NULL} }
 857
 858 #define SET_DDR_DLL_CTL3(field, expr)                           \
 859         do {                                                    \
 860                 if (octeon_is_cpuid(OCTEON_CN66XX) ||           \
 861                     octeon_is_cpuid(OCTEON_CN63XX))             \
 862                         ddr_dll_ctl3.cn63xx.field = (expr);     \
 863                 else if (octeon_is_cpuid(OCTEON_CN68XX) ||      \
 864                          octeon_is_cpuid(OCTEON_CN61XX) ||      \
 865                          octeon_is_cpuid(OCTEON_CNF71XX))       \
 866                         ddr_dll_ctl3.cn61xx.field = (expr);     \
 867                 else if (octeon_is_cpuid(OCTEON_CN70XX) ||      \
 868                          octeon_is_cpuid(OCTEON_CN78XX))        \
 869                         ddr_dll_ctl3.cn70xx.field = (expr);     \
 870                 else if (octeon_is_cpuid(OCTEON_CN73XX) ||      \
 871                          octeon_is_cpuid(OCTEON_CNF75XX))       \
 872                         ddr_dll_ctl3.cn73xx.field = (expr);     \
 873                 else                                            \
 874                         debug("%s(): " #field                   \
 875                               "not set for unknown chip\n",     \
 876                               __func__);                        \
 877         } while (0)
 878
 879 #define ENCODE_DLL90_BYTE_SEL(byte_sel)                                 \
 880         (octeon_is_cpuid(OCTEON_CN70XX) ? ((9 + 7 - (byte_sel)) % 9) :  \
 881          ((byte_sel) + 1))
 882
 883 /**
 884  * If debugging is disabled the ddr_print macro is not compatible
 885  * with this macro.
 886  */
 887 # define GET_DDR_DLL_CTL3(field)                \
 888         ((octeon_is_cpuid(OCTEON_CN66XX) ||     \
 889           octeon_is_cpuid(OCTEON_CN63XX)) ?     \
 890          ddr_dll_ctl3.cn63xx.field :            \
 891          (octeon_is_cpuid(OCTEON_CN68XX) ||     \
 892           octeon_is_cpuid(OCTEON_CN61XX) ||     \
 893           octeon_is_cpuid(OCTEON_CNF71XX)) ?    \
 894          ddr_dll_ctl3.cn61xx.field :            \
 895          (octeon_is_cpuid(OCTEON_CN70XX) ||     \
 896           octeon_is_cpuid(OCTEON_CN78XX)) ?     \
 897          ddr_dll_ctl3.cn70xx.field :            \
 898          (octeon_is_cpuid(OCTEON_CN73XX) ||     \
 899           octeon_is_cpuid(OCTEON_CNF75XX)) ?    \
 900          ddr_dll_ctl3.cn73xx.field : 0)
 901
 902 extern const char *ddr3_dimm_types[];
 903 extern const char *ddr4_dimm_types[];
 904
 905 extern const struct dimm_odt_config disable_odt_config[];
 906
 907 #define RLEVEL_BYTE_BITS        6
 908 #define RLEVEL_BYTE_MSK         ((1ULL << 6) - 1)
 909
 910 /* Prototypes */
 911 int get_ddr_type(struct dimm_config *dimm_config, int upper_dimm);
 912 int get_dimm_module_type(struct dimm_config *dimm_config, int upper_dimm,
 913                          int ddr_type);
 914 int read_spd(struct dimm_config *dimm_config, int dimm_index, int spd_field);
 915 int read_spd_init(struct dimm_config *dimm_config, int dimm_index);
 916 void report_dimm(struct dimm_config *dimm_config, int upper_dimm,
 917                  int dimm, int if_num);
 918 int validate_dimm(struct ddr_priv *priv, struct dimm_config *dimm_config,
 919                   int dimm_index);
 920 char *printable_rank_spec(char *buffer, int num_ranks, int dram_width,
 921                           int spd_package);
 922
 923 bool ddr_memory_preserved(struct ddr_priv *priv);
 924
 925 int get_wl_rank(union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, int byte);
 926 int get_rl_rank(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank, int byte);
 927 void upd_wl_rank(union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, int byte,
 928                  int delay);
 929 void upd_rl_rank(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank, int byte,
 930                  int delay);
 931
 932 int compute_ddr3_rlevel_delay(u8 mstart, u8 width,
 933                               union cvmx_lmcx_rlevel_ctl rlevel_ctl);
 934
 935 int encode_row_lsb_ddr3(int row_lsb);
 936 int encode_pbank_lsb_ddr3(int pbank_lsb);
 937
 938 int initialize_ddr_clock(struct ddr_priv *priv, struct ddr_conf *ddr_conf,
 939                          u32 cpu_hertz, u32 ddr_hertz, u32 ddr_ref_hertz,
 940                          int if_num, u32 if_mask);
 941
 942 void process_custom_dll_offsets(struct ddr_priv *priv, int if_num,
 943                                 const char *enable_str,
 944                                 const int8_t *offsets, const char *byte_str,
 945                                 int mode);
 946 int nonseq_del(struct rlevel_byte_data *rlevel_byte, int start, int end,
 947                int max_adj_delay_inc);
 948 int roundup_ddr3_wlevel_bitmask(int bitmask);
 949
 950 void oct3_ddr3_seq(struct ddr_priv *priv, int rank_mask, int if_num,
 951                    int sequence);
 952 void ddr_init_seq(struct ddr_priv *priv, int rank_mask, int if_num);
 953
 954 void rlevel_to_wlevel(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank,
 955                       union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, int byte);
 956
 957 int validate_ddr3_rlevel_bitmask(struct rlevel_bitmask *rlevel_bitmask_p,
 958                                  int ddr_type);
 959
 960 void change_dll_offset_enable(struct ddr_priv *priv, int if_num, int change);
 961 unsigned short load_dll_offset(struct ddr_priv *priv, int if_num,
 962                                int dll_offset_mode,
 963                                int byte_offset, int byte);
 964
 965 u64 lmc_ddr3_rl_dbg_read(struct ddr_priv *priv, int if_num, int idx);
 966 u64 lmc_ddr3_wl_dbg_read(struct ddr_priv *priv, int if_num, int idx);
 967
 968 void cvmx_maybe_tune_node(struct ddr_priv *priv, u32 ddr_speed);
 969 void cvmx_dbi_switchover(struct ddr_priv *priv);
 970
 971 int init_octeon3_ddr3_interface(struct ddr_priv *priv,
 972                                 struct ddr_conf *ddr_conf,
 973                                 u32 ddr_hertz, u32 cpu_hertz, u32 ddr_ref_hertz,
 974                                 int if_num, u32 if_mask);
 975
 976 char *lookup_env(struct ddr_priv *priv, const char *format, ...);
 977 char *lookup_env_ull(struct ddr_priv *priv, const char *format, ...);
 978
 979 /* Each board provides a board-specific config table via this function */
 980 struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq);
 981
 982 #endif /* __OCTEON_DDR_H_ */