1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
6 #ifndef __CVMX_REGS_H__
7 #define __CVMX_REGS_H__
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
14 #define CVMX_MAX_CORES 48
15 /* Maximum # of bits to define core in node */
16 #define CVMX_NODE_NO_SHIFT 7
17 #define CVMX_NODE_BITS 2 /* Number of bits to define a node */
18 #define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
19 #define CVMX_NODE_MASK (CVMX_MAX_NODES - 1)
20 #define CVMX_NODE_IO_SHIFT 36
21 #define CVMX_NODE_MEM_SHIFT 40
22 #define CVMX_NODE_IO_MASK ((u64)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
24 #define CVMX_MIPS_MAX_CORE_BITS 10 /* Maximum # of bits to define cores */
25 #define CVMX_MIPS_MAX_CORES (1 << CVMX_MIPS_MAX_CORE_BITS)
27 #define MAX_CORE_TADS 8
29 #define CAST_ULL(v) ((unsigned long long)(v))
30 #define CASTPTR(type, v) ((type *)(long)(v))
33 #define CVMX_CIU_PP_RST 0x0001010000000100ULL
34 #define CVMX_CIU3_NMI 0x0001010000000160ULL
35 #define CVMX_CIU_FUSE 0x00010100000001a0ULL
36 #define CVMX_CIU_NMI 0x0001070000000718ULL
38 #define CVMX_MIO_BOOT_LOC_CFGX(x) (0x0001180000000080ULL + ((x) & 1) * 8)
39 #define MIO_BOOT_LOC_CFG_BASE GENMASK_ULL(27, 3)
40 #define MIO_BOOT_LOC_CFG_EN BIT_ULL(31)
42 #define CVMX_MIO_BOOT_LOC_ADR 0x0001180000000090ULL
43 #define MIO_BOOT_LOC_ADR_ADR GENMASK_ULL(7, 3)
45 #define CVMX_MIO_BOOT_LOC_DAT 0x0001180000000098ULL
47 #define CVMX_MIO_FUS_DAT2 0x0001180000001410ULL
48 #define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
49 #define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
50 #define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
52 #define CVMX_MIO_FUS_RCMD 0x0001180000001500ULL
53 #define MIO_FUS_RCMD_ADDR GENMASK_ULL(7, 0)
54 #define MIO_FUS_RCMD_PEND BIT_ULL(12)
55 #define MIO_FUS_RCMD_DAT GENMASK_ULL(23, 16)
57 #define CVMX_RNM_CTL_STATUS 0x0001180040000000ULL
58 #define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
60 /* turn the variable name into a string */
61 #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
62 #define CVMX_TMP_STR2(x) #x
64 #define CVMX_RDHWRNV(result, regstr) \
65 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
68 asm volatile ("syncw\nsyncw\n" : : : "memory")
70 /* ToDo: Currently only node = 0 supported */
71 static inline u64 csr_rd_node(int node, u64 addr)
75 base = ioremap_nocache(addr, 0x100);
76 return ioread64(base);
79 static inline u64 csr_rd(u64 addr)
81 return csr_rd_node(0, addr);
84 static inline void csr_wr_node(int node, u64 addr, u64 val)
88 base = ioremap_nocache(addr, 0x100);
92 static inline void csr_wr(u64 addr, u64 val)
94 csr_wr_node(0, addr, val);
98 * We need to use the volatile access here, otherwise the IO accessor
99 * functions might swap the bytes
101 static inline u64 cvmx_read64_uint64(u64 addr)
103 return *(volatile u64 *)addr;
106 static inline void cvmx_write64_uint64(u64 addr, u64 val)
108 *(volatile u64 *)addr = val;
111 static inline u32 cvmx_read64_uint32(u64 addr)
113 return *(volatile u32 *)addr;
116 static inline void cvmx_write64_uint32(u64 addr, u32 val)
118 *(volatile u32 *)addr = val;
121 static inline void *cvmx_phys_to_ptr(u64 addr)
123 return (void *)CKSEG0ADDR(addr);
126 static inline u64 cvmx_ptr_to_phys(void *ptr)
128 return virt_to_phys(ptr);
132 * Number of the Core on which the program is currently running.
134 * @return core number
136 static inline unsigned int cvmx_get_core_num(void)
138 unsigned int core_num;
140 CVMX_RDHWRNV(core_num, 0);
144 #endif /* __CVMX_REGS_H__ */