1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020 Marvell International Ltd.
6 #ifndef __CVMX_PKO3_QUEUE_H__
7 #define __CVMX_PKO3_QUEUE_H__
9 enum cvmx_pko3_level_e;
14 * Find or allocate global port/dq map table
15 * which is a named table, contains entries for
16 * all possible OCI nodes.
18 * The table global pointer is stored in core-local variable
19 * so that every core will call this function once, on first use.
21 int __cvmx_pko3_dq_table_setup(void);
24 * Get the base Descriptor Queue number for an IPD port on the local node
26 int cvmx_pko3_get_queue_base(int ipd_port);
29 * Get the number of Descriptor Queues assigned for an IPD port
31 int cvmx_pko3_get_queue_num(int ipd_port);
34 * Get L1/Port Queue number assigned to interface port.
36 * @param xiface is interface number.
37 * @param index is port index.
39 int cvmx_pko3_get_port_queue(int xiface, int index);
42 * Configure L3 through L5 Scheduler Queues and Descriptor Queues
44 * The Scheduler Queues in Levels 3 to 5 and Descriptor Queues are
45 * configured one-to-one or many-to-one to a single parent Scheduler
46 * Queues. The level of the parent SQ is specified in an argument,
47 * as well as the number of children to attach to the specific parent.
48 * The children can have fair round-robin or priority-based scheduling
49 * when multiple children are assigned a single parent.
51 * @param node on which to operate
52 * @param child_level is the level of the child queue
53 * @param parent_queue is the number of the parent Scheduler Queue
54 * @param child_base is the number of the first child SQ or DQ to assign to
55 * @param child_count is the number of consecutive children to assign
56 * @param stat_prio_count is the priority setting for the children L2 SQs
58 * If <stat_prio_count> is -1, the Ln children will have equal Round-Robin
59 * relationship with eachother. If <stat_prio_count> is 0, all Ln children
60 * will be arranged in Weighted-Round-Robin, with the first having the most
61 * precedence. If <stat_prio_count> is between 1 and 8, it indicates how
62 * many children will have static priority settings (with the first having
63 * the most precedence), with the remaining Ln children having WRR scheduling.
65 * @returns 0 on success, -1 on failure.
67 * Note: this function supports the configuration of node-local unit.
69 int cvmx_pko3_sq_config_children(unsigned int node,
70 enum cvmx_pko3_level_e child_level,
71 unsigned int parent_queue,
72 unsigned int child_base,
73 unsigned int child_count, int stat_prio_count);
77 * Register a range of Descriptor Queues wth an interface port
79 * This function poulates the DQ-to-IPD translation table
80 * used by the application to retrieve the DQ range (typically ordered
81 * by priority) for a given IPD-port, which is either a physical port,
82 * or a channel on a channelized interface (i.e. ILK).
84 * @param xiface is the physical interface number
85 * @param index is either a physical port on an interface
86 * @param or a channel of an ILK interface
87 * @param dq_base is the first Descriptor Queue number in a consecutive range
88 * @param dq_count is the number of consecutive Descriptor Queues leading
89 * @param the same channel or port.
91 * Only a consecurive range of Descriptor Queues can be associated with any
92 * given channel/port, and usually they are ordered from most to least
93 * in terms of scheduling priority.
95 * Note: thus function only populates the node-local translation table.
97 * @returns 0 on success, -1 on failure.
99 int __cvmx_pko3_ipd_dq_register(int xiface, int index, unsigned int dq_base, unsigned int dq_count);
104 * Unregister DQs associated with CHAN_E (IPD port)
106 int __cvmx_pko3_ipd_dq_unregister(int xiface, int index);
109 * Map channel number in PKO
111 * @param node is to specify the node to which this configuration is applied.
112 * @param pq_num specifies the Port Queue (i.e. L1) queue number.
113 * @param l2_l3_q_num specifies L2/L3 queue number.
114 * @param channel specifies the channel number to map to the queue.
116 * The channel assignment applies to L2 or L3 Shaper Queues depending
117 * on the setting of channel credit level.
119 * Return: returns none.
121 void cvmx_pko3_map_channel(unsigned int node, unsigned int pq_num, unsigned int l2_l3_q_num,
124 int cvmx_pko3_pq_config(unsigned int node, unsigned int mac_num, unsigned int pq_num);
126 int cvmx_pko3_port_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
127 unsigned int burst_bytes, int adj_bytes);
128 int cvmx_pko3_dq_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
129 unsigned int burst_bytes);
130 int cvmx_pko3_dq_pir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
131 unsigned int burst_bytes);
133 CVMX_PKO3_SHAPE_RED_STALL,
134 CVMX_PKO3_SHAPE_RED_DISCARD,
135 CVMX_PKO3_SHAPE_RED_PASS
138 void cvmx_pko3_dq_red(unsigned int node, unsigned int dq_num, red_action_t red_act,
142 * Macros to deal with short floating point numbers,
143 * where unsigned exponent, and an unsigned normalized
144 * mantissa are represented each with a defined field width.
147 #define CVMX_SHOFT_MANT_BITS 8
148 #define CVMX_SHOFT_EXP_BITS 4
151 * Convert short-float to an unsigned integer
152 * Note that it will lose precision.
154 #define CVMX_SHOFT_TO_U64(m, e) \
155 ((((1ull << CVMX_SHOFT_MANT_BITS) | (m)) << (e)) >> CVMX_SHOFT_MANT_BITS)
158 * Convert to short-float from an unsigned integer
160 #define CVMX_SHOFT_FROM_U64(ui, m, e) \
162 unsigned long long u; \
164 k = (1ull << (CVMX_SHOFT_MANT_BITS + 1)) - 1; \
166 u = (ui) << CVMX_SHOFT_MANT_BITS; \
171 (m) = u & (k >> 1); \
174 #define CVMX_SHOFT_MAX() \
175 CVMX_SHOFT_TO_U64((1 << CVMX_SHOFT_MANT_BITS) - 1, (1 << CVMX_SHOFT_EXP_BITS) - 1)
176 #define CVMX_SHOFT_MIN() CVMX_SHOFT_TO_U64(0, 0)
178 #endif /* __CVMX_PKO3_QUEUE_H__ */