1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020 Marvell International Ltd.
5 * Configuration and status register (CSR) type definitions for
9 #ifndef __CVMX_ASXX_DEFS_H__
10 #define __CVMX_ASXX_DEFS_H__
12 #define CVMX_ASXX_GMII_RX_CLK_SET(offset) (0x00011800B0000180ull)
13 #define CVMX_ASXX_GMII_RX_DAT_SET(offset) (0x00011800B0000188ull)
14 #define CVMX_ASXX_INT_EN(offset) (0x00011800B0000018ull + ((offset) & 1) * 0x8000000ull)
15 #define CVMX_ASXX_INT_REG(offset) (0x00011800B0000010ull + ((offset) & 1) * 0x8000000ull)
16 #define CVMX_ASXX_MII_RX_DAT_SET(offset) (0x00011800B0000190ull)
17 #define CVMX_ASXX_PRT_LOOP(offset) (0x00011800B0000040ull + ((offset) & 1) * 0x8000000ull)
18 #define CVMX_ASXX_RLD_BYPASS(offset) (0x00011800B0000248ull + ((offset) & 1) * 0x8000000ull)
19 #define CVMX_ASXX_RLD_BYPASS_SETTING(offset) (0x00011800B0000250ull + ((offset) & 1) * 0x8000000ull)
20 #define CVMX_ASXX_RLD_COMP(offset) (0x00011800B0000220ull + ((offset) & 1) * 0x8000000ull)
21 #define CVMX_ASXX_RLD_DATA_DRV(offset) (0x00011800B0000218ull + ((offset) & 1) * 0x8000000ull)
22 #define CVMX_ASXX_RLD_FCRAM_MODE(offset) (0x00011800B0000210ull + ((offset) & 1) * 0x8000000ull)
23 #define CVMX_ASXX_RLD_NCTL_STRONG(offset) (0x00011800B0000230ull + ((offset) & 1) * 0x8000000ull)
24 #define CVMX_ASXX_RLD_NCTL_WEAK(offset) (0x00011800B0000240ull + ((offset) & 1) * 0x8000000ull)
25 #define CVMX_ASXX_RLD_PCTL_STRONG(offset) (0x00011800B0000228ull + ((offset) & 1) * 0x8000000ull)
26 #define CVMX_ASXX_RLD_PCTL_WEAK(offset) (0x00011800B0000238ull + ((offset) & 1) * 0x8000000ull)
27 #define CVMX_ASXX_RLD_SETTING(offset) (0x00011800B0000258ull + ((offset) & 1) * 0x8000000ull)
28 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
29 (0x00011800B0000020ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
30 #define CVMX_ASXX_RX_PRT_EN(offset) (0x00011800B0000000ull + ((offset) & 1) * 0x8000000ull)
31 #define CVMX_ASXX_RX_WOL(offset) (0x00011800B0000100ull + ((offset) & 1) * 0x8000000ull)
32 #define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B0000108ull + ((offset) & 1) * 0x8000000ull)
33 #define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B0000118ull + ((offset) & 1) * 0x8000000ull)
34 #define CVMX_ASXX_RX_WOL_SIG(offset) (0x00011800B0000110ull + ((offset) & 1) * 0x8000000ull)
35 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
36 (0x00011800B0000048ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
37 #define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B0000068ull + ((offset) & 1) * 0x8000000ull)
38 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
39 (0x00011800B0000080ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
40 #define CVMX_ASXX_TX_PRT_EN(offset) (0x00011800B0000008ull + ((offset) & 1) * 0x8000000ull)
43 * cvmx_asx#_gmii_rx_clk_set
45 * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
48 union cvmx_asxx_gmii_rx_clk_set {
50 struct cvmx_asxx_gmii_rx_clk_set_s {
51 u64 reserved_5_63 : 59;
54 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
55 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
56 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
59 typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
62 * cvmx_asx#_gmii_rx_dat_set
64 * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
67 union cvmx_asxx_gmii_rx_dat_set {
69 struct cvmx_asxx_gmii_rx_dat_set_s {
70 u64 reserved_5_63 : 59;
73 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
74 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
75 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
78 typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
83 * ASX_INT_EN = Interrupt Enable
86 union cvmx_asxx_int_en {
88 struct cvmx_asxx_int_en_s {
89 u64 reserved_12_63 : 52;
94 struct cvmx_asxx_int_en_cn30xx {
95 u64 reserved_11_63 : 53;
102 struct cvmx_asxx_int_en_cn30xx cn31xx;
103 struct cvmx_asxx_int_en_s cn38xx;
104 struct cvmx_asxx_int_en_s cn38xxp2;
105 struct cvmx_asxx_int_en_cn30xx cn50xx;
106 struct cvmx_asxx_int_en_s cn58xx;
107 struct cvmx_asxx_int_en_s cn58xxp1;
110 typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
115 * ASX_INT_REG = Interrupt Register
118 union cvmx_asxx_int_reg {
120 struct cvmx_asxx_int_reg_s {
121 u64 reserved_12_63 : 52;
126 struct cvmx_asxx_int_reg_cn30xx {
127 u64 reserved_11_63 : 53;
129 u64 reserved_7_7 : 1;
131 u64 reserved_3_3 : 1;
134 struct cvmx_asxx_int_reg_cn30xx cn31xx;
135 struct cvmx_asxx_int_reg_s cn38xx;
136 struct cvmx_asxx_int_reg_s cn38xxp2;
137 struct cvmx_asxx_int_reg_cn30xx cn50xx;
138 struct cvmx_asxx_int_reg_s cn58xx;
139 struct cvmx_asxx_int_reg_s cn58xxp1;
142 typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
145 * cvmx_asx#_mii_rx_dat_set
147 * ASX_MII_RX_DAT_SET = GMII Clock delay setting
150 union cvmx_asxx_mii_rx_dat_set {
152 struct cvmx_asxx_mii_rx_dat_set_s {
153 u64 reserved_5_63 : 59;
156 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
157 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
160 typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
165 * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
168 union cvmx_asxx_prt_loop {
170 struct cvmx_asxx_prt_loop_s {
171 u64 reserved_8_63 : 56;
175 struct cvmx_asxx_prt_loop_cn30xx {
176 u64 reserved_7_63 : 57;
178 u64 reserved_3_3 : 1;
181 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
182 struct cvmx_asxx_prt_loop_s cn38xx;
183 struct cvmx_asxx_prt_loop_s cn38xxp2;
184 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
185 struct cvmx_asxx_prt_loop_s cn58xx;
186 struct cvmx_asxx_prt_loop_s cn58xxp1;
189 typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
192 * cvmx_asx#_rld_bypass
197 union cvmx_asxx_rld_bypass {
199 struct cvmx_asxx_rld_bypass_s {
200 u64 reserved_1_63 : 63;
203 struct cvmx_asxx_rld_bypass_s cn38xx;
204 struct cvmx_asxx_rld_bypass_s cn38xxp2;
205 struct cvmx_asxx_rld_bypass_s cn58xx;
206 struct cvmx_asxx_rld_bypass_s cn58xxp1;
209 typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
212 * cvmx_asx#_rld_bypass_setting
214 * ASX_RLD_BYPASS_SETTING
217 union cvmx_asxx_rld_bypass_setting {
219 struct cvmx_asxx_rld_bypass_setting_s {
220 u64 reserved_5_63 : 59;
223 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
224 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
225 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
226 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
229 typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
237 union cvmx_asxx_rld_comp {
239 struct cvmx_asxx_rld_comp_s {
240 u64 reserved_9_63 : 55;
244 struct cvmx_asxx_rld_comp_cn38xx {
245 u64 reserved_8_63 : 56;
249 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
250 struct cvmx_asxx_rld_comp_s cn58xx;
251 struct cvmx_asxx_rld_comp_s cn58xxp1;
254 typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
257 * cvmx_asx#_rld_data_drv
262 union cvmx_asxx_rld_data_drv {
264 struct cvmx_asxx_rld_data_drv_s {
265 u64 reserved_8_63 : 56;
269 struct cvmx_asxx_rld_data_drv_s cn38xx;
270 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
271 struct cvmx_asxx_rld_data_drv_s cn58xx;
272 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
275 typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
278 * cvmx_asx#_rld_fcram_mode
283 union cvmx_asxx_rld_fcram_mode {
285 struct cvmx_asxx_rld_fcram_mode_s {
286 u64 reserved_1_63 : 63;
289 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
290 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
293 typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
296 * cvmx_asx#_rld_nctl_strong
298 * ASX_RLD_NCTL_STRONG
301 union cvmx_asxx_rld_nctl_strong {
303 struct cvmx_asxx_rld_nctl_strong_s {
304 u64 reserved_5_63 : 59;
307 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
308 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
309 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
310 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
313 typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
316 * cvmx_asx#_rld_nctl_weak
321 union cvmx_asxx_rld_nctl_weak {
323 struct cvmx_asxx_rld_nctl_weak_s {
324 u64 reserved_5_63 : 59;
327 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
328 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
329 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
330 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
333 typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
336 * cvmx_asx#_rld_pctl_strong
338 * ASX_RLD_PCTL_STRONG
341 union cvmx_asxx_rld_pctl_strong {
343 struct cvmx_asxx_rld_pctl_strong_s {
344 u64 reserved_5_63 : 59;
347 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
348 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
349 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
350 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
353 typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
356 * cvmx_asx#_rld_pctl_weak
361 union cvmx_asxx_rld_pctl_weak {
363 struct cvmx_asxx_rld_pctl_weak_s {
364 u64 reserved_5_63 : 59;
367 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
368 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
369 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
370 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
373 typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
376 * cvmx_asx#_rld_setting
381 union cvmx_asxx_rld_setting {
383 struct cvmx_asxx_rld_setting_s {
384 u64 reserved_13_63 : 51;
391 struct cvmx_asxx_rld_setting_cn38xx {
392 u64 reserved_5_63 : 59;
395 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
396 struct cvmx_asxx_rld_setting_s cn58xx;
397 struct cvmx_asxx_rld_setting_s cn58xxp1;
400 typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
403 * cvmx_asx#_rx_clk_set#
405 * ASX_RX_CLK_SET = RGMII Clock delay setting
409 * Setting to place on the open-loop RXC (RGMII receive clk)
410 * delay line, which can delay the received clock. This
411 * can be used if the board and/or transmitting device
412 * has not otherwise delayed the clock.
414 * A value of SETTING=0 disables the delay line. The delay
415 * line should be disabled unless the transmitter or board
416 * does not delay the clock.
418 * Note that this delay line provides only a coarse control
419 * over the delay. Generally, it can only reliably provide
420 * a delay in the range 1.25-2.5ns, which may not be adequate
421 * for some system applications.
423 * The open loop delay line selects
424 * from among a series of tap positions. Each incremental
425 * tap position adds a delay of 50ps to 135ps per tap, depending
426 * on the chip, its temperature, and the voltage.
427 * To achieve from 1.25-2.5ns of delay on the received
428 * clock, a fixed value of SETTING=24 may work.
429 * For more precision, we recommend the following settings
430 * based on the chip voltage:
433 * -----------------------------
442 union cvmx_asxx_rx_clk_setx {
444 struct cvmx_asxx_rx_clk_setx_s {
445 u64 reserved_5_63 : 59;
448 struct cvmx_asxx_rx_clk_setx_s cn30xx;
449 struct cvmx_asxx_rx_clk_setx_s cn31xx;
450 struct cvmx_asxx_rx_clk_setx_s cn38xx;
451 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
452 struct cvmx_asxx_rx_clk_setx_s cn50xx;
453 struct cvmx_asxx_rx_clk_setx_s cn58xx;
454 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
457 typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
460 * cvmx_asx#_rx_prt_en
462 * ASX_RX_PRT_EN = RGMII Port Enable
465 union cvmx_asxx_rx_prt_en {
467 struct cvmx_asxx_rx_prt_en_s {
468 u64 reserved_4_63 : 60;
471 struct cvmx_asxx_rx_prt_en_cn30xx {
472 u64 reserved_3_63 : 61;
475 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
476 struct cvmx_asxx_rx_prt_en_s cn38xx;
477 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
478 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
479 struct cvmx_asxx_rx_prt_en_s cn58xx;
480 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
483 typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
488 * ASX_RX_WOL = RGMII RX Wake on LAN status register
491 union cvmx_asxx_rx_wol {
493 struct cvmx_asxx_rx_wol_s {
494 u64 reserved_2_63 : 62;
498 struct cvmx_asxx_rx_wol_s cn38xx;
499 struct cvmx_asxx_rx_wol_s cn38xxp2;
502 typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
505 * cvmx_asx#_rx_wol_msk
507 * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
510 union cvmx_asxx_rx_wol_msk {
512 struct cvmx_asxx_rx_wol_msk_s {
515 struct cvmx_asxx_rx_wol_msk_s cn38xx;
516 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
519 typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
522 * cvmx_asx#_rx_wol_powok
524 * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
527 union cvmx_asxx_rx_wol_powok {
529 struct cvmx_asxx_rx_wol_powok_s {
530 u64 reserved_1_63 : 63;
533 struct cvmx_asxx_rx_wol_powok_s cn38xx;
534 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
537 typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
540 * cvmx_asx#_rx_wol_sig
542 * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
545 union cvmx_asxx_rx_wol_sig {
547 struct cvmx_asxx_rx_wol_sig_s {
548 u64 reserved_32_63 : 32;
551 struct cvmx_asxx_rx_wol_sig_s cn38xx;
552 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
555 typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
558 * cvmx_asx#_tx_clk_set#
560 * ASX_TX_CLK_SET = RGMII Clock delay setting
564 * Setting to place on the open-loop TXC (RGMII transmit clk)
565 * delay line, which can delay the transmited clock. This
566 * can be used if the board and/or transmitting device
567 * has not otherwise delayed the clock.
569 * A value of SETTING=0 disables the delay line. The delay
570 * line should be disabled unless the transmitter or board
571 * does not delay the clock.
573 * Note that this delay line provides only a coarse control
574 * over the delay. Generally, it can only reliably provide
575 * a delay in the range 1.25-2.5ns, which may not be adequate
576 * for some system applications.
578 * The open loop delay line selects
579 * from among a series of tap positions. Each incremental
580 * tap position adds a delay of 50ps to 135ps per tap, depending
581 * on the chip, its temperature, and the voltage.
582 * To achieve from 1.25-2.5ns of delay on the received
583 * clock, a fixed value of SETTING=24 may work.
584 * For more precision, we recommend the following settings
585 * based on the chip voltage:
588 * -----------------------------
597 union cvmx_asxx_tx_clk_setx {
599 struct cvmx_asxx_tx_clk_setx_s {
600 u64 reserved_5_63 : 59;
603 struct cvmx_asxx_tx_clk_setx_s cn30xx;
604 struct cvmx_asxx_tx_clk_setx_s cn31xx;
605 struct cvmx_asxx_tx_clk_setx_s cn38xx;
606 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
607 struct cvmx_asxx_tx_clk_setx_s cn50xx;
608 struct cvmx_asxx_tx_clk_setx_s cn58xx;
609 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
612 typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
615 * cvmx_asx#_tx_comp_byp
617 * ASX_TX_COMP_BYP = RGMII Clock delay setting
620 union cvmx_asxx_tx_comp_byp {
622 struct cvmx_asxx_tx_comp_byp_s {
623 u64 reserved_0_63 : 64;
625 struct cvmx_asxx_tx_comp_byp_cn30xx {
626 u64 reserved_9_63 : 55;
631 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
632 struct cvmx_asxx_tx_comp_byp_cn38xx {
633 u64 reserved_8_63 : 56;
637 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
638 struct cvmx_asxx_tx_comp_byp_cn50xx {
639 u64 reserved_17_63 : 47;
641 u64 reserved_13_15 : 3;
643 u64 reserved_5_7 : 3;
646 struct cvmx_asxx_tx_comp_byp_cn58xx {
647 u64 reserved_13_63 : 51;
649 u64 reserved_5_7 : 3;
652 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
655 typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
658 * cvmx_asx#_tx_hi_water#
660 * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
663 union cvmx_asxx_tx_hi_waterx {
665 struct cvmx_asxx_tx_hi_waterx_s {
666 u64 reserved_4_63 : 60;
669 struct cvmx_asxx_tx_hi_waterx_cn30xx {
670 u64 reserved_3_63 : 61;
673 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
674 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
675 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
676 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
677 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
678 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
681 typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
684 * cvmx_asx#_tx_prt_en
686 * ASX_TX_PRT_EN = RGMII Port Enable
689 union cvmx_asxx_tx_prt_en {
691 struct cvmx_asxx_tx_prt_en_s {
692 u64 reserved_4_63 : 60;
695 struct cvmx_asxx_tx_prt_en_cn30xx {
696 u64 reserved_3_63 : 61;
699 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
700 struct cvmx_asxx_tx_prt_en_s cn38xx;
701 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
702 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
703 struct cvmx_asxx_tx_prt_en_s cn58xx;
704 struct cvmx_asxx_tx_prt_en_s cn58xxp1;
707 typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;