1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 Marvell International Ltd.
6 #include <asm/global_data.h>
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/compat.h>
11 #include <mach/clock.h>
12 #include <mach/cavm-reg.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static int get_clocks(void)
18 const u64 ref_clock = PLL_REF_CLK;
19 void __iomem *rst_boot;
22 rst_boot = ioremap(CAVM_RST_BOOT, 0);
23 val = ioread64(rst_boot);
24 gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
25 gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
27 debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
32 /* Early mach init code run from flash */
33 int mach_cpu_init(void)
35 void __iomem *mio_boot_reg_cfg0;
37 /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
38 /* ToDo: Move this to an early running bus (bootbus) DM driver */
39 mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
40 clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
42 /* Get clocks and store them in GD */
49 * Returns number of cores
51 * @return number of CPU cores for the specified node
53 static int cavm_octeon_num_cores(void)
55 void __iomem *ciu_fuse;
57 ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
58 return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
61 int print_cpuinfo(void)
63 printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());