1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 MediaTek Inc.
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
12 void mtmips_spl_serial_init(void)
14 #ifdef CONFIG_SPL_SERIAL_SUPPORT
15 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
17 #if CONFIG_CONS_INDEX == 1
18 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
19 #elif CONFIG_CONS_INDEX == 2
20 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
21 #elif CONFIG_CONS_INDEX == 3
22 setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
23 #ifdef CONFIG_SPL_UART2_SPIS_PINMUX
24 setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
25 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
28 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
29 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
31 #endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
32 #endif /* CONFIG_CONS_INDEX */
33 #endif /* CONFIG_SPL_SERIAL_SUPPORT */