1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
5 * This code is mostly based on the code extracted from this MediaTek
8 * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
10 * I was not able to find a specific license or other developers
11 * copyrights here, so I can't add them here.
13 * Most functions in this file are copied from the MediaTek U-Boot
14 * repository. Without any documentation, it was impossible to really
15 * implement this differently. So its mostly a cleaned-up version of
16 * the original code, with only support for the MT7628 / MT7688 SoC.
22 #include <asm/cacheops.h>
26 #define NUM_OF_CACHELINE 128
28 #define MIN_FINE_START 0xf
30 #define MAX_FINE_START 0x0
32 #define CPU_FRAC_DIV 1
34 #if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
35 #define DRAM_BUTTOM 0x02000000
37 #if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
38 #define DRAM_BUTTOM 0x04000000
40 #if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
41 #define DRAM_BUTTOM 0x08000000
43 #if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
44 #define DRAM_BUTTOM 0x10000000
47 static inline void cal_memcpy(void *src, void *dst, u32 size)
53 for (i = 0; i < size; i++, psrc++, pdst++)
57 static inline void cal_memset(void *src, u8 pat, u32 size)
62 for (i = 0; i < size; i++, psrc++)
66 #define pref_op(hint, addr) \
67 __asm__ __volatile__( \
73 : "i" (hint), "R" (*(u8 *)(addr)))
75 static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
77 u32 *addr = (u32 *)start_addr;
80 for (i = 0; i < size; i++)
81 addr[i] = start_addr + i + bias;
84 static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
85 u32 offs, u32 pat, u32 val)
91 for (nc_addr = 0xa0000000;
92 nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
93 nc_addr += (DRAM_BUTTOM >> 6) + offs) {
94 writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
95 wmb(); /* Make sure store if finished */
97 c_addr = (u32 *)(nc_addr & 0xdfffffff);
98 cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
99 cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
103 (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
104 (((k == 0) ? val : test_dqs) << 8),
105 (void *)MT76XX_MEMCTRL_BASE + 0x64);
108 (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
109 (((k == 0) ? val : test_dqs) << 0),
110 (void *)MT76XX_MEMCTRL_BASE + 0x64);
111 wmb(); /* Make sure store if finished */
113 invalidate_dcache_range((u32)c_addr,
115 NUM_OF_CACHELINE * 32);
116 wmb(); /* Make sure store if finished */
118 for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
120 pref_op(0, &c_addr[i]);
123 for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
124 if (c_addr[i] != nc_addr + i + pat)
132 void ddr_calibrate(void)
134 u32 min_coarse_dqs[2];
135 u32 max_coarse_dqs[2];
140 int reg = 0, ddr_cfg2_reg;
144 u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
146 u32 fdiv = 0, frac = 0;
148 /* Setup clock to run at full speed */
149 val = readl((void *)MT76XX_DYN_CFG0_REG);
150 fdiv = (u32)((val >> 8) & 0x0F);
151 if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
156 while (frac < fdiv) {
157 val = readl((void *)MT76XX_DYN_CFG0_REG);
158 fdiv = (val >> 8) & 0x0f;
162 writel(val, (void *)MT76XX_DYN_CFG0_REG);
164 val = readl((void *)MT76XX_DYN_CFG0_REG);
165 fdiv = (val >> 8) & 0x0f;
168 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
169 ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
170 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
171 (0x3 << 28) | (0x3 << 26));
173 min_coarse_dqs[0] = MIN_START;
174 min_coarse_dqs[1] = MIN_START;
175 min_fine_dqs[0] = MIN_FINE_START;
176 min_fine_dqs[1] = MIN_FINE_START;
177 max_coarse_dqs[0] = MAX_START;
178 max_coarse_dqs[1] = MAX_START;
179 max_fine_dqs[0] = MAX_FINE_START;
180 max_fine_dqs[1] = MAX_FINE_START;
183 /* Add by KP, DQS MIN boundary */
184 reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
185 coarse_dqs_dll = (reg & 0xf00) >> 8;
186 fine_dqs_dll = (reg & 0xf0) >> 4;
187 if (coarse_dqs_dll <= 8)
188 min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
190 min_coarse_dqs_bnd = 0;
192 if (fine_dqs_dll <= 8)
193 min_fine_dqs_bnd = 8 - fine_dqs_dll;
195 min_fine_dqs_bnd = 0;
196 /* DQS MIN boundary */
200 for (k = 0; k < 2; k++) {
204 test_dqs = MAX_START;
206 test_dqs = MAX_FINE_START;
209 flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
215 } while (test_dqs <= 0xf);
218 max_coarse_dqs[dqs] = test_dqs;
222 if (test_dqs == MAX_FINE_START - 1) {
223 max_coarse_dqs[dqs]--;
224 max_fine_dqs[dqs] = 0xf;
226 max_fine_dqs[dqs] = test_dqs;
231 for (k = 0; k < 2; k++) {
235 test_dqs = MIN_START;
237 test_dqs = MIN_FINE_START;
240 flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
244 test_dqs == min_coarse_dqs_bnd)
249 if (test_dqs < min_coarse_dqs_bnd)
255 } else if (test_dqs == min_fine_dqs_bnd) {
261 if (test_dqs < min_fine_dqs_bnd)
264 } while (test_dqs >= 0);
267 min_coarse_dqs[dqs] = test_dqs;
269 if (test_dqs == MIN_FINE_START + 1) {
270 min_coarse_dqs[dqs]++;
271 min_fine_dqs[dqs] = 0x0;
273 min_fine_dqs[dqs] = test_dqs;
283 for (i = 0; i < 2; i++) {
286 coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
288 (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
289 ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
292 fine_dqs[i] = (temp - 0x10) + 0x8;
297 reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
298 (coarse_dqs[0] << 4) | fine_dqs[0];
300 clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
301 writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
302 writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
303 setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
305 for (i = 0; i < 2; i++)
306 debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
307 min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
308 debug("\nDDR Calibration DQS reg = %08X\n", reg);