arch/mips/mach-mscc/reset.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 #include <common.h>
   7
   8 #include <asm/sections.h>
   9 #include <asm/io.h>
  10
  11 #include <asm/reboot.h>
  12
  13 void _machine_restart(void)
  14 {
  15 #if defined(CONFIG_SOC_JR2)
  16         register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
  17         /* Set owner */
  18         reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
  19         reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
  20         /* Set boot mode */
  21         reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
  22         writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
  23         /* Read back in order to make BOOT mode setting active */
  24         reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
  25         /* Reset CPU only - still executing _here_. but from cache */
  26         writel(readl(BASE_CFG + ICPU_RESET) |
  27                ICPU_RESET_CORE_RST_CPU_ONLY |
  28                ICPU_RESET_CORE_RST_FORCE,
  29                BASE_CFG + ICPU_RESET);
  30 #else
  31         register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
  32         (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
  33
  34         /* Make sure VCore is NOT protected from reset */
  35         clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
  36
  37         /* Change to SPI bitbang for SPI reset workaround... */
  38         writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
  39                ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
  40
  41         /* Do the global reset */
  42         writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
  43 #endif
  44
  45         while (1)
  46                 ; /* NOP */
  47 }