arch/mips/mach-mscc/dram.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 #include <common.h>
   7
   8 #include <asm/io.h>
   9 #include <asm/types.h>
  10
  11 #include <mach/tlb.h>
  12 #include <mach/ddr.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 static inline int vcoreiii_train_bytelane(void)
  17 {
  18         int ret;
  19
  20         ret = hal_vcoreiii_train_bytelane(0);
  21
  22 #if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
  23         defined(CONFIG_SOC_SERVALT)
  24         if (ret)
  25                 return ret;
  26         ret = hal_vcoreiii_train_bytelane(1);
  27 #endif
  28
  29         return ret;
  30 }
  31
  32 int vcoreiii_ddr_init(void)
  33 {
  34         int res;
  35
  36         if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
  37               & ICPU_MEMCTRL_STAT_INIT_DONE)) {
  38                 hal_vcoreiii_init_memctl();
  39                 hal_vcoreiii_wait_memctl();
  40                 if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
  41                         hal_vcoreiii_ddr_failed();
  42         }
  43 #if (CONFIG_SYS_TEXT_BASE != 0x20000000)
  44         res = dram_check();
  45         if (res == 0)
  46                 hal_vcoreiii_ddr_verified();
  47         else
  48                 hal_vcoreiii_ddr_failed();
  49
  50         /* Clear boot-mode and read-back to activate/verify */
  51         clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  52                      ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
  53         readl(BASE_CFG + ICPU_GENERAL_CTRL);
  54 #else
  55         res = 0;
  56 #endif
  57         return res;
  58 }
  59
  60 int print_cpuinfo(void)
  61 {
  62         printf("MSCC VCore-III MIPS 24Kec\n");
  63
  64         return 0;
  65 }
  66
  67 int dram_init(void)
  68 {
  69         while (vcoreiii_ddr_init())
  70                 ;
  71
  72         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  73         return 0;
  74 }