1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
5 * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <linux/delay.h>
13 #include <mach/ar71xx_regs.h>
14 #include <mach/ath79.h>
16 DECLARE_GLOBAL_DATA_PTR;
24 struct ar934x_mem_config {
32 static const struct ar934x_mem_config ar934x_mem_config[] = {
33 [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
34 [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
35 [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
38 void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
40 void __iomem *ddr_regs;
41 const struct ar934x_mem_config *memcfg;
45 ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
48 reg = ath79_get_bootstrap();
49 if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
50 if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
51 memtype = AR934X_DDR1;
54 memtype = AR934X_DDR2;
56 ctl = BIT(6); /* Undocumented bit :-( */
62 /* Force DDR2/x16 configuratio on old chips. */
64 cycle = 0xffff; /* DDR2 16bit */
67 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
70 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
73 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
76 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
80 memtype = AR934X_SDRAM;
83 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
86 /* Undocumented register */
87 writel(0x13b, ddr_regs + 0x118);
91 memcfg = &ar934x_mem_config[memtype];
93 writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
96 writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
99 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
102 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
105 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
108 if (memtype == AR934X_DDR2) {
109 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
112 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
116 if (memtype != AR934X_SDRAM)
117 writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
121 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
124 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
127 writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
130 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
133 writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
136 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
137 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
139 if (memtype != AR934X_SDRAM) {
140 if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
142 ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
144 ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
148 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
151 writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
154 writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
157 writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
161 void ddr_tap_tuning(void)