3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/cacheops.h>
10 #ifdef CONFIG_MIPS_L2_CACHE
14 #include <asm/mipsregs.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 static void probe_l2(void)
20 #ifdef CONFIG_MIPS_L2_CACHE
21 unsigned long conf2, sl;
24 if (!(read_c0_config1() & MIPS_CONF_M))
27 conf2 = read_c0_config2();
29 if (__mips_isa_rev >= 6) {
30 l2c = conf2 & MIPS_CONF_M;
32 l2c = read_c0_config3() & MIPS_CONF_M;
34 l2c = read_c0_config4() & MIPS_CONF_M;
36 l2c = read_c0_config5() & MIPS_CONF5_L2C;
39 if (l2c && config_enabled(CONFIG_MIPS_CM)) {
40 gd->arch.l2_line_size = mips_cm_l2_line_size();
42 /* We don't know how to retrieve L2 config on this system */
45 sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF;
46 gd->arch.l2_line_size = sl ? (2 << sl) : 0;
51 void mips_cache_probe(void)
53 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
54 unsigned long conf1, il, dl;
56 conf1 = read_c0_config1();
58 il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
59 dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
61 gd->arch.l1i_line_size = il ? (2 << il) : 0;
62 gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
67 static inline unsigned long icache_line_size(void)
69 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
70 return gd->arch.l1i_line_size;
72 return CONFIG_SYS_ICACHE_LINE_SIZE;
76 static inline unsigned long dcache_line_size(void)
78 #ifdef CONFIG_SYS_CACHE_SIZE_AUTO
79 return gd->arch.l1d_line_size;
81 return CONFIG_SYS_DCACHE_LINE_SIZE;
85 static inline unsigned long scache_line_size(void)
87 #ifdef CONFIG_MIPS_L2_CACHE
88 return gd->arch.l2_line_size;
94 #define cache_loop(start, end, lsize, ops...) do { \
95 const void *addr = (const void *)(start & ~(lsize - 1)); \
96 const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
97 const unsigned int cache_ops[] = { ops }; \
100 for (; addr <= aend; addr += lsize) { \
101 for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
102 mips_cache(cache_ops[i], addr); \
106 void flush_cache(ulong start_addr, ulong size)
108 unsigned long ilsize = icache_line_size();
109 unsigned long dlsize = dcache_line_size();
110 unsigned long slsize = scache_line_size();
112 /* aend will be miscalculated when size is zero, so we return here */
116 if ((ilsize == dlsize) && !slsize) {
117 /* flush I-cache & D-cache simultaneously */
118 cache_loop(start_addr, start_addr + size, ilsize,
119 HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
124 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
128 cache_loop(start_addr, start_addr + size, slsize,
129 HIT_WRITEBACK_INV_SD);
132 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
135 /* ensure cache ops complete before any further memory accesses */
139 void flush_dcache_range(ulong start_addr, ulong stop)
141 unsigned long lsize = dcache_line_size();
142 unsigned long slsize = scache_line_size();
144 /* aend will be miscalculated when size is zero, so we return here */
145 if (start_addr == stop)
148 cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
152 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD);
154 /* ensure cache ops complete before any further memory accesses */
158 void invalidate_dcache_range(ulong start_addr, ulong stop)
160 unsigned long lsize = dcache_line_size();
161 unsigned long slsize = scache_line_size();
163 /* aend will be miscalculated when size is zero, so we return here */
164 if (start_addr == stop)
167 /* invalidate L2 cache */
169 cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
171 cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
173 /* ensure cache ops complete before any further memory accesses */