arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/memblock.h>
  22 #include <linux/pgtable.h>
  23
  24 #include <asm/fpu.h>
  25 #include <asm/page.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/pgalloc.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33
  34 #define CREATE_TRACE_POINTS
  35 #include "trace.h"
  36
  37 #ifndef VECTORSPACING
  38 #define VECTORSPACING 0x100     /* for EI/VI mode */
  39 #endif
  40
  41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
  42         KVM_GENERIC_VM_STATS()
  43 };
  44
  45 const struct kvm_stats_header kvm_vm_stats_header = {
  46         .name_size = KVM_STATS_NAME_SIZE,
  47         .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
  48         .id_offset = sizeof(struct kvm_stats_header),
  49         .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
  50         .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
  51                        sizeof(kvm_vm_stats_desc),
  52 };
  53
  54 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
  55         KVM_GENERIC_VCPU_STATS(),
  56         STATS_DESC_COUNTER(VCPU, wait_exits),
  57         STATS_DESC_COUNTER(VCPU, cache_exits),
  58         STATS_DESC_COUNTER(VCPU, signal_exits),
  59         STATS_DESC_COUNTER(VCPU, int_exits),
  60         STATS_DESC_COUNTER(VCPU, cop_unusable_exits),
  61         STATS_DESC_COUNTER(VCPU, tlbmod_exits),
  62         STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits),
  63         STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits),
  64         STATS_DESC_COUNTER(VCPU, addrerr_st_exits),
  65         STATS_DESC_COUNTER(VCPU, addrerr_ld_exits),
  66         STATS_DESC_COUNTER(VCPU, syscall_exits),
  67         STATS_DESC_COUNTER(VCPU, resvd_inst_exits),
  68         STATS_DESC_COUNTER(VCPU, break_inst_exits),
  69         STATS_DESC_COUNTER(VCPU, trap_inst_exits),
  70         STATS_DESC_COUNTER(VCPU, msa_fpe_exits),
  71         STATS_DESC_COUNTER(VCPU, fpe_exits),
  72         STATS_DESC_COUNTER(VCPU, msa_disabled_exits),
  73         STATS_DESC_COUNTER(VCPU, flush_dcache_exits),
  74         STATS_DESC_COUNTER(VCPU, vz_gpsi_exits),
  75         STATS_DESC_COUNTER(VCPU, vz_gsfc_exits),
  76         STATS_DESC_COUNTER(VCPU, vz_hc_exits),
  77         STATS_DESC_COUNTER(VCPU, vz_grr_exits),
  78         STATS_DESC_COUNTER(VCPU, vz_gva_exits),
  79         STATS_DESC_COUNTER(VCPU, vz_ghfc_exits),
  80         STATS_DESC_COUNTER(VCPU, vz_gpa_exits),
  81         STATS_DESC_COUNTER(VCPU, vz_resvd_exits),
  82 #ifdef CONFIG_CPU_LOONGSON64
  83         STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits),
  84 #endif
  85 };
  86
  87 const struct kvm_stats_header kvm_vcpu_stats_header = {
  88         .name_size = KVM_STATS_NAME_SIZE,
  89         .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
  90         .id_offset = sizeof(struct kvm_stats_header),
  91         .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
  92         .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
  93                        sizeof(kvm_vcpu_stats_desc),
  94 };
  95
  96 bool kvm_trace_guest_mode_change;
  97
  98 int kvm_guest_mode_change_trace_reg(void)
  99 {
 100         kvm_trace_guest_mode_change = true;
 101         return 0;
 102 }
 103
 104 void kvm_guest_mode_change_trace_unreg(void)
 105 {
 106         kvm_trace_guest_mode_change = false;
 107 }
 108
 109 /*
 110  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
 111  * Config7, so we are "runnable" if interrupts are pending
 112  */
 113 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 114 {
 115         return !!(vcpu->arch.pending_exceptions);
 116 }
 117
 118 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 119 {
 120         return false;
 121 }
 122
 123 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 124 {
 125         return 1;
 126 }
 127
 128 int kvm_arch_hardware_enable(void)
 129 {
 130         return kvm_mips_callbacks->hardware_enable();
 131 }
 132
 133 void kvm_arch_hardware_disable(void)
 134 {
 135         kvm_mips_callbacks->hardware_disable();
 136 }
 137
 138 int kvm_arch_hardware_setup(void *opaque)
 139 {
 140         return 0;
 141 }
 142
 143 int kvm_arch_check_processor_compat(void *opaque)
 144 {
 145         return 0;
 146 }
 147
 148 extern void kvm_init_loongson_ipi(struct kvm *kvm);
 149
 150 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 151 {
 152         switch (type) {
 153         case KVM_VM_MIPS_AUTO:
 154                 break;
 155         case KVM_VM_MIPS_VZ:
 156                 break;
 157         default:
 158                 /* Unsupported KVM type */
 159                 return -EINVAL;
 160         }
 161
 162         /* Allocate page table to map GPA -> RPA */
 163         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 164         if (!kvm->arch.gpa_mm.pgd)
 165                 return -ENOMEM;
 166
 167 #ifdef CONFIG_CPU_LOONGSON64
 168         kvm_init_loongson_ipi(kvm);
 169 #endif
 170
 171         return 0;
 172 }
 173
 174 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 175 {
 176         /* It should always be safe to remove after flushing the whole range */
 177         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 178         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 179 }
 180
 181 void kvm_arch_destroy_vm(struct kvm *kvm)
 182 {
 183         kvm_destroy_vcpus(kvm);
 184         kvm_mips_free_gpa_pt(kvm);
 185 }
 186
 187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 188                         unsigned long arg)
 189 {
 190         return -ENOIOCTLCMD;
 191 }
 192
 193 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 194 {
 195         /* Flush whole GPA */
 196         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 197         kvm_flush_remote_tlbs(kvm);
 198 }
 199
 200 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 201                                    struct kvm_memory_slot *slot)
 202 {
 203         /*
 204          * The slot has been made invalid (ready for moving or deletion), so we
 205          * need to ensure that it can no longer be accessed by any guest VCPUs.
 206          */
 207
 208         spin_lock(&kvm->mmu_lock);
 209         /* Flush slot from GPA */
 210         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 211                               slot->base_gfn + slot->npages - 1);
 212         kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
 213         spin_unlock(&kvm->mmu_lock);
 214 }
 215
 216 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 217                                    const struct kvm_memory_slot *old,
 218                                    struct kvm_memory_slot *new,
 219                                    enum kvm_mr_change change)
 220 {
 221         return 0;
 222 }
 223
 224 void kvm_arch_commit_memory_region(struct kvm *kvm,
 225                                    struct kvm_memory_slot *old,
 226                                    const struct kvm_memory_slot *new,
 227                                    enum kvm_mr_change change)
 228 {
 229         int needs_flush;
 230
 231         /*
 232          * If dirty page logging is enabled, write protect all pages in the slot
 233          * ready for dirty logging.
 234          *
 235          * There is no need to do this in any of the following cases:
 236          * CREATE:      No dirty mappings will already exist.
 237          * MOVE/DELETE: The old mappings will already have been cleaned up by
 238          *              kvm_arch_flush_shadow_memslot()
 239          */
 240         if (change == KVM_MR_FLAGS_ONLY &&
 241             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 242              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 243                 spin_lock(&kvm->mmu_lock);
 244                 /* Write protect GPA page table entries */
 245                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 246                                         new->base_gfn + new->npages - 1);
 247                 if (needs_flush)
 248                         kvm_arch_flush_remote_tlbs_memslot(kvm, new);
 249                 spin_unlock(&kvm->mmu_lock);
 250         }
 251 }
 252
 253 static inline void dump_handler(const char *symbol, void *start, void *end)
 254 {
 255         u32 *p;
 256
 257         pr_debug("LEAF(%s)\n", symbol);
 258
 259         pr_debug("\t.set push\n");
 260         pr_debug("\t.set noreorder\n");
 261
 262         for (p = start; p < (u32 *)end; ++p)
 263                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 264
 265         pr_debug("\t.set\tpop\n");
 266
 267         pr_debug("\tEND(%s)\n", symbol);
 268 }
 269
 270 /* low level hrtimer wake routine */
 271 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
 272 {
 273         struct kvm_vcpu *vcpu;
 274
 275         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
 276
 277         kvm_mips_callbacks->queue_timer_int(vcpu);
 278
 279         vcpu->arch.wait = 0;
 280         rcuwait_wake_up(&vcpu->wait);
 281
 282         return kvm_mips_count_timeout(vcpu);
 283 }
 284
 285 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 286 {
 287         return 0;
 288 }
 289
 290 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 291 {
 292         int err, size;
 293         void *gebase, *p, *handler, *refill_start, *refill_end;
 294         int i;
 295
 296         kvm_debug("kvm @ %p: create cpu %d at %p\n",
 297                   vcpu->kvm, vcpu->vcpu_id, vcpu);
 298
 299         err = kvm_mips_callbacks->vcpu_init(vcpu);
 300         if (err)
 301                 return err;
 302
 303         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
 304                      HRTIMER_MODE_REL);
 305         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
 306
 307         /*
 308          * Allocate space for host mode exception handlers that handle
 309          * guest mode exits
 310          */
 311         if (cpu_has_veic || cpu_has_vint)
 312                 size = 0x200 + VECTORSPACING * 64;
 313         else
 314                 size = 0x4000;
 315
 316         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 317
 318         if (!gebase) {
 319                 err = -ENOMEM;
 320                 goto out_uninit_vcpu;
 321         }
 322         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 323                   ALIGN(size, PAGE_SIZE), gebase);
 324
 325         /*
 326          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 327          * limits us to the low 512MB of physical address space. If the memory
 328          * we allocate is out of range, just give up now.
 329          */
 330         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 331                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 332                         gebase);
 333                 err = -ENOMEM;
 334                 goto out_free_gebase;
 335         }
 336
 337         /* Save new ebase */
 338         vcpu->arch.guest_ebase = gebase;
 339
 340         /* Build guest exception vectors dynamically in unmapped memory */
 341         handler = gebase + 0x2000;
 342
 343         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 344         refill_start = gebase;
 345         if (IS_ENABLED(CONFIG_64BIT))
 346                 refill_start += 0x080;
 347         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 348
 349         /* General Exception Entry point */
 350         kvm_mips_build_exception(gebase + 0x180, handler);
 351
 352         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 353         for (i = 0; i < 8; i++) {
 354                 kvm_debug("L1 Vectored handler @ %p\n",
 355                           gebase + 0x200 + (i * VECTORSPACING));
 356                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 357                                          handler);
 358         }
 359
 360         /* General exit handler */
 361         p = handler;
 362         p = kvm_mips_build_exit(p);
 363
 364         /* Guest entry routine */
 365         vcpu->arch.vcpu_run = p;
 366         p = kvm_mips_build_vcpu_run(p);
 367
 368         /* Dump the generated code */
 369         pr_debug("#include <asm/asm.h>\n");
 370         pr_debug("#include <asm/regdef.h>\n");
 371         pr_debug("\n");
 372         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 373         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 374         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 375         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 376
 377         /* Invalidate the icache for these ranges */
 378         flush_icache_range((unsigned long)gebase,
 379                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 380
 381         /* Init */
 382         vcpu->arch.last_sched_cpu = -1;
 383         vcpu->arch.last_exec_cpu = -1;
 384
 385         /* Initial guest state */
 386         err = kvm_mips_callbacks->vcpu_setup(vcpu);
 387         if (err)
 388                 goto out_free_gebase;
 389
 390         return 0;
 391
 392 out_free_gebase:
 393         kfree(gebase);
 394 out_uninit_vcpu:
 395         kvm_mips_callbacks->vcpu_uninit(vcpu);
 396         return err;
 397 }
 398
 399 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 400 {
 401         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 402
 403         kvm_mips_dump_stats(vcpu);
 404
 405         kvm_mmu_free_memory_caches(vcpu);
 406         kfree(vcpu->arch.guest_ebase);
 407
 408         kvm_mips_callbacks->vcpu_uninit(vcpu);
 409 }
 410
 411 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 412                                         struct kvm_guest_debug *dbg)
 413 {
 414         return -ENOIOCTLCMD;
 415 }
 416
 417 /*
 418  * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
 419  * the vCPU is running.
 420  *
 421  * This must be noinstr as instrumentation may make use of RCU, and this is not
 422  * safe during the EQS.
 423  */
 424 static int noinstr kvm_mips_vcpu_enter_exit(struct kvm_vcpu *vcpu)
 425 {
 426         int ret;
 427
 428         guest_state_enter_irqoff();
 429         ret = kvm_mips_callbacks->vcpu_run(vcpu);
 430         guest_state_exit_irqoff();
 431
 432         return ret;
 433 }
 434
 435 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
 436 {
 437         int r = -EINTR;
 438
 439         vcpu_load(vcpu);
 440
 441         kvm_sigset_activate(vcpu);
 442
 443         if (vcpu->mmio_needed) {
 444                 if (!vcpu->mmio_is_write)
 445                         kvm_mips_complete_mmio_load(vcpu);
 446                 vcpu->mmio_needed = 0;
 447         }
 448
 449         if (vcpu->run->immediate_exit)
 450                 goto out;
 451
 452         lose_fpu(1);
 453
 454         local_irq_disable();
 455         guest_timing_enter_irqoff();
 456         trace_kvm_enter(vcpu);
 457
 458         /*
 459          * Make sure the read of VCPU requests in vcpu_run() callback is not
 460          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 461          * flush request while the requester sees the VCPU as outside of guest
 462          * mode and not needing an IPI.
 463          */
 464         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 465
 466         r = kvm_mips_vcpu_enter_exit(vcpu);
 467
 468         /*
 469          * We must ensure that any pending interrupts are taken before
 470          * we exit guest timing so that timer ticks are accounted as
 471          * guest time. Transiently unmask interrupts so that any
 472          * pending interrupts are taken.
 473          *
 474          * TODO: is there a barrier which ensures that pending interrupts are
 475          * recognised? Currently this just hopes that the CPU takes any pending
 476          * interrupts between the enable and disable.
 477          */
 478         local_irq_enable();
 479         local_irq_disable();
 480
 481         trace_kvm_out(vcpu);
 482         guest_timing_exit_irqoff();
 483         local_irq_enable();
 484
 485 out:
 486         kvm_sigset_deactivate(vcpu);
 487
 488         vcpu_put(vcpu);
 489         return r;
 490 }
 491
 492 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 493                              struct kvm_mips_interrupt *irq)
 494 {
 495         int intr = (int)irq->irq;
 496         struct kvm_vcpu *dvcpu = NULL;
 497
 498         if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
 499             intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
 500             intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
 501             intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
 502                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 503                           (int)intr);
 504
 505         if (irq->cpu == -1)
 506                 dvcpu = vcpu;
 507         else
 508                 dvcpu = kvm_get_vcpu(vcpu->kvm, irq->cpu);
 509
 510         if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
 511                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 512
 513         } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
 514                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 515         } else {
 516                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 517                         irq->cpu, irq->irq);
 518                 return -EINVAL;
 519         }
 520
 521         dvcpu->arch.wait = 0;
 522
 523         rcuwait_wake_up(&dvcpu->wait);
 524
 525         return 0;
 526 }
 527
 528 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 529                                     struct kvm_mp_state *mp_state)
 530 {
 531         return -ENOIOCTLCMD;
 532 }
 533
 534 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 535                                     struct kvm_mp_state *mp_state)
 536 {
 537         return -ENOIOCTLCMD;
 538 }
 539
 540 static u64 kvm_mips_get_one_regs[] = {
 541         KVM_REG_MIPS_R0,
 542         KVM_REG_MIPS_R1,
 543         KVM_REG_MIPS_R2,
 544         KVM_REG_MIPS_R3,
 545         KVM_REG_MIPS_R4,
 546         KVM_REG_MIPS_R5,
 547         KVM_REG_MIPS_R6,
 548         KVM_REG_MIPS_R7,
 549         KVM_REG_MIPS_R8,
 550         KVM_REG_MIPS_R9,
 551         KVM_REG_MIPS_R10,
 552         KVM_REG_MIPS_R11,
 553         KVM_REG_MIPS_R12,
 554         KVM_REG_MIPS_R13,
 555         KVM_REG_MIPS_R14,
 556         KVM_REG_MIPS_R15,
 557         KVM_REG_MIPS_R16,
 558         KVM_REG_MIPS_R17,
 559         KVM_REG_MIPS_R18,
 560         KVM_REG_MIPS_R19,
 561         KVM_REG_MIPS_R20,
 562         KVM_REG_MIPS_R21,
 563         KVM_REG_MIPS_R22,
 564         KVM_REG_MIPS_R23,
 565         KVM_REG_MIPS_R24,
 566         KVM_REG_MIPS_R25,
 567         KVM_REG_MIPS_R26,
 568         KVM_REG_MIPS_R27,
 569         KVM_REG_MIPS_R28,
 570         KVM_REG_MIPS_R29,
 571         KVM_REG_MIPS_R30,
 572         KVM_REG_MIPS_R31,
 573
 574 #ifndef CONFIG_CPU_MIPSR6
 575         KVM_REG_MIPS_HI,
 576         KVM_REG_MIPS_LO,
 577 #endif
 578         KVM_REG_MIPS_PC,
 579 };
 580
 581 static u64 kvm_mips_get_one_regs_fpu[] = {
 582         KVM_REG_MIPS_FCR_IR,
 583         KVM_REG_MIPS_FCR_CSR,
 584 };
 585
 586 static u64 kvm_mips_get_one_regs_msa[] = {
 587         KVM_REG_MIPS_MSA_IR,
 588         KVM_REG_MIPS_MSA_CSR,
 589 };
 590
 591 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 592 {
 593         unsigned long ret;
 594
 595         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 596         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 597                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 598                 /* odd doubles */
 599                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 600                         ret += 16;
 601         }
 602         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 603                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 604         ret += kvm_mips_callbacks->num_regs(vcpu);
 605
 606         return ret;
 607 }
 608
 609 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 610 {
 611         u64 index;
 612         unsigned int i;
 613
 614         if (copy_to_user(indices, kvm_mips_get_one_regs,
 615                          sizeof(kvm_mips_get_one_regs)))
 616                 return -EFAULT;
 617         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 618
 619         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 620                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 621                                  sizeof(kvm_mips_get_one_regs_fpu)))
 622                         return -EFAULT;
 623                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 624
 625                 for (i = 0; i < 32; ++i) {
 626                         index = KVM_REG_MIPS_FPR_32(i);
 627                         if (copy_to_user(indices, &index, sizeof(index)))
 628                                 return -EFAULT;
 629                         ++indices;
 630
 631                         /* skip odd doubles if no F64 */
 632                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 633                                 continue;
 634
 635                         index = KVM_REG_MIPS_FPR_64(i);
 636                         if (copy_to_user(indices, &index, sizeof(index)))
 637                                 return -EFAULT;
 638                         ++indices;
 639                 }
 640         }
 641
 642         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 643                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 644                                  sizeof(kvm_mips_get_one_regs_msa)))
 645                         return -EFAULT;
 646                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 647
 648                 for (i = 0; i < 32; ++i) {
 649                         index = KVM_REG_MIPS_VEC_128(i);
 650                         if (copy_to_user(indices, &index, sizeof(index)))
 651                                 return -EFAULT;
 652                         ++indices;
 653                 }
 654         }
 655
 656         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 657 }
 658
 659 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 660                             const struct kvm_one_reg *reg)
 661 {
 662         struct mips_coproc *cop0 = vcpu->arch.cop0;
 663         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 664         int ret;
 665         s64 v;
 666         s64 vs[2];
 667         unsigned int idx;
 668
 669         switch (reg->id) {
 670         /* General purpose registers */
 671         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 672                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 673                 break;
 674 #ifndef CONFIG_CPU_MIPSR6
 675         case KVM_REG_MIPS_HI:
 676                 v = (long)vcpu->arch.hi;
 677                 break;
 678         case KVM_REG_MIPS_LO:
 679                 v = (long)vcpu->arch.lo;
 680                 break;
 681 #endif
 682         case KVM_REG_MIPS_PC:
 683                 v = (long)vcpu->arch.pc;
 684                 break;
 685
 686         /* Floating point registers */
 687         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 688                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 689                         return -EINVAL;
 690                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 691                 /* Odd singles in top of even double when FR=0 */
 692                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 693                         v = get_fpr32(&fpu->fpr[idx], 0);
 694                 else
 695                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 696                 break;
 697         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 698                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 699                         return -EINVAL;
 700                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 701                 /* Can't access odd doubles in FR=0 mode */
 702                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 703                         return -EINVAL;
 704                 v = get_fpr64(&fpu->fpr[idx], 0);
 705                 break;
 706         case KVM_REG_MIPS_FCR_IR:
 707                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 708                         return -EINVAL;
 709                 v = boot_cpu_data.fpu_id;
 710                 break;
 711         case KVM_REG_MIPS_FCR_CSR:
 712                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 713                         return -EINVAL;
 714                 v = fpu->fcr31;
 715                 break;
 716
 717         /* MIPS SIMD Architecture (MSA) registers */
 718         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 719                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 720                         return -EINVAL;
 721                 /* Can't access MSA registers in FR=0 mode */
 722                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 723                         return -EINVAL;
 724                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 725 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 726                 /* least significant byte first */
 727                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 728                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 729 #else
 730                 /* most significant byte first */
 731                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 732                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 733 #endif
 734                 break;
 735         case KVM_REG_MIPS_MSA_IR:
 736                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 737                         return -EINVAL;
 738                 v = boot_cpu_data.msa_id;
 739                 break;
 740         case KVM_REG_MIPS_MSA_CSR:
 741                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 742                         return -EINVAL;
 743                 v = fpu->msacsr;
 744                 break;
 745
 746         /* registers to be handled specially */
 747         default:
 748                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 749                 if (ret)
 750                         return ret;
 751                 break;
 752         }
 753         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 754                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 755
 756                 return put_user(v, uaddr64);
 757         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 758                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 759                 u32 v32 = (u32)v;
 760
 761                 return put_user(v32, uaddr32);
 762         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 763                 void __user *uaddr = (void __user *)(long)reg->addr;
 764
 765                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 766         } else {
 767                 return -EINVAL;
 768         }
 769 }
 770
 771 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 772                             const struct kvm_one_reg *reg)
 773 {
 774         struct mips_coproc *cop0 = vcpu->arch.cop0;
 775         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 776         s64 v;
 777         s64 vs[2];
 778         unsigned int idx;
 779
 780         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 781                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 782
 783                 if (get_user(v, uaddr64) != 0)
 784                         return -EFAULT;
 785         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 786                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 787                 s32 v32;
 788
 789                 if (get_user(v32, uaddr32) != 0)
 790                         return -EFAULT;
 791                 v = (s64)v32;
 792         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 793                 void __user *uaddr = (void __user *)(long)reg->addr;
 794
 795                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 796         } else {
 797                 return -EINVAL;
 798         }
 799
 800         switch (reg->id) {
 801         /* General purpose registers */
 802         case KVM_REG_MIPS_R0:
 803                 /* Silently ignore requests to set $0 */
 804                 break;
 805         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 806                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 807                 break;
 808 #ifndef CONFIG_CPU_MIPSR6
 809         case KVM_REG_MIPS_HI:
 810                 vcpu->arch.hi = v;
 811                 break;
 812         case KVM_REG_MIPS_LO:
 813                 vcpu->arch.lo = v;
 814                 break;
 815 #endif
 816         case KVM_REG_MIPS_PC:
 817                 vcpu->arch.pc = v;
 818                 break;
 819
 820         /* Floating point registers */
 821         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 822                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 823                         return -EINVAL;
 824                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 825                 /* Odd singles in top of even double when FR=0 */
 826                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 827                         set_fpr32(&fpu->fpr[idx], 0, v);
 828                 else
 829                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 830                 break;
 831         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 832                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 833                         return -EINVAL;
 834                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 835                 /* Can't access odd doubles in FR=0 mode */
 836                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 837                         return -EINVAL;
 838                 set_fpr64(&fpu->fpr[idx], 0, v);
 839                 break;
 840         case KVM_REG_MIPS_FCR_IR:
 841                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 842                         return -EINVAL;
 843                 /* Read-only */
 844                 break;
 845         case KVM_REG_MIPS_FCR_CSR:
 846                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 847                         return -EINVAL;
 848                 fpu->fcr31 = v;
 849                 break;
 850
 851         /* MIPS SIMD Architecture (MSA) registers */
 852         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 853                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 854                         return -EINVAL;
 855                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 856 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 857                 /* least significant byte first */
 858                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 859                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 860 #else
 861                 /* most significant byte first */
 862                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 863                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 864 #endif
 865                 break;
 866         case KVM_REG_MIPS_MSA_IR:
 867                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 868                         return -EINVAL;
 869                 /* Read-only */
 870                 break;
 871         case KVM_REG_MIPS_MSA_CSR:
 872                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 873                         return -EINVAL;
 874                 fpu->msacsr = v;
 875                 break;
 876
 877         /* registers to be handled specially */
 878         default:
 879                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 880         }
 881         return 0;
 882 }
 883
 884 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 885                                      struct kvm_enable_cap *cap)
 886 {
 887         int r = 0;
 888
 889         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 890                 return -EINVAL;
 891         if (cap->flags)
 892                 return -EINVAL;
 893         if (cap->args[0])
 894                 return -EINVAL;
 895
 896         switch (cap->cap) {
 897         case KVM_CAP_MIPS_FPU:
 898                 vcpu->arch.fpu_enabled = true;
 899                 break;
 900         case KVM_CAP_MIPS_MSA:
 901                 vcpu->arch.msa_enabled = true;
 902                 break;
 903         default:
 904                 r = -EINVAL;
 905                 break;
 906         }
 907
 908         return r;
 909 }
 910
 911 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 912                                unsigned long arg)
 913 {
 914         struct kvm_vcpu *vcpu = filp->private_data;
 915         void __user *argp = (void __user *)arg;
 916
 917         if (ioctl == KVM_INTERRUPT) {
 918                 struct kvm_mips_interrupt irq;
 919
 920                 if (copy_from_user(&irq, argp, sizeof(irq)))
 921                         return -EFAULT;
 922                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 923                           irq.irq);
 924
 925                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 926         }
 927
 928         return -ENOIOCTLCMD;
 929 }
 930
 931 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 932                          unsigned long arg)
 933 {
 934         struct kvm_vcpu *vcpu = filp->private_data;
 935         void __user *argp = (void __user *)arg;
 936         long r;
 937
 938         vcpu_load(vcpu);
 939
 940         switch (ioctl) {
 941         case KVM_SET_ONE_REG:
 942         case KVM_GET_ONE_REG: {
 943                 struct kvm_one_reg reg;
 944
 945                 r = -EFAULT;
 946                 if (copy_from_user(&reg, argp, sizeof(reg)))
 947                         break;
 948                 if (ioctl == KVM_SET_ONE_REG)
 949                         r = kvm_mips_set_reg(vcpu, &reg);
 950                 else
 951                         r = kvm_mips_get_reg(vcpu, &reg);
 952                 break;
 953         }
 954         case KVM_GET_REG_LIST: {
 955                 struct kvm_reg_list __user *user_list = argp;
 956                 struct kvm_reg_list reg_list;
 957                 unsigned n;
 958
 959                 r = -EFAULT;
 960                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 961                         break;
 962                 n = reg_list.n;
 963                 reg_list.n = kvm_mips_num_regs(vcpu);
 964                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 965                         break;
 966                 r = -E2BIG;
 967                 if (n < reg_list.n)
 968                         break;
 969                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 970                 break;
 971         }
 972         case KVM_ENABLE_CAP: {
 973                 struct kvm_enable_cap cap;
 974
 975                 r = -EFAULT;
 976                 if (copy_from_user(&cap, argp, sizeof(cap)))
 977                         break;
 978                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 979                 break;
 980         }
 981         default:
 982                 r = -ENOIOCTLCMD;
 983         }
 984
 985         vcpu_put(vcpu);
 986         return r;
 987 }
 988
 989 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
 990 {
 991
 992 }
 993
 994 int kvm_arch_flush_remote_tlb(struct kvm *kvm)
 995 {
 996         kvm_mips_callbacks->prepare_flush_shadow(kvm);
 997         return 1;
 998 }
 999
1000 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
1001                                         const struct kvm_memory_slot *memslot)
1002 {
1003         kvm_flush_remote_tlbs(kvm);
1004 }
1005
1006 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1007 {
1008         long r;
1009
1010         switch (ioctl) {
1011         default:
1012                 r = -ENOIOCTLCMD;
1013         }
1014
1015         return r;
1016 }
1017
1018 int kvm_arch_init(void *opaque)
1019 {
1020         if (kvm_mips_callbacks) {
1021                 kvm_err("kvm: module already exists\n");
1022                 return -EEXIST;
1023         }
1024
1025         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1026 }
1027
1028 void kvm_arch_exit(void)
1029 {
1030         kvm_mips_callbacks = NULL;
1031 }
1032
1033 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1034                                   struct kvm_sregs *sregs)
1035 {
1036         return -ENOIOCTLCMD;
1037 }
1038
1039 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1040                                   struct kvm_sregs *sregs)
1041 {
1042         return -ENOIOCTLCMD;
1043 }
1044
1045 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1046 {
1047 }
1048
1049 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1050 {
1051         return -ENOIOCTLCMD;
1052 }
1053
1054 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055 {
1056         return -ENOIOCTLCMD;
1057 }
1058
1059 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1060 {
1061         return VM_FAULT_SIGBUS;
1062 }
1063
1064 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1065 {
1066         int r;
1067
1068         switch (ext) {
1069         case KVM_CAP_ONE_REG:
1070         case KVM_CAP_ENABLE_CAP:
1071         case KVM_CAP_READONLY_MEM:
1072         case KVM_CAP_SYNC_MMU:
1073         case KVM_CAP_IMMEDIATE_EXIT:
1074                 r = 1;
1075                 break;
1076         case KVM_CAP_NR_VCPUS:
1077                 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
1078                 break;
1079         case KVM_CAP_MAX_VCPUS:
1080                 r = KVM_MAX_VCPUS;
1081                 break;
1082         case KVM_CAP_MAX_VCPU_ID:
1083                 r = KVM_MAX_VCPU_IDS;
1084                 break;
1085         case KVM_CAP_MIPS_FPU:
1086                 /* We don't handle systems with inconsistent cpu_has_fpu */
1087                 r = !!raw_cpu_has_fpu;
1088                 break;
1089         case KVM_CAP_MIPS_MSA:
1090                 /*
1091                  * We don't support MSA vector partitioning yet:
1092                  * 1) It would require explicit support which can't be tested
1093                  *    yet due to lack of support in current hardware.
1094                  * 2) It extends the state that would need to be saved/restored
1095                  *    by e.g. QEMU for migration.
1096                  *
1097                  * When vector partitioning hardware becomes available, support
1098                  * could be added by requiring a flag when enabling
1099                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1100                  * to save/restore the appropriate extra state.
1101                  */
1102                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1103                 break;
1104         default:
1105                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1106                 break;
1107         }
1108         return r;
1109 }
1110
1111 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1112 {
1113         return kvm_mips_pending_timer(vcpu) ||
1114                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1115 }
1116
1117 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1118 {
1119         int i;
1120         struct mips_coproc *cop0;
1121
1122         if (!vcpu)
1123                 return -1;
1124
1125         kvm_debug("VCPU Register Dump:\n");
1126         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1127         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1128
1129         for (i = 0; i < 32; i += 4) {
1130                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1131                        vcpu->arch.gprs[i],
1132                        vcpu->arch.gprs[i + 1],
1133                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1134         }
1135         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1136         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1137
1138         cop0 = vcpu->arch.cop0;
1139         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1140                   kvm_read_c0_guest_status(cop0),
1141                   kvm_read_c0_guest_cause(cop0));
1142
1143         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1144
1145         return 0;
1146 }
1147
1148 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1149 {
1150         int i;
1151
1152         vcpu_load(vcpu);
1153
1154         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1155                 vcpu->arch.gprs[i] = regs->gpr[i];
1156         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1157         vcpu->arch.hi = regs->hi;
1158         vcpu->arch.lo = regs->lo;
1159         vcpu->arch.pc = regs->pc;
1160
1161         vcpu_put(vcpu);
1162         return 0;
1163 }
1164
1165 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1166 {
1167         int i;
1168
1169         vcpu_load(vcpu);
1170
1171         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1172                 regs->gpr[i] = vcpu->arch.gprs[i];
1173
1174         regs->hi = vcpu->arch.hi;
1175         regs->lo = vcpu->arch.lo;
1176         regs->pc = vcpu->arch.pc;
1177
1178         vcpu_put(vcpu);
1179         return 0;
1180 }
1181
1182 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1183                                   struct kvm_translation *tr)
1184 {
1185         return 0;
1186 }
1187
1188 static void kvm_mips_set_c0_status(void)
1189 {
1190         u32 status = read_c0_status();
1191
1192         if (cpu_has_dsp)
1193                 status |= (ST0_MX);
1194
1195         write_c0_status(status);
1196         ehb();
1197 }
1198
1199 /*
1200  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1201  */
1202 static int __kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1203 {
1204         struct kvm_run *run = vcpu->run;
1205         u32 cause = vcpu->arch.host_cp0_cause;
1206         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1207         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1208         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1209         enum emulation_result er = EMULATE_DONE;
1210         u32 inst;
1211         int ret = RESUME_GUEST;
1212
1213         vcpu->mode = OUTSIDE_GUEST_MODE;
1214
1215         /* Set a default exit reason */
1216         run->exit_reason = KVM_EXIT_UNKNOWN;
1217         run->ready_for_interrupt_injection = 1;
1218
1219         /*
1220          * Set the appropriate status bits based on host CPU features,
1221          * before we hit the scheduler
1222          */
1223         kvm_mips_set_c0_status();
1224
1225         local_irq_enable();
1226
1227         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1228                         cause, opc, run, vcpu);
1229         trace_kvm_exit(vcpu, exccode);
1230
1231         switch (exccode) {
1232         case EXCCODE_INT:
1233                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1234
1235                 ++vcpu->stat.int_exits;
1236
1237                 if (need_resched())
1238                         cond_resched();
1239
1240                 ret = RESUME_GUEST;
1241                 break;
1242
1243         case EXCCODE_CPU:
1244                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1245
1246                 ++vcpu->stat.cop_unusable_exits;
1247                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1248                 /* XXXKYMA: Might need to return to user space */
1249                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1250                         ret = RESUME_HOST;
1251                 break;
1252
1253         case EXCCODE_MOD:
1254                 ++vcpu->stat.tlbmod_exits;
1255                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1256                 break;
1257
1258         case EXCCODE_TLBS:
1259                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1260                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1261                           badvaddr);
1262
1263                 ++vcpu->stat.tlbmiss_st_exits;
1264                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1265                 break;
1266
1267         case EXCCODE_TLBL:
1268                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1269                           cause, opc, badvaddr);
1270
1271                 ++vcpu->stat.tlbmiss_ld_exits;
1272                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1273                 break;
1274
1275         case EXCCODE_ADES:
1276                 ++vcpu->stat.addrerr_st_exits;
1277                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1278                 break;
1279
1280         case EXCCODE_ADEL:
1281                 ++vcpu->stat.addrerr_ld_exits;
1282                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1283                 break;
1284
1285         case EXCCODE_SYS:
1286                 ++vcpu->stat.syscall_exits;
1287                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1288                 break;
1289
1290         case EXCCODE_RI:
1291                 ++vcpu->stat.resvd_inst_exits;
1292                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1293                 break;
1294
1295         case EXCCODE_BP:
1296                 ++vcpu->stat.break_inst_exits;
1297                 ret = kvm_mips_callbacks->handle_break(vcpu);
1298                 break;
1299
1300         case EXCCODE_TR:
1301                 ++vcpu->stat.trap_inst_exits;
1302                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1303                 break;
1304
1305         case EXCCODE_MSAFPE:
1306                 ++vcpu->stat.msa_fpe_exits;
1307                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1308                 break;
1309
1310         case EXCCODE_FPE:
1311                 ++vcpu->stat.fpe_exits;
1312                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1313                 break;
1314
1315         case EXCCODE_MSADIS:
1316                 ++vcpu->stat.msa_disabled_exits;
1317                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1318                 break;
1319
1320         case EXCCODE_GE:
1321                 /* defer exit accounting to handler */
1322                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1323                 break;
1324
1325         default:
1326                 if (cause & CAUSEF_BD)
1327                         opc += 1;
1328                 inst = 0;
1329                 kvm_get_badinstr(opc, vcpu, &inst);
1330                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1331                         exccode, opc, inst, badvaddr,
1332                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1333                 kvm_arch_vcpu_dump_regs(vcpu);
1334                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1335                 ret = RESUME_HOST;
1336                 break;
1337
1338         }
1339
1340         local_irq_disable();
1341
1342         if (ret == RESUME_GUEST)
1343                 kvm_vz_acquire_htimer(vcpu);
1344
1345         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1346                 kvm_mips_deliver_interrupts(vcpu, cause);
1347
1348         if (!(ret & RESUME_HOST)) {
1349                 /* Only check for signals if not already exiting to userspace */
1350                 if (signal_pending(current)) {
1351                         run->exit_reason = KVM_EXIT_INTR;
1352                         ret = (-EINTR << 2) | RESUME_HOST;
1353                         ++vcpu->stat.signal_exits;
1354                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1355                 }
1356         }
1357
1358         if (ret == RESUME_GUEST) {
1359                 trace_kvm_reenter(vcpu);
1360
1361                 /*
1362                  * Make sure the read of VCPU requests in vcpu_reenter()
1363                  * callback is not reordered ahead of the write to vcpu->mode,
1364                  * or we could miss a TLB flush request while the requester sees
1365                  * the VCPU as outside of guest mode and not needing an IPI.
1366                  */
1367                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1368
1369                 kvm_mips_callbacks->vcpu_reenter(vcpu);
1370
1371                 /*
1372                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1373                  * is live), restore FCR31 / MSACSR.
1374                  *
1375                  * This should be before returning to the guest exception
1376                  * vector, as it may well cause an [MSA] FP exception if there
1377                  * are pending exception bits unmasked. (see
1378                  * kvm_mips_csr_die_notifier() for how that is handled).
1379                  */
1380                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1381                     read_c0_status() & ST0_CU1)
1382                         __kvm_restore_fcsr(&vcpu->arch);
1383
1384                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1385                     read_c0_config5() & MIPS_CONF5_MSAEN)
1386                         __kvm_restore_msacsr(&vcpu->arch);
1387         }
1388         return ret;
1389 }
1390
1391 int noinstr kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1392 {
1393         int ret;
1394
1395         guest_state_exit_irqoff();
1396         ret = __kvm_mips_handle_exit(vcpu);
1397         guest_state_enter_irqoff();
1398
1399         return ret;
1400 }
1401
1402 /* Enable FPU for guest and restore context */
1403 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1404 {
1405         struct mips_coproc *cop0 = vcpu->arch.cop0;
1406         unsigned int sr, cfg5;
1407
1408         preempt_disable();
1409
1410         sr = kvm_read_c0_guest_status(cop0);
1411
1412         /*
1413          * If MSA state is already live, it is undefined how it interacts with
1414          * FR=0 FPU state, and we don't want to hit reserved instruction
1415          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1416          * play it safe and save it first.
1417          */
1418         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1419             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1420                 kvm_lose_fpu(vcpu);
1421
1422         /*
1423          * Enable FPU for guest
1424          * We set FR and FRE according to guest context
1425          */
1426         change_c0_status(ST0_CU1 | ST0_FR, sr);
1427         if (cpu_has_fre) {
1428                 cfg5 = kvm_read_c0_guest_config5(cop0);
1429                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1430         }
1431         enable_fpu_hazard();
1432
1433         /* If guest FPU state not active, restore it now */
1434         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1435                 __kvm_restore_fpu(&vcpu->arch);
1436                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1437                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1438         } else {
1439                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1440         }
1441
1442         preempt_enable();
1443 }
1444
1445 #ifdef CONFIG_CPU_HAS_MSA
1446 /* Enable MSA for guest and restore context */
1447 void kvm_own_msa(struct kvm_vcpu *vcpu)
1448 {
1449         struct mips_coproc *cop0 = vcpu->arch.cop0;
1450         unsigned int sr, cfg5;
1451
1452         preempt_disable();
1453
1454         /*
1455          * Enable FPU if enabled in guest, since we're restoring FPU context
1456          * anyway. We set FR and FRE according to guest context.
1457          */
1458         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1459                 sr = kvm_read_c0_guest_status(cop0);
1460
1461                 /*
1462                  * If FR=0 FPU state is already live, it is undefined how it
1463                  * interacts with MSA state, so play it safe and save it first.
1464                  */
1465                 if (!(sr & ST0_FR) &&
1466                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1467                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1468                         kvm_lose_fpu(vcpu);
1469
1470                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1471                 if (sr & ST0_CU1 && cpu_has_fre) {
1472                         cfg5 = kvm_read_c0_guest_config5(cop0);
1473                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1474                 }
1475         }
1476
1477         /* Enable MSA for guest */
1478         set_c0_config5(MIPS_CONF5_MSAEN);
1479         enable_fpu_hazard();
1480
1481         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1482         case KVM_MIPS_AUX_FPU:
1483                 /*
1484                  * Guest FPU state already loaded, only restore upper MSA state
1485                  */
1486                 __kvm_restore_msa_upper(&vcpu->arch);
1487                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1488                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1489                 break;
1490         case 0:
1491                 /* Neither FPU or MSA already active, restore full MSA state */
1492                 __kvm_restore_msa(&vcpu->arch);
1493                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1494                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1495                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1496                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1497                               KVM_TRACE_AUX_FPU_MSA);
1498                 break;
1499         default:
1500                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1501                 break;
1502         }
1503
1504         preempt_enable();
1505 }
1506 #endif
1507
1508 /* Drop FPU & MSA without saving it */
1509 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1510 {
1511         preempt_disable();
1512         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1513                 disable_msa();
1514                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1515                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1516         }
1517         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1518                 clear_c0_status(ST0_CU1 | ST0_FR);
1519                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1520                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1521         }
1522         preempt_enable();
1523 }
1524
1525 /* Save and disable FPU & MSA */
1526 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1527 {
1528         /*
1529          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1530          * is disabled in guest context (software), but the register state in
1531          * the hardware may still be in use.
1532          * This is why we explicitly re-enable the hardware before saving.
1533          */
1534
1535         preempt_disable();
1536         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1537                 __kvm_save_msa(&vcpu->arch);
1538                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1539
1540                 /* Disable MSA & FPU */
1541                 disable_msa();
1542                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1543                         clear_c0_status(ST0_CU1 | ST0_FR);
1544                         disable_fpu_hazard();
1545                 }
1546                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1547         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1548                 __kvm_save_fpu(&vcpu->arch);
1549                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1550                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1551
1552                 /* Disable FPU */
1553                 clear_c0_status(ST0_CU1 | ST0_FR);
1554                 disable_fpu_hazard();
1555         }
1556         preempt_enable();
1557 }
1558
1559 /*
1560  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1561  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1562  * exception if cause bits are set in the value being written.
1563  */
1564 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1565                                    unsigned long cmd, void *ptr)
1566 {
1567         struct die_args *args = (struct die_args *)ptr;
1568         struct pt_regs *regs = args->regs;
1569         unsigned long pc;
1570
1571         /* Only interested in FPE and MSAFPE */
1572         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1573                 return NOTIFY_DONE;
1574
1575         /* Return immediately if guest context isn't active */
1576         if (!(current->flags & PF_VCPU))
1577                 return NOTIFY_DONE;
1578
1579         /* Should never get here from user mode */
1580         BUG_ON(user_mode(regs));
1581
1582         pc = instruction_pointer(regs);
1583         switch (cmd) {
1584         case DIE_FP:
1585                 /* match 2nd instruction in __kvm_restore_fcsr */
1586                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1587                         return NOTIFY_DONE;
1588                 break;
1589         case DIE_MSAFP:
1590                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1591                 if (!cpu_has_msa ||
1592                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1593                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1594                         return NOTIFY_DONE;
1595                 break;
1596         }
1597
1598         /* Move PC forward a little and continue executing */
1599         instruction_pointer(regs) += 4;
1600
1601         return NOTIFY_STOP;
1602 }
1603
1604 static struct notifier_block kvm_mips_csr_die_notifier = {
1605         .notifier_call = kvm_mips_csr_die_notify,
1606 };
1607
1608 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1609         [MIPS_EXC_INT_TIMER] = C_IRQ5,
1610         [MIPS_EXC_INT_IO_1]  = C_IRQ0,
1611         [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1612         [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1613 };
1614
1615 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1616         [MIPS_EXC_INT_TIMER] = C_IRQ5,
1617         [MIPS_EXC_INT_IO_1]  = C_IRQ0,
1618         [MIPS_EXC_INT_IO_2]  = C_IRQ1,
1619         [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1620 };
1621
1622 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1623
1624 u32 kvm_irq_to_priority(u32 irq)
1625 {
1626         int i;
1627
1628         for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1629                 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1630                         return i;
1631         }
1632
1633         return MIPS_EXC_MAX;
1634 }
1635
1636 static int __init kvm_mips_init(void)
1637 {
1638         int ret;
1639
1640         if (cpu_has_mmid) {
1641                 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1642                 return -EOPNOTSUPP;
1643         }
1644
1645         ret = kvm_mips_entry_setup();
1646         if (ret)
1647                 return ret;
1648
1649         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1650
1651         if (ret)
1652                 return ret;
1653
1654         if (boot_cpu_type() == CPU_LOONGSON64)
1655                 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1656
1657         register_die_notifier(&kvm_mips_csr_die_notifier);
1658
1659         return 0;
1660 }
1661
1662 static void __exit kvm_mips_exit(void)
1663 {
1664         kvm_exit();
1665
1666         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1667 }
1668
1669 module_init(kvm_mips_init);
1670 module_exit(kvm_mips_exit);
1671
1672 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);