2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
19 #include <linux/bootmem.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
26 #include <linux/kvm_host.h>
28 #include "interrupt.h"
31 #define CREATE_TRACE_POINTS
35 #define VECTORSPACING 0x100 /* for EI/VI mode */
38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
39 struct kvm_stats_debugfs_item debugfs_entries[] = {
40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
69 for_each_possible_cpu(i) {
70 vcpu->arch.guest_kernel_asid[i] = 0;
71 vcpu->arch.guest_user_asid[i] = 0;
78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
79 * Config7, so we are "runnable" if interrupts are pending
81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
83 return !!(vcpu->arch.pending_exceptions);
86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
91 int kvm_arch_hardware_enable(void)
96 int kvm_arch_hardware_setup(void)
101 void kvm_arch_check_processor_compat(void *rtn)
106 static void kvm_mips_init_tlbs(struct kvm *kvm)
111 * Add a wired entry to the TLB, it is used to map the commpage to
114 wired = read_c0_wired();
115 write_c0_wired(wired + 1);
117 kvm->arch.commpage_tlb = wired;
119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
120 kvm->arch.commpage_tlb);
123 static void kvm_mips_init_vm_percpu(void *arg)
125 struct kvm *kvm = (struct kvm *)arg;
127 kvm_mips_init_tlbs(kvm);
128 kvm_mips_callbacks->vm_init(kvm);
132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
134 if (atomic_inc_return(&kvm_mips_instance) == 1) {
135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
143 bool kvm_arch_has_vcpu_debugfs(void)
148 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
153 void kvm_mips_free_vcpus(struct kvm *kvm)
156 struct kvm_vcpu *vcpu;
158 /* Put the pages we reserved for the guest pmap */
159 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
160 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
161 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
163 kfree(kvm->arch.guest_pmap);
165 kvm_for_each_vcpu(i, vcpu, kvm) {
166 kvm_arch_vcpu_free(vcpu);
169 mutex_lock(&kvm->lock);
171 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
172 kvm->vcpus[i] = NULL;
174 atomic_set(&kvm->online_vcpus, 0);
176 mutex_unlock(&kvm->lock);
179 static void kvm_mips_uninit_tlbs(void *arg)
181 /* Restore wired count */
184 /* Clear out all the TLBs */
185 kvm_local_flush_tlb_all();
188 void kvm_arch_destroy_vm(struct kvm *kvm)
190 kvm_mips_free_vcpus(kvm);
192 /* If this is the last instance, restore wired count */
193 if (atomic_dec_return(&kvm_mips_instance) == 0) {
194 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
196 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
200 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
206 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
207 unsigned long npages)
212 int kvm_arch_prepare_memory_region(struct kvm *kvm,
213 struct kvm_memory_slot *memslot,
214 const struct kvm_userspace_memory_region *mem,
215 enum kvm_mr_change change)
220 void kvm_arch_commit_memory_region(struct kvm *kvm,
221 const struct kvm_userspace_memory_region *mem,
222 const struct kvm_memory_slot *old,
223 const struct kvm_memory_slot *new,
224 enum kvm_mr_change change)
226 unsigned long npages = 0;
229 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
230 __func__, kvm, mem->slot, mem->guest_phys_addr,
231 mem->memory_size, mem->userspace_addr);
233 /* Setup Guest PMAP table */
234 if (!kvm->arch.guest_pmap) {
236 npages = mem->memory_size >> PAGE_SHIFT;
239 kvm->arch.guest_pmap_npages = npages;
240 kvm->arch.guest_pmap =
241 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
243 if (!kvm->arch.guest_pmap) {
244 kvm_err("Failed to allocate guest PMAP\n");
248 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
249 npages, kvm->arch.guest_pmap);
251 /* Now setup the page table */
252 for (i = 0; i < npages; i++)
253 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
258 static inline void dump_handler(const char *symbol, void *start, void *end)
262 pr_debug("LEAF(%s)\n", symbol);
264 pr_debug("\t.set push\n");
265 pr_debug("\t.set noreorder\n");
267 for (p = start; p < (u32 *)end; ++p)
268 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
270 pr_debug("\t.set\tpop\n");
272 pr_debug("\tEND(%s)\n", symbol);
275 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
278 void *gebase, *p, *handler;
281 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
288 err = kvm_vcpu_init(vcpu, kvm, id);
293 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
296 * Allocate space for host mode exception handlers that handle
299 if (cpu_has_veic || cpu_has_vint)
300 size = 0x200 + VECTORSPACING * 64;
304 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
310 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
311 ALIGN(size, PAGE_SIZE), gebase);
314 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
315 * limits us to the low 512MB of physical address space. If the memory
316 * we allocate is out of range, just give up now.
318 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
319 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
322 goto out_free_gebase;
326 vcpu->arch.guest_ebase = gebase;
328 /* Build guest exception vectors dynamically in unmapped memory */
329 handler = gebase + 0x2000;
331 /* TLB Refill, EXL = 0 */
332 kvm_mips_build_exception(gebase, handler);
334 /* General Exception Entry point */
335 kvm_mips_build_exception(gebase + 0x180, handler);
337 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
338 for (i = 0; i < 8; i++) {
339 kvm_debug("L1 Vectored handler @ %p\n",
340 gebase + 0x200 + (i * VECTORSPACING));
341 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
345 /* General exit handler */
347 p = kvm_mips_build_exit(p);
349 /* Guest entry routine */
350 vcpu->arch.vcpu_run = p;
351 p = kvm_mips_build_vcpu_run(p);
353 /* Dump the generated code */
354 pr_debug("#include <asm/asm.h>\n");
355 pr_debug("#include <asm/regdef.h>\n");
357 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
358 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
359 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
361 /* Invalidate the icache for these ranges */
362 local_flush_icache_range((unsigned long)gebase,
363 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
366 * Allocate comm page for guest kernel, a TLB will be reserved for
367 * mapping GVA @ 0xFFFF8000 to this page
369 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
371 if (!vcpu->arch.kseg0_commpage) {
373 goto out_free_gebase;
376 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
377 kvm_mips_commpage_init(vcpu);
380 vcpu->arch.last_sched_cpu = -1;
382 /* Start off the timer */
383 kvm_mips_init_count(vcpu);
391 kvm_vcpu_uninit(vcpu);
400 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
402 hrtimer_cancel(&vcpu->arch.comparecount_timer);
404 kvm_vcpu_uninit(vcpu);
406 kvm_mips_dump_stats(vcpu);
408 kfree(vcpu->arch.guest_ebase);
409 kfree(vcpu->arch.kseg0_commpage);
413 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
415 kvm_arch_vcpu_free(vcpu);
418 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
419 struct kvm_guest_debug *dbg)
424 /* Must be called with preemption disabled, just before entering guest */
425 static void kvm_mips_check_asids(struct kvm_vcpu *vcpu)
427 struct mips_coproc *cop0 = vcpu->arch.cop0;
428 int cpu = smp_processor_id();
432 * Lazy host ASID regeneration for guest user mode.
433 * If the guest ASID has changed since the last guest usermode
434 * execution, regenerate the host ASID so as to invalidate stale TLB
437 if (!KVM_GUEST_KERNEL_MODE(vcpu)) {
438 gasid = kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID;
439 if (gasid != vcpu->arch.last_user_gasid) {
440 kvm_get_new_mmu_context(&vcpu->arch.guest_user_mm, cpu,
442 vcpu->arch.guest_user_asid[cpu] =
443 vcpu->arch.guest_user_mm.context.asid[cpu];
444 vcpu->arch.last_user_gasid = gasid;
449 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
454 if (vcpu->sigset_active)
455 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
457 if (vcpu->mmio_needed) {
458 if (!vcpu->mmio_is_write)
459 kvm_mips_complete_mmio_load(vcpu, run);
460 vcpu->mmio_needed = 0;
466 /* Check if we have any exceptions/interrupts pending */
467 kvm_mips_deliver_interrupts(vcpu,
468 kvm_read_c0_guest_cause(vcpu->arch.cop0));
470 guest_enter_irqoff();
472 /* Disable hardware page table walking while in guest */
475 trace_kvm_enter(vcpu);
477 kvm_mips_check_asids(vcpu);
479 r = vcpu->arch.vcpu_run(run, vcpu);
482 /* Re-enable HTW before enabling interrupts */
488 if (vcpu->sigset_active)
489 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
494 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
495 struct kvm_mips_interrupt *irq)
497 int intr = (int)irq->irq;
498 struct kvm_vcpu *dvcpu = NULL;
500 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
501 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
507 dvcpu = vcpu->kvm->vcpus[irq->cpu];
509 if (intr == 2 || intr == 3 || intr == 4) {
510 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
512 } else if (intr == -2 || intr == -3 || intr == -4) {
513 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
515 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
520 dvcpu->arch.wait = 0;
522 if (swait_active(&dvcpu->wq))
523 swake_up(&dvcpu->wq);
528 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
529 struct kvm_mp_state *mp_state)
534 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
535 struct kvm_mp_state *mp_state)
540 static u64 kvm_mips_get_one_regs[] = {
574 #ifndef CONFIG_CPU_MIPSR6
580 KVM_REG_MIPS_CP0_INDEX,
581 KVM_REG_MIPS_CP0_CONTEXT,
582 KVM_REG_MIPS_CP0_USERLOCAL,
583 KVM_REG_MIPS_CP0_PAGEMASK,
584 KVM_REG_MIPS_CP0_WIRED,
585 KVM_REG_MIPS_CP0_HWRENA,
586 KVM_REG_MIPS_CP0_BADVADDR,
587 KVM_REG_MIPS_CP0_COUNT,
588 KVM_REG_MIPS_CP0_ENTRYHI,
589 KVM_REG_MIPS_CP0_COMPARE,
590 KVM_REG_MIPS_CP0_STATUS,
591 KVM_REG_MIPS_CP0_CAUSE,
592 KVM_REG_MIPS_CP0_EPC,
593 KVM_REG_MIPS_CP0_PRID,
594 KVM_REG_MIPS_CP0_CONFIG,
595 KVM_REG_MIPS_CP0_CONFIG1,
596 KVM_REG_MIPS_CP0_CONFIG2,
597 KVM_REG_MIPS_CP0_CONFIG3,
598 KVM_REG_MIPS_CP0_CONFIG4,
599 KVM_REG_MIPS_CP0_CONFIG5,
600 KVM_REG_MIPS_CP0_CONFIG7,
601 KVM_REG_MIPS_CP0_ERROREPC,
603 KVM_REG_MIPS_COUNT_CTL,
604 KVM_REG_MIPS_COUNT_RESUME,
605 KVM_REG_MIPS_COUNT_HZ,
608 static u64 kvm_mips_get_one_regs_fpu[] = {
610 KVM_REG_MIPS_FCR_CSR,
613 static u64 kvm_mips_get_one_regs_msa[] = {
615 KVM_REG_MIPS_MSA_CSR,
618 static u64 kvm_mips_get_one_regs_kscratch[] = {
619 KVM_REG_MIPS_CP0_KSCRATCH1,
620 KVM_REG_MIPS_CP0_KSCRATCH2,
621 KVM_REG_MIPS_CP0_KSCRATCH3,
622 KVM_REG_MIPS_CP0_KSCRATCH4,
623 KVM_REG_MIPS_CP0_KSCRATCH5,
624 KVM_REG_MIPS_CP0_KSCRATCH6,
627 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
631 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
632 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
633 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
635 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
638 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
639 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
640 ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
641 ret += kvm_mips_callbacks->num_regs(vcpu);
646 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
651 if (copy_to_user(indices, kvm_mips_get_one_regs,
652 sizeof(kvm_mips_get_one_regs)))
654 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
656 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
657 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
658 sizeof(kvm_mips_get_one_regs_fpu)))
660 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
662 for (i = 0; i < 32; ++i) {
663 index = KVM_REG_MIPS_FPR_32(i);
664 if (copy_to_user(indices, &index, sizeof(index)))
668 /* skip odd doubles if no F64 */
669 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
672 index = KVM_REG_MIPS_FPR_64(i);
673 if (copy_to_user(indices, &index, sizeof(index)))
679 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
680 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
681 sizeof(kvm_mips_get_one_regs_msa)))
683 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
685 for (i = 0; i < 32; ++i) {
686 index = KVM_REG_MIPS_VEC_128(i);
687 if (copy_to_user(indices, &index, sizeof(index)))
693 for (i = 0; i < 6; ++i) {
694 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
697 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
698 sizeof(kvm_mips_get_one_regs_kscratch[i])))
703 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
706 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
707 const struct kvm_one_reg *reg)
709 struct mips_coproc *cop0 = vcpu->arch.cop0;
710 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
717 /* General purpose registers */
718 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
719 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
721 #ifndef CONFIG_CPU_MIPSR6
722 case KVM_REG_MIPS_HI:
723 v = (long)vcpu->arch.hi;
725 case KVM_REG_MIPS_LO:
726 v = (long)vcpu->arch.lo;
729 case KVM_REG_MIPS_PC:
730 v = (long)vcpu->arch.pc;
733 /* Floating point registers */
734 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
735 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
737 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
738 /* Odd singles in top of even double when FR=0 */
739 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
740 v = get_fpr32(&fpu->fpr[idx], 0);
742 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
744 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
745 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
747 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
748 /* Can't access odd doubles in FR=0 mode */
749 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
751 v = get_fpr64(&fpu->fpr[idx], 0);
753 case KVM_REG_MIPS_FCR_IR:
754 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
756 v = boot_cpu_data.fpu_id;
758 case KVM_REG_MIPS_FCR_CSR:
759 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
764 /* MIPS SIMD Architecture (MSA) registers */
765 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
766 if (!kvm_mips_guest_has_msa(&vcpu->arch))
768 /* Can't access MSA registers in FR=0 mode */
769 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
771 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
772 #ifdef CONFIG_CPU_LITTLE_ENDIAN
773 /* least significant byte first */
774 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
775 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
777 /* most significant byte first */
778 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
779 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
782 case KVM_REG_MIPS_MSA_IR:
783 if (!kvm_mips_guest_has_msa(&vcpu->arch))
785 v = boot_cpu_data.msa_id;
787 case KVM_REG_MIPS_MSA_CSR:
788 if (!kvm_mips_guest_has_msa(&vcpu->arch))
793 /* Co-processor 0 registers */
794 case KVM_REG_MIPS_CP0_INDEX:
795 v = (long)kvm_read_c0_guest_index(cop0);
797 case KVM_REG_MIPS_CP0_CONTEXT:
798 v = (long)kvm_read_c0_guest_context(cop0);
800 case KVM_REG_MIPS_CP0_USERLOCAL:
801 v = (long)kvm_read_c0_guest_userlocal(cop0);
803 case KVM_REG_MIPS_CP0_PAGEMASK:
804 v = (long)kvm_read_c0_guest_pagemask(cop0);
806 case KVM_REG_MIPS_CP0_WIRED:
807 v = (long)kvm_read_c0_guest_wired(cop0);
809 case KVM_REG_MIPS_CP0_HWRENA:
810 v = (long)kvm_read_c0_guest_hwrena(cop0);
812 case KVM_REG_MIPS_CP0_BADVADDR:
813 v = (long)kvm_read_c0_guest_badvaddr(cop0);
815 case KVM_REG_MIPS_CP0_ENTRYHI:
816 v = (long)kvm_read_c0_guest_entryhi(cop0);
818 case KVM_REG_MIPS_CP0_COMPARE:
819 v = (long)kvm_read_c0_guest_compare(cop0);
821 case KVM_REG_MIPS_CP0_STATUS:
822 v = (long)kvm_read_c0_guest_status(cop0);
824 case KVM_REG_MIPS_CP0_CAUSE:
825 v = (long)kvm_read_c0_guest_cause(cop0);
827 case KVM_REG_MIPS_CP0_EPC:
828 v = (long)kvm_read_c0_guest_epc(cop0);
830 case KVM_REG_MIPS_CP0_PRID:
831 v = (long)kvm_read_c0_guest_prid(cop0);
833 case KVM_REG_MIPS_CP0_CONFIG:
834 v = (long)kvm_read_c0_guest_config(cop0);
836 case KVM_REG_MIPS_CP0_CONFIG1:
837 v = (long)kvm_read_c0_guest_config1(cop0);
839 case KVM_REG_MIPS_CP0_CONFIG2:
840 v = (long)kvm_read_c0_guest_config2(cop0);
842 case KVM_REG_MIPS_CP0_CONFIG3:
843 v = (long)kvm_read_c0_guest_config3(cop0);
845 case KVM_REG_MIPS_CP0_CONFIG4:
846 v = (long)kvm_read_c0_guest_config4(cop0);
848 case KVM_REG_MIPS_CP0_CONFIG5:
849 v = (long)kvm_read_c0_guest_config5(cop0);
851 case KVM_REG_MIPS_CP0_CONFIG7:
852 v = (long)kvm_read_c0_guest_config7(cop0);
854 case KVM_REG_MIPS_CP0_ERROREPC:
855 v = (long)kvm_read_c0_guest_errorepc(cop0);
857 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
858 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
859 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
863 v = (long)kvm_read_c0_guest_kscratch1(cop0);
866 v = (long)kvm_read_c0_guest_kscratch2(cop0);
869 v = (long)kvm_read_c0_guest_kscratch3(cop0);
872 v = (long)kvm_read_c0_guest_kscratch4(cop0);
875 v = (long)kvm_read_c0_guest_kscratch5(cop0);
878 v = (long)kvm_read_c0_guest_kscratch6(cop0);
882 /* registers to be handled specially */
884 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
889 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
890 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
892 return put_user(v, uaddr64);
893 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
894 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
897 return put_user(v32, uaddr32);
898 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
899 void __user *uaddr = (void __user *)(long)reg->addr;
901 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
907 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
908 const struct kvm_one_reg *reg)
910 struct mips_coproc *cop0 = vcpu->arch.cop0;
911 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
916 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
917 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
919 if (get_user(v, uaddr64) != 0)
921 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
922 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
925 if (get_user(v32, uaddr32) != 0)
928 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
929 void __user *uaddr = (void __user *)(long)reg->addr;
931 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
937 /* General purpose registers */
938 case KVM_REG_MIPS_R0:
939 /* Silently ignore requests to set $0 */
941 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
942 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
944 #ifndef CONFIG_CPU_MIPSR6
945 case KVM_REG_MIPS_HI:
948 case KVM_REG_MIPS_LO:
952 case KVM_REG_MIPS_PC:
956 /* Floating point registers */
957 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
958 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
960 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
961 /* Odd singles in top of even double when FR=0 */
962 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
963 set_fpr32(&fpu->fpr[idx], 0, v);
965 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
967 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
968 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
970 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
971 /* Can't access odd doubles in FR=0 mode */
972 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
974 set_fpr64(&fpu->fpr[idx], 0, v);
976 case KVM_REG_MIPS_FCR_IR:
977 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
981 case KVM_REG_MIPS_FCR_CSR:
982 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
987 /* MIPS SIMD Architecture (MSA) registers */
988 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
989 if (!kvm_mips_guest_has_msa(&vcpu->arch))
991 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
992 #ifdef CONFIG_CPU_LITTLE_ENDIAN
993 /* least significant byte first */
994 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
995 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
997 /* most significant byte first */
998 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
999 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
1002 case KVM_REG_MIPS_MSA_IR:
1003 if (!kvm_mips_guest_has_msa(&vcpu->arch))
1007 case KVM_REG_MIPS_MSA_CSR:
1008 if (!kvm_mips_guest_has_msa(&vcpu->arch))
1013 /* Co-processor 0 registers */
1014 case KVM_REG_MIPS_CP0_INDEX:
1015 kvm_write_c0_guest_index(cop0, v);
1017 case KVM_REG_MIPS_CP0_CONTEXT:
1018 kvm_write_c0_guest_context(cop0, v);
1020 case KVM_REG_MIPS_CP0_USERLOCAL:
1021 kvm_write_c0_guest_userlocal(cop0, v);
1023 case KVM_REG_MIPS_CP0_PAGEMASK:
1024 kvm_write_c0_guest_pagemask(cop0, v);
1026 case KVM_REG_MIPS_CP0_WIRED:
1027 kvm_write_c0_guest_wired(cop0, v);
1029 case KVM_REG_MIPS_CP0_HWRENA:
1030 kvm_write_c0_guest_hwrena(cop0, v);
1032 case KVM_REG_MIPS_CP0_BADVADDR:
1033 kvm_write_c0_guest_badvaddr(cop0, v);
1035 case KVM_REG_MIPS_CP0_ENTRYHI:
1036 kvm_write_c0_guest_entryhi(cop0, v);
1038 case KVM_REG_MIPS_CP0_STATUS:
1039 kvm_write_c0_guest_status(cop0, v);
1041 case KVM_REG_MIPS_CP0_EPC:
1042 kvm_write_c0_guest_epc(cop0, v);
1044 case KVM_REG_MIPS_CP0_PRID:
1045 kvm_write_c0_guest_prid(cop0, v);
1047 case KVM_REG_MIPS_CP0_ERROREPC:
1048 kvm_write_c0_guest_errorepc(cop0, v);
1050 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
1051 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
1052 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
1056 kvm_write_c0_guest_kscratch1(cop0, v);
1059 kvm_write_c0_guest_kscratch2(cop0, v);
1062 kvm_write_c0_guest_kscratch3(cop0, v);
1065 kvm_write_c0_guest_kscratch4(cop0, v);
1068 kvm_write_c0_guest_kscratch5(cop0, v);
1071 kvm_write_c0_guest_kscratch6(cop0, v);
1075 /* registers to be handled specially */
1077 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1082 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1083 struct kvm_enable_cap *cap)
1087 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1095 case KVM_CAP_MIPS_FPU:
1096 vcpu->arch.fpu_enabled = true;
1098 case KVM_CAP_MIPS_MSA:
1099 vcpu->arch.msa_enabled = true;
1109 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1112 struct kvm_vcpu *vcpu = filp->private_data;
1113 void __user *argp = (void __user *)arg;
1117 case KVM_SET_ONE_REG:
1118 case KVM_GET_ONE_REG: {
1119 struct kvm_one_reg reg;
1121 if (copy_from_user(®, argp, sizeof(reg)))
1123 if (ioctl == KVM_SET_ONE_REG)
1124 return kvm_mips_set_reg(vcpu, ®);
1126 return kvm_mips_get_reg(vcpu, ®);
1128 case KVM_GET_REG_LIST: {
1129 struct kvm_reg_list __user *user_list = argp;
1130 struct kvm_reg_list reg_list;
1133 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
1136 reg_list.n = kvm_mips_num_regs(vcpu);
1137 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
1141 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1144 /* Treat the NMI as a CPU reset */
1145 r = kvm_mips_reset_vcpu(vcpu);
1149 struct kvm_mips_interrupt irq;
1152 if (copy_from_user(&irq, argp, sizeof(irq)))
1155 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1158 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1161 case KVM_ENABLE_CAP: {
1162 struct kvm_enable_cap cap;
1165 if (copy_from_user(&cap, argp, sizeof(cap)))
1167 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1178 /* Get (and clear) the dirty memory log for a memory slot. */
1179 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1181 struct kvm_memslots *slots;
1182 struct kvm_memory_slot *memslot;
1183 unsigned long ga, ga_end;
1188 mutex_lock(&kvm->slots_lock);
1190 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1194 /* If nothing is dirty, don't bother messing with page tables. */
1196 slots = kvm_memslots(kvm);
1197 memslot = id_to_memslot(slots, log->slot);
1199 ga = memslot->base_gfn << PAGE_SHIFT;
1200 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1202 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1205 n = kvm_dirty_bitmap_bytes(memslot);
1206 memset(memslot->dirty_bitmap, 0, n);
1211 mutex_unlock(&kvm->slots_lock);
1216 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1228 int kvm_arch_init(void *opaque)
1230 if (kvm_mips_callbacks) {
1231 kvm_err("kvm: module already exists\n");
1235 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1238 void kvm_arch_exit(void)
1240 kvm_mips_callbacks = NULL;
1243 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1244 struct kvm_sregs *sregs)
1246 return -ENOIOCTLCMD;
1249 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1250 struct kvm_sregs *sregs)
1252 return -ENOIOCTLCMD;
1255 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1259 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1261 return -ENOIOCTLCMD;
1264 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1266 return -ENOIOCTLCMD;
1269 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1271 return VM_FAULT_SIGBUS;
1274 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1279 case KVM_CAP_ONE_REG:
1280 case KVM_CAP_ENABLE_CAP:
1283 case KVM_CAP_COALESCED_MMIO:
1284 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1286 case KVM_CAP_MIPS_FPU:
1287 /* We don't handle systems with inconsistent cpu_has_fpu */
1288 r = !!raw_cpu_has_fpu;
1290 case KVM_CAP_MIPS_MSA:
1292 * We don't support MSA vector partitioning yet:
1293 * 1) It would require explicit support which can't be tested
1294 * yet due to lack of support in current hardware.
1295 * 2) It extends the state that would need to be saved/restored
1296 * by e.g. QEMU for migration.
1298 * When vector partitioning hardware becomes available, support
1299 * could be added by requiring a flag when enabling
1300 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1301 * to save/restore the appropriate extra state.
1303 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1312 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1314 return kvm_mips_pending_timer(vcpu);
1317 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1320 struct mips_coproc *cop0;
1325 kvm_debug("VCPU Register Dump:\n");
1326 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1327 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1329 for (i = 0; i < 32; i += 4) {
1330 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1332 vcpu->arch.gprs[i + 1],
1333 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1335 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1336 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1338 cop0 = vcpu->arch.cop0;
1339 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1340 kvm_read_c0_guest_status(cop0),
1341 kvm_read_c0_guest_cause(cop0));
1343 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1348 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1352 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1353 vcpu->arch.gprs[i] = regs->gpr[i];
1354 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1355 vcpu->arch.hi = regs->hi;
1356 vcpu->arch.lo = regs->lo;
1357 vcpu->arch.pc = regs->pc;
1362 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1366 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1367 regs->gpr[i] = vcpu->arch.gprs[i];
1369 regs->hi = vcpu->arch.hi;
1370 regs->lo = vcpu->arch.lo;
1371 regs->pc = vcpu->arch.pc;
1376 static void kvm_mips_comparecount_func(unsigned long data)
1378 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1380 kvm_mips_callbacks->queue_timer_int(vcpu);
1382 vcpu->arch.wait = 0;
1383 if (swait_active(&vcpu->wq))
1384 swake_up(&vcpu->wq);
1387 /* low level hrtimer wake routine */
1388 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1390 struct kvm_vcpu *vcpu;
1392 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1393 kvm_mips_comparecount_func((unsigned long) vcpu);
1394 return kvm_mips_count_timeout(vcpu);
1397 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1399 kvm_mips_callbacks->vcpu_init(vcpu);
1400 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1402 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1406 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1407 struct kvm_translation *tr)
1412 /* Initial guest state */
1413 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1415 return kvm_mips_callbacks->vcpu_setup(vcpu);
1418 static void kvm_mips_set_c0_status(void)
1420 u32 status = read_c0_status();
1425 write_c0_status(status);
1430 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1432 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1434 u32 cause = vcpu->arch.host_cp0_cause;
1435 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1436 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1437 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1438 enum emulation_result er = EMULATE_DONE;
1439 int ret = RESUME_GUEST;
1441 /* re-enable HTW before enabling interrupts */
1444 /* Set a default exit reason */
1445 run->exit_reason = KVM_EXIT_UNKNOWN;
1446 run->ready_for_interrupt_injection = 1;
1449 * Set the appropriate status bits based on host CPU features,
1450 * before we hit the scheduler
1452 kvm_mips_set_c0_status();
1456 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1457 cause, opc, run, vcpu);
1458 trace_kvm_exit(vcpu, exccode);
1461 * Do a privilege check, if in UM most of these exit conditions end up
1462 * causing an exception to be delivered to the Guest Kernel
1464 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1465 if (er == EMULATE_PRIV_FAIL) {
1467 } else if (er == EMULATE_FAIL) {
1468 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1475 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1477 ++vcpu->stat.int_exits;
1486 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1488 ++vcpu->stat.cop_unusable_exits;
1489 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1490 /* XXXKYMA: Might need to return to user space */
1491 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1496 ++vcpu->stat.tlbmod_exits;
1497 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1501 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1502 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1505 ++vcpu->stat.tlbmiss_st_exits;
1506 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1510 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1511 cause, opc, badvaddr);
1513 ++vcpu->stat.tlbmiss_ld_exits;
1514 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1518 ++vcpu->stat.addrerr_st_exits;
1519 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1523 ++vcpu->stat.addrerr_ld_exits;
1524 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1528 ++vcpu->stat.syscall_exits;
1529 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1533 ++vcpu->stat.resvd_inst_exits;
1534 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1538 ++vcpu->stat.break_inst_exits;
1539 ret = kvm_mips_callbacks->handle_break(vcpu);
1543 ++vcpu->stat.trap_inst_exits;
1544 ret = kvm_mips_callbacks->handle_trap(vcpu);
1547 case EXCCODE_MSAFPE:
1548 ++vcpu->stat.msa_fpe_exits;
1549 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1553 ++vcpu->stat.fpe_exits;
1554 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1557 case EXCCODE_MSADIS:
1558 ++vcpu->stat.msa_disabled_exits;
1559 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1563 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1564 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1565 kvm_read_c0_guest_status(vcpu->arch.cop0));
1566 kvm_arch_vcpu_dump_regs(vcpu);
1567 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1574 local_irq_disable();
1576 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1577 kvm_mips_deliver_interrupts(vcpu, cause);
1579 if (!(ret & RESUME_HOST)) {
1580 /* Only check for signals if not already exiting to userspace */
1581 if (signal_pending(current)) {
1582 run->exit_reason = KVM_EXIT_INTR;
1583 ret = (-EINTR << 2) | RESUME_HOST;
1584 ++vcpu->stat.signal_exits;
1585 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1589 if (ret == RESUME_GUEST) {
1590 trace_kvm_reenter(vcpu);
1592 kvm_mips_check_asids(vcpu);
1595 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1596 * is live), restore FCR31 / MSACSR.
1598 * This should be before returning to the guest exception
1599 * vector, as it may well cause an [MSA] FP exception if there
1600 * are pending exception bits unmasked. (see
1601 * kvm_mips_csr_die_notifier() for how that is handled).
1603 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1604 read_c0_status() & ST0_CU1)
1605 __kvm_restore_fcsr(&vcpu->arch);
1607 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1608 read_c0_config5() & MIPS_CONF5_MSAEN)
1609 __kvm_restore_msacsr(&vcpu->arch);
1612 /* Disable HTW before returning to guest or host */
1618 /* Enable FPU for guest and restore context */
1619 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1621 struct mips_coproc *cop0 = vcpu->arch.cop0;
1622 unsigned int sr, cfg5;
1626 sr = kvm_read_c0_guest_status(cop0);
1629 * If MSA state is already live, it is undefined how it interacts with
1630 * FR=0 FPU state, and we don't want to hit reserved instruction
1631 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1632 * play it safe and save it first.
1634 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1635 * get called when guest CU1 is set, however we can't trust the guest
1636 * not to clobber the status register directly via the commpage.
1638 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1639 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1643 * Enable FPU for guest
1644 * We set FR and FRE according to guest context
1646 change_c0_status(ST0_CU1 | ST0_FR, sr);
1648 cfg5 = kvm_read_c0_guest_config5(cop0);
1649 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1651 enable_fpu_hazard();
1653 /* If guest FPU state not active, restore it now */
1654 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1655 __kvm_restore_fpu(&vcpu->arch);
1656 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1657 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1659 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1665 #ifdef CONFIG_CPU_HAS_MSA
1666 /* Enable MSA for guest and restore context */
1667 void kvm_own_msa(struct kvm_vcpu *vcpu)
1669 struct mips_coproc *cop0 = vcpu->arch.cop0;
1670 unsigned int sr, cfg5;
1675 * Enable FPU if enabled in guest, since we're restoring FPU context
1676 * anyway. We set FR and FRE according to guest context.
1678 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1679 sr = kvm_read_c0_guest_status(cop0);
1682 * If FR=0 FPU state is already live, it is undefined how it
1683 * interacts with MSA state, so play it safe and save it first.
1685 if (!(sr & ST0_FR) &&
1686 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1687 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1690 change_c0_status(ST0_CU1 | ST0_FR, sr);
1691 if (sr & ST0_CU1 && cpu_has_fre) {
1692 cfg5 = kvm_read_c0_guest_config5(cop0);
1693 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1697 /* Enable MSA for guest */
1698 set_c0_config5(MIPS_CONF5_MSAEN);
1699 enable_fpu_hazard();
1701 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1702 case KVM_MIPS_AUX_FPU:
1704 * Guest FPU state already loaded, only restore upper MSA state
1706 __kvm_restore_msa_upper(&vcpu->arch);
1707 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1708 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1711 /* Neither FPU or MSA already active, restore full MSA state */
1712 __kvm_restore_msa(&vcpu->arch);
1713 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1714 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1715 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1716 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1717 KVM_TRACE_AUX_FPU_MSA);
1720 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1728 /* Drop FPU & MSA without saving it */
1729 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1732 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1734 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1735 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1737 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1738 clear_c0_status(ST0_CU1 | ST0_FR);
1739 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1740 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1745 /* Save and disable FPU & MSA */
1746 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1749 * FPU & MSA get disabled in root context (hardware) when it is disabled
1750 * in guest context (software), but the register state in the hardware
1751 * may still be in use. This is why we explicitly re-enable the hardware
1756 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1757 set_c0_config5(MIPS_CONF5_MSAEN);
1758 enable_fpu_hazard();
1760 __kvm_save_msa(&vcpu->arch);
1761 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1763 /* Disable MSA & FPU */
1765 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1766 clear_c0_status(ST0_CU1 | ST0_FR);
1767 disable_fpu_hazard();
1769 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1770 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1771 set_c0_status(ST0_CU1);
1772 enable_fpu_hazard();
1774 __kvm_save_fpu(&vcpu->arch);
1775 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1776 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1779 clear_c0_status(ST0_CU1 | ST0_FR);
1780 disable_fpu_hazard();
1786 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1787 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1788 * exception if cause bits are set in the value being written.
1790 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1791 unsigned long cmd, void *ptr)
1793 struct die_args *args = (struct die_args *)ptr;
1794 struct pt_regs *regs = args->regs;
1797 /* Only interested in FPE and MSAFPE */
1798 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1801 /* Return immediately if guest context isn't active */
1802 if (!(current->flags & PF_VCPU))
1805 /* Should never get here from user mode */
1806 BUG_ON(user_mode(regs));
1808 pc = instruction_pointer(regs);
1811 /* match 2nd instruction in __kvm_restore_fcsr */
1812 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1816 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1818 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1819 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1824 /* Move PC forward a little and continue executing */
1825 instruction_pointer(regs) += 4;
1830 static struct notifier_block kvm_mips_csr_die_notifier = {
1831 .notifier_call = kvm_mips_csr_die_notify,
1834 static int __init kvm_mips_init(void)
1838 ret = kvm_mips_entry_setup();
1842 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1847 register_die_notifier(&kvm_mips_csr_die_notifier);
1852 static void __exit kvm_mips_exit(void)
1856 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1859 module_init(kvm_mips_init);
1860 module_exit(kvm_mips_exit);
1862 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);