arch/mips/kernel/perf_event_mipsxx.c

   1 /*
   2  * Linux performance counter support for MIPS.
   3  *
   4  * Copyright (C) 2010 MIPS Technologies, Inc.
   5  * Copyright (C) 2011 Cavium Networks, Inc.
   6  * Author: Deng-Cheng Zhu
   7  *
   8  * This code is based on the implementation for ARM, which is in turn
   9  * based on the sparc64 perf event code and the x86 code. Performance
  10  * counter access is based on the MIPS Oprofile code. And the callchain
  11  * support references the code of MIPS stacktrace.c.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/cpumask.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/smp.h>
  21 #include <linux/kernel.h>
  22 #include <linux/perf_event.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/irq.h>
  26 #include <asm/irq_regs.h>
  27 #include <asm/stacktrace.h>
  28 #include <asm/time.h> /* For perf_irq */
  29
  30 #define MIPS_MAX_HWEVENTS 4
  31
  32 struct cpu_hw_events {
  33         /* Array of events on this cpu. */
  34         struct perf_event       *events[MIPS_MAX_HWEVENTS];
  35
  36         /*
  37          * Set the bit (indexed by the counter number) when the counter
  38          * is used for an event.
  39          */
  40         unsigned long           used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
  41
  42         /*
  43          * Software copy of the control register for each performance counter.
  44          * MIPS CPUs vary in performance counters. They use this differently,
  45          * and even may not use it.
  46          */
  47         unsigned int            saved_ctrl[MIPS_MAX_HWEVENTS];
  48 };
  49 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  50         .saved_ctrl = {0},
  51 };
  52
  53 /* The description of MIPS performance events. */
  54 struct mips_perf_event {
  55         unsigned int event_id;
  56         /*
  57          * MIPS performance counters are indexed starting from 0.
  58          * CNTR_EVEN indicates the indexes of the counters to be used are
  59          * even numbers.
  60          */
  61         unsigned int cntr_mask;
  62         #define CNTR_EVEN       0x55555555
  63         #define CNTR_ODD        0xaaaaaaaa
  64         #define CNTR_ALL        0xffffffff
  65 #ifdef CONFIG_MIPS_MT_SMP
  66         enum {
  67                 T  = 0,
  68                 V  = 1,
  69                 P  = 2,
  70         } range;
  71 #else
  72         #define T
  73         #define V
  74         #define P
  75 #endif
  76 };
  77
  78 static struct mips_perf_event raw_event;
  79 static DEFINE_MUTEX(raw_event_mutex);
  80
  81 #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
  82 #define C(x) PERF_COUNT_HW_CACHE_##x
  83
  84 struct mips_pmu {
  85         u64             max_period;
  86         u64             valid_count;
  87         u64             overflow;
  88         const char      *name;
  89         int             irq;
  90         u64             (*read_counter)(unsigned int idx);
  91         void            (*write_counter)(unsigned int idx, u64 val);
  92         const struct mips_perf_event *(*map_raw_event)(u64 config);
  93         const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
  94         const struct mips_perf_event (*cache_event_map)
  95                                 [PERF_COUNT_HW_CACHE_MAX]
  96                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  97                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  98         unsigned int    num_counters;
  99 };
 100
 101 static struct mips_pmu mipspmu;
 102
 103 #define M_CONFIG1_PC    (1 << 4)
 104
 105 #define M_PERFCTL_EXL                   (1      <<  0)
 106 #define M_PERFCTL_KERNEL                (1      <<  1)
 107 #define M_PERFCTL_SUPERVISOR            (1      <<  2)
 108 #define M_PERFCTL_USER                  (1      <<  3)
 109 #define M_PERFCTL_INTERRUPT_ENABLE      (1      <<  4)
 110 #define M_PERFCTL_EVENT(event)          (((event) & 0x3ff)  << 5)
 111 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
 112 #define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
 113 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
 114 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
 115 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
 116 #define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
 117 #define M_PERFCTL_WIDE                  (1      << 30)
 118 #define M_PERFCTL_MORE                  (1      << 31)
 119
 120 #define M_PERFCTL_COUNT_EVENT_WHENEVER  (M_PERFCTL_EXL |                \
 121                                         M_PERFCTL_KERNEL |              \
 122                                         M_PERFCTL_USER |                \
 123                                         M_PERFCTL_SUPERVISOR |          \
 124                                         M_PERFCTL_INTERRUPT_ENABLE)
 125
 126 #ifdef CONFIG_MIPS_MT_SMP
 127 #define M_PERFCTL_CONFIG_MASK           0x3fff801f
 128 #else
 129 #define M_PERFCTL_CONFIG_MASK           0x1f
 130 #endif
 131 #define M_PERFCTL_EVENT_MASK            0xfe0
 132
 133
 134 #ifdef CONFIG_MIPS_MT_SMP
 135 static int cpu_has_mipsmt_pertccounters;
 136
 137 static DEFINE_RWLOCK(pmuint_rwlock);
 138
 139 /*
 140  * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
 141  * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
 142  */
 143 #if defined(CONFIG_HW_PERF_EVENTS)
 144 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 145                         0 : smp_processor_id())
 146 #else
 147 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 148                         0 : cpu_data[smp_processor_id()].vpe_id)
 149 #endif
 150
 151 /* Copied from op_model_mipsxx.c */
 152 static unsigned int vpe_shift(void)
 153 {
 154         if (num_possible_cpus() > 1)
 155                 return 1;
 156
 157         return 0;
 158 }
 159
 160 static unsigned int counters_total_to_per_cpu(unsigned int counters)
 161 {
 162         return counters >> vpe_shift();
 163 }
 164
 165 #else /* !CONFIG_MIPS_MT_SMP */
 166 #define vpe_id()        0
 167
 168 #endif /* CONFIG_MIPS_MT_SMP */
 169
 170 static void resume_local_counters(void);
 171 static void pause_local_counters(void);
 172 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
 173 static int mipsxx_pmu_handle_shared_irq(void);
 174
 175 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
 176 {
 177         if (vpe_id() == 1)
 178                 idx = (idx + 2) & 3;
 179         return idx;
 180 }
 181
 182 static u64 mipsxx_pmu_read_counter(unsigned int idx)
 183 {
 184         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 185
 186         switch (idx) {
 187         case 0:
 188                 /*
 189                  * The counters are unsigned, we must cast to truncate
 190                  * off the high bits.
 191                  */
 192                 return (u32)read_c0_perfcntr0();
 193         case 1:
 194                 return (u32)read_c0_perfcntr1();
 195         case 2:
 196                 return (u32)read_c0_perfcntr2();
 197         case 3:
 198                 return (u32)read_c0_perfcntr3();
 199         default:
 200                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 201                 return 0;
 202         }
 203 }
 204
 205 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
 206 {
 207         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 208
 209         switch (idx) {
 210         case 0:
 211                 return read_c0_perfcntr0_64();
 212         case 1:
 213                 return read_c0_perfcntr1_64();
 214         case 2:
 215                 return read_c0_perfcntr2_64();
 216         case 3:
 217                 return read_c0_perfcntr3_64();
 218         default:
 219                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 220                 return 0;
 221         }
 222 }
 223
 224 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
 225 {
 226         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 227
 228         switch (idx) {
 229         case 0:
 230                 write_c0_perfcntr0(val);
 231                 return;
 232         case 1:
 233                 write_c0_perfcntr1(val);
 234                 return;
 235         case 2:
 236                 write_c0_perfcntr2(val);
 237                 return;
 238         case 3:
 239                 write_c0_perfcntr3(val);
 240                 return;
 241         }
 242 }
 243
 244 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
 245 {
 246         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 247
 248         switch (idx) {
 249         case 0:
 250                 write_c0_perfcntr0_64(val);
 251                 return;
 252         case 1:
 253                 write_c0_perfcntr1_64(val);
 254                 return;
 255         case 2:
 256                 write_c0_perfcntr2_64(val);
 257                 return;
 258         case 3:
 259                 write_c0_perfcntr3_64(val);
 260                 return;
 261         }
 262 }
 263
 264 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
 265 {
 266         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 267
 268         switch (idx) {
 269         case 0:
 270                 return read_c0_perfctrl0();
 271         case 1:
 272                 return read_c0_perfctrl1();
 273         case 2:
 274                 return read_c0_perfctrl2();
 275         case 3:
 276                 return read_c0_perfctrl3();
 277         default:
 278                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 279                 return 0;
 280         }
 281 }
 282
 283 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
 284 {
 285         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 286
 287         switch (idx) {
 288         case 0:
 289                 write_c0_perfctrl0(val);
 290                 return;
 291         case 1:
 292                 write_c0_perfctrl1(val);
 293                 return;
 294         case 2:
 295                 write_c0_perfctrl2(val);
 296                 return;
 297         case 3:
 298                 write_c0_perfctrl3(val);
 299                 return;
 300         }
 301 }
 302
 303 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
 304                                     struct hw_perf_event *hwc)
 305 {
 306         int i;
 307
 308         /*
 309          * We only need to care the counter mask. The range has been
 310          * checked definitely.
 311          */
 312         unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
 313
 314         for (i = mipspmu.num_counters - 1; i >= 0; i--) {
 315                 /*
 316                  * Note that some MIPS perf events can be counted by both
 317                  * even and odd counters, wheresas many other are only by
 318                  * even _or_ odd counters. This introduces an issue that
 319                  * when the former kind of event takes the counter the
 320                  * latter kind of event wants to use, then the "counter
 321                  * allocation" for the latter event will fail. In fact if
 322                  * they can be dynamically swapped, they both feel happy.
 323                  * But here we leave this issue alone for now.
 324                  */
 325                 if (test_bit(i, &cntr_mask) &&
 326                         !test_and_set_bit(i, cpuc->used_mask))
 327                         return i;
 328         }
 329
 330         return -EAGAIN;
 331 }
 332
 333 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
 334 {
 335         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 336
 337         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 338
 339         cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
 340                 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
 341                 /* Make sure interrupt enabled. */
 342                 M_PERFCTL_INTERRUPT_ENABLE;
 343         /*
 344          * We do not actually let the counter run. Leave it until start().
 345          */
 346 }
 347
 348 static void mipsxx_pmu_disable_event(int idx)
 349 {
 350         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 351         unsigned long flags;
 352
 353         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 354
 355         local_irq_save(flags);
 356         cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
 357                 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
 358         mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
 359         local_irq_restore(flags);
 360 }
 361
 362 static int mipspmu_event_set_period(struct perf_event *event,
 363                                     struct hw_perf_event *hwc,
 364                                     int idx)
 365 {
 366         u64 left = local64_read(&hwc->period_left);
 367         u64 period = hwc->sample_period;
 368         int ret = 0;
 369
 370         if (unlikely((left + period) & (1ULL << 63))) {
 371                 /* left underflowed by more than period. */
 372                 left = period;
 373                 local64_set(&hwc->period_left, left);
 374                 hwc->last_period = period;
 375                 ret = 1;
 376         } else  if (unlikely((left + period) <= period)) {
 377                 /* left underflowed by less than period. */
 378                 left += period;
 379                 local64_set(&hwc->period_left, left);
 380                 hwc->last_period = period;
 381                 ret = 1;
 382         }
 383
 384         if (left > mipspmu.max_period) {
 385                 left = mipspmu.max_period;
 386                 local64_set(&hwc->period_left, left);
 387         }
 388
 389         local64_set(&hwc->prev_count, mipspmu.overflow - left);
 390
 391         mipspmu.write_counter(idx, mipspmu.overflow - left);
 392
 393         perf_event_update_userpage(event);
 394
 395         return ret;
 396 }
 397
 398 static void mipspmu_event_update(struct perf_event *event,
 399                                  struct hw_perf_event *hwc,
 400                                  int idx)
 401 {
 402         u64 prev_raw_count, new_raw_count;
 403         u64 delta;
 404
 405 again:
 406         prev_raw_count = local64_read(&hwc->prev_count);
 407         new_raw_count = mipspmu.read_counter(idx);
 408
 409         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 410                                 new_raw_count) != prev_raw_count)
 411                 goto again;
 412
 413         delta = new_raw_count - prev_raw_count;
 414
 415         local64_add(delta, &event->count);
 416         local64_sub(delta, &hwc->period_left);
 417 }
 418
 419 static void mipspmu_start(struct perf_event *event, int flags)
 420 {
 421         struct hw_perf_event *hwc = &event->hw;
 422
 423         if (flags & PERF_EF_RELOAD)
 424                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 425
 426         hwc->state = 0;
 427
 428         /* Set the period for the event. */
 429         mipspmu_event_set_period(event, hwc, hwc->idx);
 430
 431         /* Enable the event. */
 432         mipsxx_pmu_enable_event(hwc, hwc->idx);
 433 }
 434
 435 static void mipspmu_stop(struct perf_event *event, int flags)
 436 {
 437         struct hw_perf_event *hwc = &event->hw;
 438
 439         if (!(hwc->state & PERF_HES_STOPPED)) {
 440                 /* We are working on a local event. */
 441                 mipsxx_pmu_disable_event(hwc->idx);
 442                 barrier();
 443                 mipspmu_event_update(event, hwc, hwc->idx);
 444                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 445         }
 446 }
 447
 448 static int mipspmu_add(struct perf_event *event, int flags)
 449 {
 450         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 451         struct hw_perf_event *hwc = &event->hw;
 452         int idx;
 453         int err = 0;
 454
 455         perf_pmu_disable(event->pmu);
 456
 457         /* To look for a free counter for this event. */
 458         idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
 459         if (idx < 0) {
 460                 err = idx;
 461                 goto out;
 462         }
 463
 464         /*
 465          * If there is an event in the counter we are going to use then
 466          * make sure it is disabled.
 467          */
 468         event->hw.idx = idx;
 469         mipsxx_pmu_disable_event(idx);
 470         cpuc->events[idx] = event;
 471
 472         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 473         if (flags & PERF_EF_START)
 474                 mipspmu_start(event, PERF_EF_RELOAD);
 475
 476         /* Propagate our changes to the userspace mapping. */
 477         perf_event_update_userpage(event);
 478
 479 out:
 480         perf_pmu_enable(event->pmu);
 481         return err;
 482 }
 483
 484 static void mipspmu_del(struct perf_event *event, int flags)
 485 {
 486         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 487         struct hw_perf_event *hwc = &event->hw;
 488         int idx = hwc->idx;
 489
 490         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 491
 492         mipspmu_stop(event, PERF_EF_UPDATE);
 493         cpuc->events[idx] = NULL;
 494         clear_bit(idx, cpuc->used_mask);
 495
 496         perf_event_update_userpage(event);
 497 }
 498
 499 static void mipspmu_read(struct perf_event *event)
 500 {
 501         struct hw_perf_event *hwc = &event->hw;
 502
 503         /* Don't read disabled counters! */
 504         if (hwc->idx < 0)
 505                 return;
 506
 507         mipspmu_event_update(event, hwc, hwc->idx);
 508 }
 509
 510 static void mipspmu_enable(struct pmu *pmu)
 511 {
 512 #ifdef CONFIG_MIPS_MT_SMP
 513         write_unlock(&pmuint_rwlock);
 514 #endif
 515         resume_local_counters();
 516 }
 517
 518 /*
 519  * MIPS performance counters can be per-TC. The control registers can
 520  * not be directly accessed accross CPUs. Hence if we want to do global
 521  * control, we need cross CPU calls. on_each_cpu() can help us, but we
 522  * can not make sure this function is called with interrupts enabled. So
 523  * here we pause local counters and then grab a rwlock and leave the
 524  * counters on other CPUs alone. If any counter interrupt raises while
 525  * we own the write lock, simply pause local counters on that CPU and
 526  * spin in the handler. Also we know we won't be switched to another
 527  * CPU after pausing local counters and before grabbing the lock.
 528  */
 529 static void mipspmu_disable(struct pmu *pmu)
 530 {
 531         pause_local_counters();
 532 #ifdef CONFIG_MIPS_MT_SMP
 533         write_lock(&pmuint_rwlock);
 534 #endif
 535 }
 536
 537 static atomic_t active_events = ATOMIC_INIT(0);
 538 static DEFINE_MUTEX(pmu_reserve_mutex);
 539 static int (*save_perf_irq)(void);
 540
 541 static int mipspmu_get_irq(void)
 542 {
 543         int err;
 544
 545         if (mipspmu.irq >= 0) {
 546                 /* Request my own irq handler. */
 547                 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
 548                         IRQF_PERCPU | IRQF_NOBALANCING,
 549                         "mips_perf_pmu", NULL);
 550                 if (err) {
 551                         pr_warning("Unable to request IRQ%d for MIPS "
 552                            "performance counters!\n", mipspmu.irq);
 553                 }
 554         } else if (cp0_perfcount_irq < 0) {
 555                 /*
 556                  * We are sharing the irq number with the timer interrupt.
 557                  */
 558                 save_perf_irq = perf_irq;
 559                 perf_irq = mipsxx_pmu_handle_shared_irq;
 560                 err = 0;
 561         } else {
 562                 pr_warning("The platform hasn't properly defined its "
 563                         "interrupt controller.\n");
 564                 err = -ENOENT;
 565         }
 566
 567         return err;
 568 }
 569
 570 static void mipspmu_free_irq(void)
 571 {
 572         if (mipspmu.irq >= 0)
 573                 free_irq(mipspmu.irq, NULL);
 574         else if (cp0_perfcount_irq < 0)
 575                 perf_irq = save_perf_irq;
 576 }
 577
 578 /*
 579  * mipsxx/rm9000/loongson2 have different performance counters, they have
 580  * specific low-level init routines.
 581  */
 582 static void reset_counters(void *arg);
 583 static int __hw_perf_event_init(struct perf_event *event);
 584
 585 static void hw_perf_event_destroy(struct perf_event *event)
 586 {
 587         if (atomic_dec_and_mutex_lock(&active_events,
 588                                 &pmu_reserve_mutex)) {
 589                 /*
 590                  * We must not call the destroy function with interrupts
 591                  * disabled.
 592                  */
 593                 on_each_cpu(reset_counters,
 594                         (void *)(long)mipspmu.num_counters, 1);
 595                 mipspmu_free_irq();
 596                 mutex_unlock(&pmu_reserve_mutex);
 597         }
 598 }
 599
 600 static int mipspmu_event_init(struct perf_event *event)
 601 {
 602         int err = 0;
 603
 604         /* does not support taken branch sampling */
 605         if (has_branch_stack(event))
 606                 return -EOPNOTSUPP;
 607
 608         switch (event->attr.type) {
 609         case PERF_TYPE_RAW:
 610         case PERF_TYPE_HARDWARE:
 611         case PERF_TYPE_HW_CACHE:
 612                 break;
 613
 614         default:
 615                 return -ENOENT;
 616         }
 617
 618         if (event->cpu >= nr_cpumask_bits ||
 619             (event->cpu >= 0 && !cpu_online(event->cpu)))
 620                 return -ENODEV;
 621
 622         if (!atomic_inc_not_zero(&active_events)) {
 623                 mutex_lock(&pmu_reserve_mutex);
 624                 if (atomic_read(&active_events) == 0)
 625                         err = mipspmu_get_irq();
 626
 627                 if (!err)
 628                         atomic_inc(&active_events);
 629                 mutex_unlock(&pmu_reserve_mutex);
 630         }
 631
 632         if (err)
 633                 return err;
 634
 635         return __hw_perf_event_init(event);
 636 }
 637
 638 static struct pmu pmu = {
 639         .pmu_enable     = mipspmu_enable,
 640         .pmu_disable    = mipspmu_disable,
 641         .event_init     = mipspmu_event_init,
 642         .add            = mipspmu_add,
 643         .del            = mipspmu_del,
 644         .start          = mipspmu_start,
 645         .stop           = mipspmu_stop,
 646         .read           = mipspmu_read,
 647 };
 648
 649 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
 650 {
 651 /*
 652  * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
 653  * event_id.
 654  */
 655 #ifdef CONFIG_MIPS_MT_SMP
 656         return ((unsigned int)pev->range << 24) |
 657                 (pev->cntr_mask & 0xffff00) |
 658                 (pev->event_id & 0xff);
 659 #else
 660         return (pev->cntr_mask & 0xffff00) |
 661                 (pev->event_id & 0xff);
 662 #endif
 663 }
 664
 665 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
 666 {
 667         const struct mips_perf_event *pev;
 668
 669         pev = ((*mipspmu.general_event_map)[idx].event_id ==
 670                 UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
 671                 &(*mipspmu.general_event_map)[idx]);
 672
 673         return pev;
 674 }
 675
 676 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 677 {
 678         unsigned int cache_type, cache_op, cache_result;
 679         const struct mips_perf_event *pev;
 680
 681         cache_type = (config >> 0) & 0xff;
 682         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 683                 return ERR_PTR(-EINVAL);
 684
 685         cache_op = (config >> 8) & 0xff;
 686         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 687                 return ERR_PTR(-EINVAL);
 688
 689         cache_result = (config >> 16) & 0xff;
 690         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 691                 return ERR_PTR(-EINVAL);
 692
 693         pev = &((*mipspmu.cache_event_map)
 694                                         [cache_type]
 695                                         [cache_op]
 696                                         [cache_result]);
 697
 698         if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
 699                 return ERR_PTR(-EOPNOTSUPP);
 700
 701         return pev;
 702
 703 }
 704
 705 static int validate_group(struct perf_event *event)
 706 {
 707         struct perf_event *sibling, *leader = event->group_leader;
 708         struct cpu_hw_events fake_cpuc;
 709
 710         memset(&fake_cpuc, 0, sizeof(fake_cpuc));
 711
 712         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
 713                 return -EINVAL;
 714
 715         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 716                 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
 717                         return -EINVAL;
 718         }
 719
 720         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
 721                 return -EINVAL;
 722
 723         return 0;
 724 }
 725
 726 /* This is needed by specific irq handlers in perf_event_*.c */
 727 static void handle_associated_event(struct cpu_hw_events *cpuc,
 728                                     int idx, struct perf_sample_data *data,
 729                                     struct pt_regs *regs)
 730 {
 731         struct perf_event *event = cpuc->events[idx];
 732         struct hw_perf_event *hwc = &event->hw;
 733
 734         mipspmu_event_update(event, hwc, idx);
 735         data->period = event->hw.last_period;
 736         if (!mipspmu_event_set_period(event, hwc, idx))
 737                 return;
 738
 739         if (perf_event_overflow(event, data, regs))
 740                 mipsxx_pmu_disable_event(idx);
 741 }
 742
 743
 744 static int __n_counters(void)
 745 {
 746         if (!(read_c0_config1() & M_CONFIG1_PC))
 747                 return 0;
 748         if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
 749                 return 1;
 750         if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
 751                 return 2;
 752         if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
 753                 return 3;
 754
 755         return 4;
 756 }
 757
 758 static int n_counters(void)
 759 {
 760         int counters;
 761
 762         switch (current_cpu_type()) {
 763         case CPU_R10000:
 764                 counters = 2;
 765                 break;
 766
 767         case CPU_R12000:
 768         case CPU_R14000:
 769                 counters = 4;
 770                 break;
 771
 772         default:
 773                 counters = __n_counters();
 774         }
 775
 776         return counters;
 777 }
 778
 779 static void reset_counters(void *arg)
 780 {
 781         int counters = (int)(long)arg;
 782         switch (counters) {
 783         case 4:
 784                 mipsxx_pmu_write_control(3, 0);
 785                 mipspmu.write_counter(3, 0);
 786         case 3:
 787                 mipsxx_pmu_write_control(2, 0);
 788                 mipspmu.write_counter(2, 0);
 789         case 2:
 790                 mipsxx_pmu_write_control(1, 0);
 791                 mipspmu.write_counter(1, 0);
 792         case 1:
 793                 mipsxx_pmu_write_control(0, 0);
 794                 mipspmu.write_counter(0, 0);
 795         }
 796 }
 797
 798 /* 24K/34K/1004K cores can share the same event map. */
 799 static const struct mips_perf_event mipsxxcore_event_map
 800                                 [PERF_COUNT_HW_MAX] = {
 801         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 802         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 803         [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
 804         [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
 805         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
 806         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 807         [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 808 };
 809
 810 /* 74K core has different branch event code. */
 811 static const struct mips_perf_event mipsxx74Kcore_event_map
 812                                 [PERF_COUNT_HW_MAX] = {
 813         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 814         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 815         [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
 816         [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
 817         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
 818         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
 819         [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 820 };
 821
 822 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
 823         [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 824         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
 825         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
 826         [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL  },
 827         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
 828         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
 829         [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
 830 };
 831
 832 /* 24K/34K/1004K cores can share the same cache event map. */
 833 static const struct mips_perf_event mipsxxcore_cache_map
 834                                 [PERF_COUNT_HW_CACHE_MAX]
 835                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 836                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 837 [C(L1D)] = {
 838         /*
 839          * Like some other architectures (e.g. ARM), the performance
 840          * counters don't differentiate between read and write
 841          * accesses/misses, so this isn't strictly correct, but it's the
 842          * best we can do. Writes and reads get combined.
 843          */
 844         [C(OP_READ)] = {
 845                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 846                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 847         },
 848         [C(OP_WRITE)] = {
 849                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 850                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 851         },
 852         [C(OP_PREFETCH)] = {
 853                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 854                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 855         },
 856 },
 857 [C(L1I)] = {
 858         [C(OP_READ)] = {
 859                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 860                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 861         },
 862         [C(OP_WRITE)] = {
 863                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 864                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 865         },
 866         [C(OP_PREFETCH)] = {
 867                 [C(RESULT_ACCESS)]      = { 0x14, CNTR_EVEN, T },
 868                 /*
 869                  * Note that MIPS has only "hit" events countable for
 870                  * the prefetch operation.
 871                  */
 872                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 873         },
 874 },
 875 [C(LL)] = {
 876         [C(OP_READ)] = {
 877                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 878                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 879         },
 880         [C(OP_WRITE)] = {
 881                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 882                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 883         },
 884         [C(OP_PREFETCH)] = {
 885                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 886                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 887         },
 888 },
 889 [C(DTLB)] = {
 890         [C(OP_READ)] = {
 891                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 892                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 893         },
 894         [C(OP_WRITE)] = {
 895                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 896                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 897         },
 898         [C(OP_PREFETCH)] = {
 899                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 900                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 901         },
 902 },
 903 [C(ITLB)] = {
 904         [C(OP_READ)] = {
 905                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 906                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 907         },
 908         [C(OP_WRITE)] = {
 909                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 910                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 911         },
 912         [C(OP_PREFETCH)] = {
 913                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 914                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 915         },
 916 },
 917 [C(BPU)] = {
 918         /* Using the same code for *HW_BRANCH* */
 919         [C(OP_READ)] = {
 920                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 921                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 922         },
 923         [C(OP_WRITE)] = {
 924                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 925                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 926         },
 927         [C(OP_PREFETCH)] = {
 928                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 929                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 930         },
 931 },
 932 [C(NODE)] = {
 933         [C(OP_READ)] = {
 934                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 935                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 936         },
 937         [C(OP_WRITE)] = {
 938                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 939                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 940         },
 941         [C(OP_PREFETCH)] = {
 942                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 943                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 944         },
 945 },
 946 };
 947
 948 /* 74K core has completely different cache event map. */
 949 static const struct mips_perf_event mipsxx74Kcore_cache_map
 950                                 [PERF_COUNT_HW_CACHE_MAX]
 951                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 952                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 953 [C(L1D)] = {
 954         /*
 955          * Like some other architectures (e.g. ARM), the performance
 956          * counters don't differentiate between read and write
 957          * accesses/misses, so this isn't strictly correct, but it's the
 958          * best we can do. Writes and reads get combined.
 959          */
 960         [C(OP_READ)] = {
 961                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 962                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 963         },
 964         [C(OP_WRITE)] = {
 965                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 966                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 967         },
 968         [C(OP_PREFETCH)] = {
 969                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
 970                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 971         },
 972 },
 973 [C(L1I)] = {
 974         [C(OP_READ)] = {
 975                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 976                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 977         },
 978         [C(OP_WRITE)] = {
 979                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 980                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 981         },
 982         [C(OP_PREFETCH)] = {
 983                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_EVEN, T },
 984                 /*
 985                  * Note that MIPS has only "hit" events countable for
 986                  * the prefetch operation.
 987                  */
 988                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
 989         },
 990 },
 991 [C(LL)] = {
 992         [C(OP_READ)] = {
 993                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 994                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
 995         },
 996         [C(OP_WRITE)] = {
 997                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 998                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
 999         },
1000         [C(OP_PREFETCH)] = {
1001                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1002                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1003         },
1004 },
1005 [C(DTLB)] = {
1006         /* 74K core does not have specific DTLB events. */
1007         [C(OP_READ)] = {
1008                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1009                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1010         },
1011         [C(OP_WRITE)] = {
1012                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1013                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1014         },
1015         [C(OP_PREFETCH)] = {
1016                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1017                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1018         },
1019 },
1020 [C(ITLB)] = {
1021         [C(OP_READ)] = {
1022                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
1023                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
1024         },
1025         [C(OP_WRITE)] = {
1026                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
1027                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
1028         },
1029         [C(OP_PREFETCH)] = {
1030                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1031                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1032         },
1033 },
1034 [C(BPU)] = {
1035         /* Using the same code for *HW_BRANCH* */
1036         [C(OP_READ)] = {
1037                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
1038                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
1039         },
1040         [C(OP_WRITE)] = {
1041                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
1042                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
1043         },
1044         [C(OP_PREFETCH)] = {
1045                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1046                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1047         },
1048 },
1049 [C(NODE)] = {
1050         [C(OP_READ)] = {
1051                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1052                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1053         },
1054         [C(OP_WRITE)] = {
1055                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1056                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1057         },
1058         [C(OP_PREFETCH)] = {
1059                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1060                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1061         },
1062 },
1063 };
1064
1065
1066 static const struct mips_perf_event octeon_cache_map
1067                                 [PERF_COUNT_HW_CACHE_MAX]
1068                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1069                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1070 [C(L1D)] = {
1071         [C(OP_READ)] = {
1072                 [C(RESULT_ACCESS)]      = { 0x2b, CNTR_ALL },
1073                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL },
1074         },
1075         [C(OP_WRITE)] = {
1076                 [C(RESULT_ACCESS)]      = { 0x30, CNTR_ALL },
1077                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1078         },
1079         [C(OP_PREFETCH)] = {
1080                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1081                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1082         },
1083 },
1084 [C(L1I)] = {
1085         [C(OP_READ)] = {
1086                 [C(RESULT_ACCESS)]      = { 0x18, CNTR_ALL },
1087                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1088         },
1089         [C(OP_WRITE)] = {
1090                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1091                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1092         },
1093         [C(OP_PREFETCH)] = {
1094                 [C(RESULT_ACCESS)]      = { 0x19, CNTR_ALL },
1095                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1096         },
1097 },
1098 [C(LL)] = {
1099         [C(OP_READ)] = {
1100                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1101                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1102         },
1103         [C(OP_WRITE)] = {
1104                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1105                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1106         },
1107         [C(OP_PREFETCH)] = {
1108                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1109                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1110         },
1111 },
1112 [C(DTLB)] = {
1113         /*
1114          * Only general DTLB misses are counted use the same event for
1115          * read and write.
1116          */
1117         [C(OP_READ)] = {
1118                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1119                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1120         },
1121         [C(OP_WRITE)] = {
1122                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1123                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1124         },
1125         [C(OP_PREFETCH)] = {
1126                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1127                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1128         },
1129 },
1130 [C(ITLB)] = {
1131         [C(OP_READ)] = {
1132                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1133                 [C(RESULT_MISS)]        = { 0x37, CNTR_ALL },
1134         },
1135         [C(OP_WRITE)] = {
1136                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1137                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1138         },
1139         [C(OP_PREFETCH)] = {
1140                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1141                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1142         },
1143 },
1144 [C(BPU)] = {
1145         /* Using the same code for *HW_BRANCH* */
1146         [C(OP_READ)] = {
1147                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1148                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1149         },
1150         [C(OP_WRITE)] = {
1151                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1152                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1153         },
1154         [C(OP_PREFETCH)] = {
1155                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1156                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1157         },
1158 },
1159 };
1160
1161 #ifdef CONFIG_MIPS_MT_SMP
1162 static void check_and_calc_range(struct perf_event *event,
1163                                  const struct mips_perf_event *pev)
1164 {
1165         struct hw_perf_event *hwc = &event->hw;
1166
1167         if (event->cpu >= 0) {
1168                 if (pev->range > V) {
1169                         /*
1170                          * The user selected an event that is processor
1171                          * wide, while expecting it to be VPE wide.
1172                          */
1173                         hwc->config_base |= M_TC_EN_ALL;
1174                 } else {
1175                         /*
1176                          * FIXME: cpu_data[event->cpu].vpe_id reports 0
1177                          * for both CPUs.
1178                          */
1179                         hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1180                         hwc->config_base |= M_TC_EN_VPE;
1181                 }
1182         } else
1183                 hwc->config_base |= M_TC_EN_ALL;
1184 }
1185 #else
1186 static void check_and_calc_range(struct perf_event *event,
1187                                  const struct mips_perf_event *pev)
1188 {
1189 }
1190 #endif
1191
1192 static int __hw_perf_event_init(struct perf_event *event)
1193 {
1194         struct perf_event_attr *attr = &event->attr;
1195         struct hw_perf_event *hwc = &event->hw;
1196         const struct mips_perf_event *pev;
1197         int err;
1198
1199         /* Returning MIPS event descriptor for generic perf event. */
1200         if (PERF_TYPE_HARDWARE == event->attr.type) {
1201                 if (event->attr.config >= PERF_COUNT_HW_MAX)
1202                         return -EINVAL;
1203                 pev = mipspmu_map_general_event(event->attr.config);
1204         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1205                 pev = mipspmu_map_cache_event(event->attr.config);
1206         } else if (PERF_TYPE_RAW == event->attr.type) {
1207                 /* We are working on the global raw event. */
1208                 mutex_lock(&raw_event_mutex);
1209                 pev = mipspmu.map_raw_event(event->attr.config);
1210         } else {
1211                 /* The event type is not (yet) supported. */
1212                 return -EOPNOTSUPP;
1213         }
1214
1215         if (IS_ERR(pev)) {
1216                 if (PERF_TYPE_RAW == event->attr.type)
1217                         mutex_unlock(&raw_event_mutex);
1218                 return PTR_ERR(pev);
1219         }
1220
1221         /*
1222          * We allow max flexibility on how each individual counter shared
1223          * by the single CPU operates (the mode exclusion and the range).
1224          */
1225         hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
1226
1227         /* Calculate range bits and validate it. */
1228         if (num_possible_cpus() > 1)
1229                 check_and_calc_range(event, pev);
1230
1231         hwc->event_base = mipspmu_perf_event_encode(pev);
1232         if (PERF_TYPE_RAW == event->attr.type)
1233                 mutex_unlock(&raw_event_mutex);
1234
1235         if (!attr->exclude_user)
1236                 hwc->config_base |= M_PERFCTL_USER;
1237         if (!attr->exclude_kernel) {
1238                 hwc->config_base |= M_PERFCTL_KERNEL;
1239                 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1240                 hwc->config_base |= M_PERFCTL_EXL;
1241         }
1242         if (!attr->exclude_hv)
1243                 hwc->config_base |= M_PERFCTL_SUPERVISOR;
1244
1245         hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1246         /*
1247          * The event can belong to another cpu. We do not assign a local
1248          * counter for it for now.
1249          */
1250         hwc->idx = -1;
1251         hwc->config = 0;
1252
1253         if (!hwc->sample_period) {
1254                 hwc->sample_period  = mipspmu.max_period;
1255                 hwc->last_period    = hwc->sample_period;
1256                 local64_set(&hwc->period_left, hwc->sample_period);
1257         }
1258
1259         err = 0;
1260         if (event->group_leader != event)
1261                 err = validate_group(event);
1262
1263         event->destroy = hw_perf_event_destroy;
1264
1265         if (err)
1266                 event->destroy(event);
1267
1268         return err;
1269 }
1270
1271 static void pause_local_counters(void)
1272 {
1273         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1274         int ctr = mipspmu.num_counters;
1275         unsigned long flags;
1276
1277         local_irq_save(flags);
1278         do {
1279                 ctr--;
1280                 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1281                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1282                                          ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1283         } while (ctr > 0);
1284         local_irq_restore(flags);
1285 }
1286
1287 static void resume_local_counters(void)
1288 {
1289         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1290         int ctr = mipspmu.num_counters;
1291
1292         do {
1293                 ctr--;
1294                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1295         } while (ctr > 0);
1296 }
1297
1298 static int mipsxx_pmu_handle_shared_irq(void)
1299 {
1300         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1301         struct perf_sample_data data;
1302         unsigned int counters = mipspmu.num_counters;
1303         u64 counter;
1304         int handled = IRQ_NONE;
1305         struct pt_regs *regs;
1306
1307         if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
1308                 return handled;
1309         /*
1310          * First we pause the local counters, so that when we are locked
1311          * here, the counters are all paused. When it gets locked due to
1312          * perf_disable(), the timer interrupt handler will be delayed.
1313          *
1314          * See also mipsxx_pmu_start().
1315          */
1316         pause_local_counters();
1317 #ifdef CONFIG_MIPS_MT_SMP
1318         read_lock(&pmuint_rwlock);
1319 #endif
1320
1321         regs = get_irq_regs();
1322
1323         perf_sample_data_init(&data, 0, 0);
1324
1325         switch (counters) {
1326 #define HANDLE_COUNTER(n)                                               \
1327         case n + 1:                                                     \
1328                 if (test_bit(n, cpuc->used_mask)) {                     \
1329                         counter = mipspmu.read_counter(n);              \
1330                         if (counter & mipspmu.overflow) {               \
1331                                 handle_associated_event(cpuc, n, &data, regs); \
1332                                 handled = IRQ_HANDLED;                  \
1333                         }                                               \
1334                 }
1335         HANDLE_COUNTER(3)
1336         HANDLE_COUNTER(2)
1337         HANDLE_COUNTER(1)
1338         HANDLE_COUNTER(0)
1339         }
1340
1341         /*
1342          * Do all the work for the pending perf events. We can do this
1343          * in here because the performance counter interrupt is a regular
1344          * interrupt, not NMI.
1345          */
1346         if (handled == IRQ_HANDLED)
1347                 irq_work_run();
1348
1349 #ifdef CONFIG_MIPS_MT_SMP
1350         read_unlock(&pmuint_rwlock);
1351 #endif
1352         resume_local_counters();
1353         return handled;
1354 }
1355
1356 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1357 {
1358         return mipsxx_pmu_handle_shared_irq();
1359 }
1360
1361 /* 24K */
1362 #define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
1363         ((b) == 0 || (b) == 1 || (b) == 11)
1364
1365 /* 34K */
1366 #define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
1367         ((b) == 0 || (b) == 1 || (b) == 11)
1368 #ifdef CONFIG_MIPS_MT_SMP
1369 #define IS_RANGE_P_34K_EVENT(r, b)                                      \
1370         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1371          (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
1372          (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
1373          ((b) >= 64 && (b) <= 67))
1374 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1375 #endif
1376
1377 /* 74K */
1378 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
1379         ((b) == 0 || (b) == 1)
1380
1381 /* 1004K */
1382 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
1383         ((b) == 0 || (b) == 1 || (b) == 11)
1384 #ifdef CONFIG_MIPS_MT_SMP
1385 #define IS_RANGE_P_1004K_EVENT(r, b)                                    \
1386         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1387          (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||            \
1388          (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||        \
1389          (r) == 188 || (b) == 61 || (b) == 62 ||                        \
1390          ((b) >= 64 && (b) <= 67))
1391 #define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
1392 #endif
1393
1394 /*
1395  * User can use 0-255 raw events, where 0-127 for the events of even
1396  * counters, and 128-255 for odd counters. Note that bit 7 is used to
1397  * indicate the parity. So, for example, when user wants to take the
1398  * Event Num of 15 for odd counters (by referring to the user manual),
1399  * then 128 needs to be added to 15 as the input for the event config,
1400  * i.e., 143 (0x8F) to be used.
1401  */
1402 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1403 {
1404         unsigned int raw_id = config & 0xff;
1405         unsigned int base_id = raw_id & 0x7f;
1406
1407         raw_event.event_id = base_id;
1408
1409         switch (current_cpu_type()) {
1410         case CPU_24K:
1411                 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1412                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1413                 else
1414                         raw_event.cntr_mask =
1415                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1416 #ifdef CONFIG_MIPS_MT_SMP
1417                 /*
1418                  * This is actually doing nothing. Non-multithreading
1419                  * CPUs will not check and calculate the range.
1420                  */
1421                 raw_event.range = P;
1422 #endif
1423                 break;
1424         case CPU_34K:
1425                 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1426                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1427                 else
1428                         raw_event.cntr_mask =
1429                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1430 #ifdef CONFIG_MIPS_MT_SMP
1431                 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1432                         raw_event.range = P;
1433                 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1434                         raw_event.range = V;
1435                 else
1436                         raw_event.range = T;
1437 #endif
1438                 break;
1439         case CPU_74K:
1440                 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1441                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1442                 else
1443                         raw_event.cntr_mask =
1444                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1445 #ifdef CONFIG_MIPS_MT_SMP
1446                 raw_event.range = P;
1447 #endif
1448                 break;
1449         case CPU_1004K:
1450                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1451                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1452                 else
1453                         raw_event.cntr_mask =
1454                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1455 #ifdef CONFIG_MIPS_MT_SMP
1456                 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1457                         raw_event.range = P;
1458                 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1459                         raw_event.range = V;
1460                 else
1461                         raw_event.range = T;
1462 #endif
1463                 break;
1464         }
1465
1466         return &raw_event;
1467 }
1468
1469 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1470 {
1471         unsigned int raw_id = config & 0xff;
1472         unsigned int base_id = raw_id & 0x7f;
1473
1474
1475         raw_event.cntr_mask = CNTR_ALL;
1476         raw_event.event_id = base_id;
1477
1478         if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1479                 if (base_id > 0x42)
1480                         return ERR_PTR(-EOPNOTSUPP);
1481         } else {
1482                 if (base_id > 0x3a)
1483                         return ERR_PTR(-EOPNOTSUPP);
1484         }
1485
1486         switch (base_id) {
1487         case 0x00:
1488         case 0x0f:
1489         case 0x1e:
1490         case 0x1f:
1491         case 0x2f:
1492         case 0x34:
1493         case 0x3b ... 0x3f:
1494                 return ERR_PTR(-EOPNOTSUPP);
1495         default:
1496                 break;
1497         }
1498
1499         return &raw_event;
1500 }
1501
1502 static int __init
1503 init_hw_perf_events(void)
1504 {
1505         int counters, irq;
1506         int counter_bits;
1507
1508         pr_info("Performance counters: ");
1509
1510         counters = n_counters();
1511         if (counters == 0) {
1512                 pr_cont("No available PMU.\n");
1513                 return -ENODEV;
1514         }
1515
1516 #ifdef CONFIG_MIPS_MT_SMP
1517         cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1518         if (!cpu_has_mipsmt_pertccounters)
1519                 counters = counters_total_to_per_cpu(counters);
1520 #endif
1521
1522 #ifdef MSC01E_INT_BASE
1523         if (cpu_has_veic) {
1524                 /*
1525                  * Using platform specific interrupt controller defines.
1526                  */
1527                 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
1528         } else {
1529 #endif
1530                 if ((cp0_perfcount_irq >= 0) &&
1531                                 (cp0_compare_irq != cp0_perfcount_irq))
1532                         irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1533                 else
1534                         irq = -1;
1535 #ifdef MSC01E_INT_BASE
1536         }
1537 #endif
1538
1539         mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1540
1541         switch (current_cpu_type()) {
1542         case CPU_24K:
1543                 mipspmu.name = "mips/24K";
1544                 mipspmu.general_event_map = &mipsxxcore_event_map;
1545                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1546                 break;
1547         case CPU_34K:
1548                 mipspmu.name = "mips/34K";
1549                 mipspmu.general_event_map = &mipsxxcore_event_map;
1550                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1551                 break;
1552         case CPU_74K:
1553                 mipspmu.name = "mips/74K";
1554                 mipspmu.general_event_map = &mipsxx74Kcore_event_map;
1555                 mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
1556                 break;
1557         case CPU_1004K:
1558                 mipspmu.name = "mips/1004K";
1559                 mipspmu.general_event_map = &mipsxxcore_event_map;
1560                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1561                 break;
1562         case CPU_CAVIUM_OCTEON:
1563         case CPU_CAVIUM_OCTEON_PLUS:
1564         case CPU_CAVIUM_OCTEON2:
1565                 mipspmu.name = "octeon";
1566                 mipspmu.general_event_map = &octeon_event_map;
1567                 mipspmu.cache_event_map = &octeon_cache_map;
1568                 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1569                 break;
1570         default:
1571                 pr_cont("Either hardware does not support performance "
1572                         "counters, or not yet implemented.\n");
1573                 return -ENODEV;
1574         }
1575
1576         mipspmu.num_counters = counters;
1577         mipspmu.irq = irq;
1578
1579         if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
1580                 mipspmu.max_period = (1ULL << 63) - 1;
1581                 mipspmu.valid_count = (1ULL << 63) - 1;
1582                 mipspmu.overflow = 1ULL << 63;
1583                 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1584                 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1585                 counter_bits = 64;
1586         } else {
1587                 mipspmu.max_period = (1ULL << 31) - 1;
1588                 mipspmu.valid_count = (1ULL << 31) - 1;
1589                 mipspmu.overflow = 1ULL << 31;
1590                 mipspmu.read_counter = mipsxx_pmu_read_counter;
1591                 mipspmu.write_counter = mipsxx_pmu_write_counter;
1592                 counter_bits = 32;
1593         }
1594
1595         on_each_cpu(reset_counters, (void *)(long)counters, 1);
1596
1597         pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1598                 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1599                 irq < 0 ? " (share with timer interrupt)" : "");
1600
1601         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1602
1603         return 0;
1604 }
1605 early_initcall(init_hw_perf_events);