arch/mips/kernel/irq-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/init.h>
  11 #include <linux/smp.h>
  12 #include <linux/irq.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/gic.h>
  16 #include <asm/setup.h>
  17 #include <asm/traps.h>
  18 #include <asm/gcmpregs.h>
  19 #include <linux/hardirq.h>
  20 #include <asm-generic/bitops/find.h>
  21
  22 unsigned int gic_frequency;
  23 unsigned int gic_present;
  24 unsigned long _gic_base;
  25 unsigned int gic_irq_base;
  26 unsigned int gic_irq_flags[GIC_NUM_INTRS];
  27
  28 /* The index into this array is the vector # of the interrupt. */
  29 struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  30
  31 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  32 static struct gic_pending_regs pending_regs[NR_CPUS];
  33 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  34
  35 unsigned int gic_get_timer_pending(void)
  36 {
  37         unsigned int vpe_pending;
  38
  39         GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  40         GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  41         return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  42 }
  43
  44 void gic_bind_eic_interrupt(int irq, int set)
  45 {
  46         /* Convert irq vector # to hw int # */
  47         irq -= GIC_PIN_TO_VEC_OFFSET;
  48
  49         /* Set irq to use shadow set */
  50         GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  51 }
  52
  53 void gic_send_ipi(unsigned int intr)
  54 {
  55         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
  56 }
  57
  58 static void gic_eic_irq_dispatch(void)
  59 {
  60         unsigned int cause = read_c0_cause();
  61         int irq;
  62
  63         irq = (cause & ST0_IM) >> STATUSB_IP2;
  64         if (irq == 0)
  65                 irq = -1;
  66
  67         if (irq >= 0)
  68                 do_IRQ(gic_irq_base + irq);
  69         else
  70                 spurious_interrupt();
  71 }
  72
  73 static void __init vpe_local_setup(unsigned int numvpes)
  74 {
  75         unsigned long timer_intr = GIC_INT_TMR;
  76         unsigned long perf_intr = GIC_INT_PERFCTR;
  77         unsigned int vpe_ctl;
  78         int i;
  79
  80         if (cpu_has_veic) {
  81                 /*
  82                  * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
  83                  * map to pin X+2-1 (since GIC adds 1)
  84                  */
  85                 timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  86                 /*
  87                  * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
  88                  * map to pin X+2-1 (since GIC adds 1)
  89                  */
  90                 perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  91         }
  92
  93         /*
  94          * Setup the default performance counter timer interrupts
  95          * for all VPEs
  96          */
  97         for (i = 0; i < numvpes; i++) {
  98                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
  99
 100                 /* Are Interrupts locally routable? */
 101                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 102                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 103                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 104                                  GIC_MAP_TO_PIN_MSK | timer_intr);
 105                 if (cpu_has_veic) {
 106                         set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
 107                                 gic_eic_irq_dispatch);
 108                         gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
 109                 }
 110
 111                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 112                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 113                                  GIC_MAP_TO_PIN_MSK | perf_intr);
 114                 if (cpu_has_veic) {
 115                         set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
 116                         gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
 117                 }
 118         }
 119 }
 120
 121 unsigned int gic_get_int(void)
 122 {
 123         unsigned int i;
 124         unsigned long *pending, *intrmask, *pcpu_mask;
 125         unsigned long *pending_abs, *intrmask_abs;
 126
 127         /* Get per-cpu bitmaps */
 128         pending = pending_regs[smp_processor_id()].pending;
 129         intrmask = intrmask_regs[smp_processor_id()].intrmask;
 130         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 131
 132         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 133                                                          GIC_SH_PEND_31_0_OFS);
 134         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 135                                                           GIC_SH_MASK_31_0_OFS);
 136
 137         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 138                 GICREAD(*pending_abs, pending[i]);
 139                 GICREAD(*intrmask_abs, intrmask[i]);
 140                 pending_abs++;
 141                 intrmask_abs++;
 142         }
 143
 144         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 145         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 146
 147         return find_first_bit(pending, GIC_NUM_INTRS);
 148 }
 149
 150 static void gic_mask_irq(struct irq_data *d)
 151 {
 152         GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 153 }
 154
 155 static void gic_unmask_irq(struct irq_data *d)
 156 {
 157         GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 158 }
 159
 160 #ifdef CONFIG_SMP
 161 static DEFINE_SPINLOCK(gic_lock);
 162
 163 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 164                             bool force)
 165 {
 166         unsigned int irq = (d->irq - gic_irq_base);
 167         cpumask_t       tmp = CPU_MASK_NONE;
 168         unsigned long   flags;
 169         int             i;
 170
 171         cpumask_and(&tmp, cpumask, cpu_online_mask);
 172         if (cpus_empty(tmp))
 173                 return -1;
 174
 175         /* Assumption : cpumask refers to a single CPU */
 176         spin_lock_irqsave(&gic_lock, flags);
 177         for (;;) {
 178                 /* Re-route this IRQ */
 179                 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 180
 181                 /* Update the pcpu_masks */
 182                 for (i = 0; i < NR_CPUS; i++)
 183                         clear_bit(irq, pcpu_masks[i].pcpu_mask);
 184                 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 185
 186         }
 187         cpumask_copy(d->affinity, cpumask);
 188         spin_unlock_irqrestore(&gic_lock, flags);
 189
 190         return IRQ_SET_MASK_OK_NOCOPY;
 191 }
 192 #endif
 193
 194 static struct irq_chip gic_irq_controller = {
 195         .name                   =       "MIPS GIC",
 196         .irq_ack                =       gic_irq_ack,
 197         .irq_mask               =       gic_mask_irq,
 198         .irq_mask_ack           =       gic_mask_irq,
 199         .irq_unmask             =       gic_unmask_irq,
 200         .irq_eoi                =       gic_finish_irq,
 201 #ifdef CONFIG_SMP
 202         .irq_set_affinity       =       gic_set_affinity,
 203 #endif
 204 };
 205
 206 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 207         unsigned int pin, unsigned int polarity, unsigned int trigtype,
 208         unsigned int flags)
 209 {
 210         struct gic_shared_intr_map *map_ptr;
 211
 212         /* Setup Intr to Pin mapping */
 213         if (pin & GIC_MAP_TO_NMI_MSK) {
 214                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 215                 /* FIXME: hack to route NMI to all cpu's */
 216                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 217                         GICWRITE(GIC_REG_ADDR(SHARED,
 218                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 219                                  0xffffffff);
 220                 }
 221         } else {
 222                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 223                          GIC_MAP_TO_PIN_MSK | pin);
 224                 /* Setup Intr to CPU mapping */
 225                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 226                 if (cpu_has_veic) {
 227                         set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
 228                                 gic_eic_irq_dispatch);
 229                         map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
 230                         if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
 231                                 BUG();
 232                         map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
 233                 }
 234         }
 235
 236         /* Setup Intr Polarity */
 237         GIC_SET_POLARITY(intr, polarity);
 238
 239         /* Setup Intr Trigger Type */
 240         GIC_SET_TRIGGER(intr, trigtype);
 241
 242         /* Init Intr Masks */
 243         GIC_CLR_INTR_MASK(intr);
 244         /* Initialise per-cpu Interrupt software masks */
 245         if (flags & GIC_FLAG_IPI)
 246                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 247         if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
 248                 GIC_SET_INTR_MASK(intr);
 249         if (trigtype == GIC_TRIG_EDGE)
 250                 gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 251 }
 252
 253 static void __init gic_basic_init(int numintrs, int numvpes,
 254                         struct gic_intr_map *intrmap, int mapsize)
 255 {
 256         unsigned int i, cpu;
 257         unsigned int pin_offset = 0;
 258
 259         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 260
 261         /* Setup defaults */
 262         for (i = 0; i < numintrs; i++) {
 263                 GIC_SET_POLARITY(i, GIC_POL_POS);
 264                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 265                 GIC_CLR_INTR_MASK(i);
 266                 if (i < GIC_NUM_INTRS) {
 267                         gic_irq_flags[i] = 0;
 268                         gic_shared_intr_map[i].num_shared_intr = 0;
 269                         gic_shared_intr_map[i].local_intr_mask = 0;
 270                 }
 271         }
 272
 273         /*
 274          * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
 275          * one because the GIC will add one (since 0=no intr).
 276          */
 277         if (cpu_has_veic)
 278                 pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
 279
 280         /* Setup specifics */
 281         for (i = 0; i < mapsize; i++) {
 282                 cpu = intrmap[i].cpunum;
 283                 if (cpu == GIC_UNUSED)
 284                         continue;
 285                 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 286                         continue;
 287                 gic_setup_intr(i,
 288                         intrmap[i].cpunum,
 289                         intrmap[i].pin + pin_offset,
 290                         intrmap[i].polarity,
 291                         intrmap[i].trigtype,
 292                         intrmap[i].flags);
 293         }
 294
 295         vpe_local_setup(numvpes);
 296 }
 297
 298 void __init gic_init(unsigned long gic_base_addr,
 299                      unsigned long gic_addrspace_size,
 300                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
 301                      unsigned int irqbase)
 302 {
 303         unsigned int gicconfig;
 304         int numvpes, numintrs;
 305
 306         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 307                                                     gic_addrspace_size);
 308         gic_irq_base = irqbase;
 309
 310         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 311         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 312                    GIC_SH_CONFIG_NUMINTRS_SHF;
 313         numintrs = ((numintrs + 1) * 8);
 314
 315         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 316                   GIC_SH_CONFIG_NUMVPES_SHF;
 317         numvpes = numvpes + 1;
 318
 319         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 320
 321         gic_platform_init(numintrs, &gic_irq_controller);
 322 }