2 * MIPS idle loop and WAIT instruction support.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/export.h>
15 #include <linux/init.h>
16 #include <linux/irqflags.h>
17 #include <linux/printk.h>
18 #include <linux/sched.h>
20 #include <asm/cpu-info.h>
21 #include <asm/mipsregs.h>
24 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
25 * the implementation of the "wait" feature differs between CPU families. This
26 * points to the function that implements CPU specific wait.
27 * The wait instruction stops the pipeline and reduces the power consumption of
30 void (*cpu_wait)(void);
31 EXPORT_SYMBOL(cpu_wait);
33 static void r3081_wait(void)
35 unsigned long cfg = read_c0_conf();
36 write_c0_conf(cfg | R30XX_CONF_HALT);
39 static void r39xx_wait(void)
43 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
47 extern void r4k_wait(void);
50 * This variant is preferable as it allows testing need_resched and going to
51 * sleep depending on the outcome atomically. Unfortunately the "It is
52 * implementation-dependent whether the pipeline restarts when a non-enabled
53 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
54 * using this version a gamble.
56 void r4k_wait_irqoff(void)
67 " .globl __pastwait \n"
72 * The RM7000 variant has to handle erratum 38. The workaround is to not
73 * have any pending stores when the WAIT instruction is executed.
75 static void rm7k_wait_irqoff(void)
85 " mtc0 $1, $12 # stalls until W stage \n"
87 " mtc0 $1, $12 # stalls until W stage \n"
93 * The Au1xxx wait is available only if using 32khz counter or
94 * external timer source, but specifically not CP0 Counter.
95 * alchemy/common/time.c may override cpu_wait!
97 static void au1k_wait(void)
101 " cache 0x14, 0(%0) \n"
102 " cache 0x14, 32(%0) \n"
111 : : "r" (au1k_wait));
114 static int __initdata nowait;
116 static int __init wait_disable(char *s)
123 __setup("nowait", wait_disable);
125 void __init check_wait(void)
127 struct cpuinfo_mips *c = ¤t_cpu_data;
130 printk("Wait instruction disabled.\n");
134 switch (c->cputype) {
137 cpu_wait = r3081_wait;
140 cpu_wait = r39xx_wait;
143 /* case CPU_R4300: */
161 case CPU_CAVIUM_OCTEON:
162 case CPU_CAVIUM_OCTEON_PLUS:
163 case CPU_CAVIUM_OCTEON2:
172 cpu_wait = rm7k_wait_irqoff;
181 if (read_c0_config7() & MIPS_CONF7_WII)
182 cpu_wait = r4k_wait_irqoff;
187 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
188 cpu_wait = r4k_wait_irqoff;
192 cpu_wait = r4k_wait_irqoff;
195 cpu_wait = au1k_wait;
199 * WAIT on Rev1.0 has E1, E2, E3 and E16.
200 * WAIT on Rev2.0 and Rev3.0 has E16.
201 * Rev3.1 WAIT is nop, why bother
203 if ((c->processor_id & 0xff) <= 0x64)
207 * Another rev is incremeting c0_count at a reduced clock
208 * rate while in WAIT mode. So we basically have the choice
209 * between using the cp0 timer as clocksource or avoiding
210 * the WAIT instruction. Until more details are known,
211 * disable the use of WAIT for 20Kc entirely.
216 if ((c->processor_id & 0x00ff) >= 0x40)
224 static void smtc_idle_hook(void)
226 #ifdef CONFIG_MIPS_MT_SMTC
227 void smtc_idle_loop_hook(void);
229 smtc_idle_loop_hook();
233 void arch_cpu_idle(void)