2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
40 static void r3081_wait(void)
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
46 static void r39xx_wait(void)
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
54 extern void r4k_wait(void);
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void r4k_wait_irqoff(void)
67 __asm__(" .set push \n"
72 __asm__(" .globl __pastwait \n"
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
80 static void rm7k_wait_irqoff(void)
90 " mtc0 $1, $12 # stalls until W stage \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
102 static void au1k_wait(void)
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
115 : : "r" (au1k_wait));
118 static int __initdata nowait;
120 static int __init wait_disable(char *s)
127 __setup("nowait", wait_disable);
129 static int __cpuinitdata mips_fpu_disabled;
131 static int __init fpu_disable(char *s)
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
139 __setup("nofpu", fpu_disable);
141 int __cpuinitdata mips_dsp_disabled;
143 static int __init dsp_disable(char *s)
145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
146 mips_dsp_disabled = 1;
151 __setup("nodsp", dsp_disable);
153 void __init check_wait(void)
155 struct cpuinfo_mips *c = ¤t_cpu_data;
158 printk("Wait instruction disabled.\n");
162 switch (c->cputype) {
165 cpu_wait = r3081_wait;
168 cpu_wait = r39xx_wait;
171 /* case CPU_R4300: */
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
200 cpu_wait = rm7k_wait_irqoff;
208 if (read_c0_config7() & MIPS_CONF7_WII)
209 cpu_wait = r4k_wait_irqoff;
214 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
215 cpu_wait = r4k_wait_irqoff;
219 cpu_wait = r4k_wait_irqoff;
222 cpu_wait = au1k_wait;
226 * WAIT on Rev1.0 has E1, E2, E3 and E16.
227 * WAIT on Rev2.0 and Rev3.0 has E16.
228 * Rev3.1 WAIT is nop, why bother
230 if ((c->processor_id & 0xff) <= 0x64)
234 * Another rev is incremeting c0_count at a reduced clock
235 * rate while in WAIT mode. So we basically have the choice
236 * between using the cp0 timer as clocksource or avoiding
237 * the WAIT instruction. Until more details are known,
238 * disable the use of WAIT for 20Kc entirely.
243 if ((c->processor_id & 0x00ff) >= 0x40)
251 static inline void check_errata(void)
253 struct cpuinfo_mips *c = ¤t_cpu_data;
255 switch (c->cputype) {
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/SMTC/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
270 void __init check_bugs32(void)
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
280 static inline int cpu_has_confreg(void)
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
291 return size1 != size2;
297 static inline void set_elf_platform(int cpu, const char *plat)
300 __elf_platform = plat;
304 * Get the FPU Implementation/Revision.
306 static inline unsigned long cpu_get_fpu_id(void)
308 unsigned long tmp, fpu_id;
310 tmp = read_c0_status();
312 fpu_id = read_32bit_cp1_register(CP1_REVISION);
313 write_c0_status(tmp);
318 * Check the CPU has an FPU the official way.
320 static inline int __cpu_has_fpu(void)
322 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
325 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
327 #ifdef __NEED_VMBITS_PROBE
328 write_c0_entryhi(0x3fffffffffffe000ULL);
329 back_to_back_c0_hazard();
330 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
334 static char unknown_isa[] __cpuinitdata = KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
337 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
339 unsigned int config0;
342 config0 = read_c0_config();
344 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
345 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
351 c->isa_level = MIPS_CPU_ISA_M32R1;
354 c->isa_level = MIPS_CPU_ISA_M32R2;
361 switch ((config0 & MIPS_CONF_AR) >> 10) {
363 c->isa_level = MIPS_CPU_ISA_M64R1;
366 c->isa_level = MIPS_CPU_ISA_M64R2;
376 return config0 & MIPS_CONF_M;
379 panic(unknown_isa, config0);
382 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
384 unsigned int config1;
386 config1 = read_c0_config1();
388 if (config1 & MIPS_CONF1_MD)
389 c->ases |= MIPS_ASE_MDMX;
390 if (config1 & MIPS_CONF1_WR)
391 c->options |= MIPS_CPU_WATCH;
392 if (config1 & MIPS_CONF1_CA)
393 c->ases |= MIPS_ASE_MIPS16;
394 if (config1 & MIPS_CONF1_EP)
395 c->options |= MIPS_CPU_EJTAG;
396 if (config1 & MIPS_CONF1_FP) {
397 c->options |= MIPS_CPU_FPU;
398 c->options |= MIPS_CPU_32FPR;
401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
403 return config1 & MIPS_CONF_M;
406 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
408 unsigned int config2;
410 config2 = read_c0_config2();
412 if (config2 & MIPS_CONF2_SL)
413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
415 return config2 & MIPS_CONF_M;
418 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
420 unsigned int config3;
422 config3 = read_c0_config3();
424 if (config3 & MIPS_CONF3_SM) {
425 c->ases |= MIPS_ASE_SMARTMIPS;
426 c->options |= MIPS_CPU_RIXI;
428 if (config3 & MIPS_CONF3_RXI)
429 c->options |= MIPS_CPU_RIXI;
430 if (config3 & MIPS_CONF3_DSP)
431 c->ases |= MIPS_ASE_DSP;
432 if (config3 & MIPS_CONF3_DSP2P)
433 c->ases |= MIPS_ASE_DSP2P;
434 if (config3 & MIPS_CONF3_VINT)
435 c->options |= MIPS_CPU_VINT;
436 if (config3 & MIPS_CONF3_VEIC)
437 c->options |= MIPS_CPU_VEIC;
438 if (config3 & MIPS_CONF3_MT)
439 c->ases |= MIPS_ASE_MIPSMT;
440 if (config3 & MIPS_CONF3_ULRI)
441 c->options |= MIPS_CPU_ULRI;
443 return config3 & MIPS_CONF_M;
446 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
448 unsigned int config4;
450 config4 = read_c0_config4();
452 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
454 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
456 c->kscratch_mask = (config4 >> 16) & 0xff;
458 return config4 & MIPS_CONF_M;
461 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
465 /* MIPS32 or MIPS64 compliant CPU. */
466 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
467 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
469 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
471 ok = decode_config0(c); /* Read Config registers. */
472 BUG_ON(!ok); /* Arch spec violation! */
474 ok = decode_config1(c);
476 ok = decode_config2(c);
478 ok = decode_config3(c);
480 ok = decode_config4(c);
482 mips_probe_watch_registers(c);
485 c->core = read_c0_ebase() & 0x3ff;
488 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
491 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
493 switch (c->processor_id & 0xff00) {
495 c->cputype = CPU_R2000;
496 __cpu_name[cpu] = "R2000";
497 c->isa_level = MIPS_CPU_ISA_I;
498 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
501 c->options |= MIPS_CPU_FPU;
505 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
506 if (cpu_has_confreg()) {
507 c->cputype = CPU_R3081E;
508 __cpu_name[cpu] = "R3081";
510 c->cputype = CPU_R3000A;
511 __cpu_name[cpu] = "R3000A";
514 c->cputype = CPU_R3000;
515 __cpu_name[cpu] = "R3000";
517 c->isa_level = MIPS_CPU_ISA_I;
518 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
521 c->options |= MIPS_CPU_FPU;
525 if (read_c0_config() & CONF_SC) {
526 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
527 c->cputype = CPU_R4400PC;
528 __cpu_name[cpu] = "R4400PC";
530 c->cputype = CPU_R4000PC;
531 __cpu_name[cpu] = "R4000PC";
534 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
535 c->cputype = CPU_R4400SC;
536 __cpu_name[cpu] = "R4400SC";
538 c->cputype = CPU_R4000SC;
539 __cpu_name[cpu] = "R4000SC";
543 c->isa_level = MIPS_CPU_ISA_III;
544 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
545 MIPS_CPU_WATCH | MIPS_CPU_VCE |
549 case PRID_IMP_VR41XX:
550 switch (c->processor_id & 0xf0) {
551 case PRID_REV_VR4111:
552 c->cputype = CPU_VR4111;
553 __cpu_name[cpu] = "NEC VR4111";
555 case PRID_REV_VR4121:
556 c->cputype = CPU_VR4121;
557 __cpu_name[cpu] = "NEC VR4121";
559 case PRID_REV_VR4122:
560 if ((c->processor_id & 0xf) < 0x3) {
561 c->cputype = CPU_VR4122;
562 __cpu_name[cpu] = "NEC VR4122";
564 c->cputype = CPU_VR4181A;
565 __cpu_name[cpu] = "NEC VR4181A";
568 case PRID_REV_VR4130:
569 if ((c->processor_id & 0xf) < 0x4) {
570 c->cputype = CPU_VR4131;
571 __cpu_name[cpu] = "NEC VR4131";
573 c->cputype = CPU_VR4133;
574 __cpu_name[cpu] = "NEC VR4133";
578 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
579 c->cputype = CPU_VR41XX;
580 __cpu_name[cpu] = "NEC Vr41xx";
583 c->isa_level = MIPS_CPU_ISA_III;
584 c->options = R4K_OPTS;
588 c->cputype = CPU_R4300;
589 __cpu_name[cpu] = "R4300";
590 c->isa_level = MIPS_CPU_ISA_III;
591 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
596 c->cputype = CPU_R4600;
597 __cpu_name[cpu] = "R4600";
598 c->isa_level = MIPS_CPU_ISA_III;
599 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
606 * This processor doesn't have an MMU, so it's not
607 * "real easy" to run Linux on it. It is left purely
608 * for documentation. Commented out because it shares
609 * it's c0_prid id number with the TX3900.
611 c->cputype = CPU_R4650;
612 __cpu_name[cpu] = "R4650";
613 c->isa_level = MIPS_CPU_ISA_III;
614 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
619 c->isa_level = MIPS_CPU_ISA_I;
620 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
622 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
623 c->cputype = CPU_TX3927;
624 __cpu_name[cpu] = "TX3927";
627 switch (c->processor_id & 0xff) {
628 case PRID_REV_TX3912:
629 c->cputype = CPU_TX3912;
630 __cpu_name[cpu] = "TX3912";
633 case PRID_REV_TX3922:
634 c->cputype = CPU_TX3922;
635 __cpu_name[cpu] = "TX3922";
642 c->cputype = CPU_R4700;
643 __cpu_name[cpu] = "R4700";
644 c->isa_level = MIPS_CPU_ISA_III;
645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
650 c->cputype = CPU_TX49XX;
651 __cpu_name[cpu] = "R49XX";
652 c->isa_level = MIPS_CPU_ISA_III;
653 c->options = R4K_OPTS | MIPS_CPU_LLSC;
654 if (!(c->processor_id & 0x08))
655 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
659 c->cputype = CPU_R5000;
660 __cpu_name[cpu] = "R5000";
661 c->isa_level = MIPS_CPU_ISA_IV;
662 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
667 c->cputype = CPU_R5432;
668 __cpu_name[cpu] = "R5432";
669 c->isa_level = MIPS_CPU_ISA_IV;
670 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
671 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
675 c->cputype = CPU_R5500;
676 __cpu_name[cpu] = "R5500";
677 c->isa_level = MIPS_CPU_ISA_IV;
678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
679 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
682 case PRID_IMP_NEVADA:
683 c->cputype = CPU_NEVADA;
684 __cpu_name[cpu] = "Nevada";
685 c->isa_level = MIPS_CPU_ISA_IV;
686 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
687 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
691 c->cputype = CPU_R6000;
692 __cpu_name[cpu] = "R6000";
693 c->isa_level = MIPS_CPU_ISA_II;
694 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
698 case PRID_IMP_R6000A:
699 c->cputype = CPU_R6000A;
700 __cpu_name[cpu] = "R6000A";
701 c->isa_level = MIPS_CPU_ISA_II;
702 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
706 case PRID_IMP_RM7000:
707 c->cputype = CPU_RM7000;
708 __cpu_name[cpu] = "RM7000";
709 c->isa_level = MIPS_CPU_ISA_IV;
710 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
713 * Undocumented RM7000: Bit 29 in the info register of
714 * the RM7000 v2.0 indicates if the TLB has 48 or 64
717 * 29 1 => 64 entry JTLB
720 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
722 case PRID_IMP_RM9000:
723 c->cputype = CPU_RM9000;
724 __cpu_name[cpu] = "RM9000";
725 c->isa_level = MIPS_CPU_ISA_IV;
726 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
729 * Bit 29 in the info register of the RM9000
730 * indicates if the TLB has 48 or 64 entries.
732 * 29 1 => 64 entry JTLB
735 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
738 c->cputype = CPU_R8000;
739 __cpu_name[cpu] = "RM8000";
740 c->isa_level = MIPS_CPU_ISA_IV;
741 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
742 MIPS_CPU_FPU | MIPS_CPU_32FPR |
744 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
746 case PRID_IMP_R10000:
747 c->cputype = CPU_R10000;
748 __cpu_name[cpu] = "R10000";
749 c->isa_level = MIPS_CPU_ISA_IV;
750 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
751 MIPS_CPU_FPU | MIPS_CPU_32FPR |
752 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
756 case PRID_IMP_R12000:
757 c->cputype = CPU_R12000;
758 __cpu_name[cpu] = "R12000";
759 c->isa_level = MIPS_CPU_ISA_IV;
760 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
761 MIPS_CPU_FPU | MIPS_CPU_32FPR |
762 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
766 case PRID_IMP_R14000:
767 c->cputype = CPU_R14000;
768 __cpu_name[cpu] = "R14000";
769 c->isa_level = MIPS_CPU_ISA_IV;
770 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
771 MIPS_CPU_FPU | MIPS_CPU_32FPR |
772 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
776 case PRID_IMP_LOONGSON2:
777 c->cputype = CPU_LOONGSON2;
778 __cpu_name[cpu] = "ICT Loongson-2";
780 switch (c->processor_id & PRID_REV_MASK) {
781 case PRID_REV_LOONGSON2E:
782 set_elf_platform(cpu, "loongson2e");
784 case PRID_REV_LOONGSON2F:
785 set_elf_platform(cpu, "loongson2f");
789 c->isa_level = MIPS_CPU_ISA_III;
790 c->options = R4K_OPTS |
791 MIPS_CPU_FPU | MIPS_CPU_LLSC |
795 case PRID_IMP_LOONGSON1:
798 c->cputype = CPU_LOONGSON1;
800 switch (c->processor_id & PRID_REV_MASK) {
801 case PRID_REV_LOONGSON1B:
802 __cpu_name[cpu] = "Loongson 1B";
810 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
813 switch (c->processor_id & 0xff00) {
815 c->cputype = CPU_4KC;
816 __cpu_name[cpu] = "MIPS 4Kc";
819 case PRID_IMP_4KECR2:
820 c->cputype = CPU_4KEC;
821 __cpu_name[cpu] = "MIPS 4KEc";
825 c->cputype = CPU_4KSC;
826 __cpu_name[cpu] = "MIPS 4KSc";
829 c->cputype = CPU_5KC;
830 __cpu_name[cpu] = "MIPS 5Kc";
833 c->cputype = CPU_5KE;
834 __cpu_name[cpu] = "MIPS 5KE";
837 c->cputype = CPU_20KC;
838 __cpu_name[cpu] = "MIPS 20Kc";
842 c->cputype = CPU_24K;
843 __cpu_name[cpu] = "MIPS 24Kc";
846 c->cputype = CPU_25KF;
847 __cpu_name[cpu] = "MIPS 25Kc";
850 c->cputype = CPU_34K;
851 __cpu_name[cpu] = "MIPS 34Kc";
854 c->cputype = CPU_74K;
855 __cpu_name[cpu] = "MIPS 74Kc";
858 c->cputype = CPU_M14KC;
859 __cpu_name[cpu] = "MIPS M14Kc";
862 c->cputype = CPU_1004K;
863 __cpu_name[cpu] = "MIPS 1004Kc";
866 c->cputype = CPU_74K;
867 __cpu_name[cpu] = "MIPS 1074Kc";
874 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
877 switch (c->processor_id & 0xff00) {
878 case PRID_IMP_AU1_REV1:
879 case PRID_IMP_AU1_REV2:
880 c->cputype = CPU_ALCHEMY;
881 switch ((c->processor_id >> 24) & 0xff) {
883 __cpu_name[cpu] = "Au1000";
886 __cpu_name[cpu] = "Au1500";
889 __cpu_name[cpu] = "Au1100";
892 __cpu_name[cpu] = "Au1550";
895 __cpu_name[cpu] = "Au1200";
896 if ((c->processor_id & 0xff) == 2)
897 __cpu_name[cpu] = "Au1250";
900 __cpu_name[cpu] = "Au1210";
903 __cpu_name[cpu] = "Au1xxx";
910 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
914 switch (c->processor_id & 0xff00) {
916 c->cputype = CPU_SB1;
917 __cpu_name[cpu] = "SiByte SB1";
918 /* FPU in pass1 is known to have issues. */
919 if ((c->processor_id & 0xff) < 0x02)
920 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
923 c->cputype = CPU_SB1A;
924 __cpu_name[cpu] = "SiByte SB1A";
929 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
932 switch (c->processor_id & 0xff00) {
933 case PRID_IMP_SR71000:
934 c->cputype = CPU_SR71000;
935 __cpu_name[cpu] = "Sandcraft SR71000";
942 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
945 switch (c->processor_id & 0xff00) {
946 case PRID_IMP_PR4450:
947 c->cputype = CPU_PR4450;
948 __cpu_name[cpu] = "Philips PR4450";
949 c->isa_level = MIPS_CPU_ISA_M32R1;
954 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
957 switch (c->processor_id & 0xff00) {
958 case PRID_IMP_BMIPS32_REV4:
959 case PRID_IMP_BMIPS32_REV8:
960 c->cputype = CPU_BMIPS32;
961 __cpu_name[cpu] = "Broadcom BMIPS32";
962 set_elf_platform(cpu, "bmips32");
964 case PRID_IMP_BMIPS3300:
965 case PRID_IMP_BMIPS3300_ALT:
966 case PRID_IMP_BMIPS3300_BUG:
967 c->cputype = CPU_BMIPS3300;
968 __cpu_name[cpu] = "Broadcom BMIPS3300";
969 set_elf_platform(cpu, "bmips3300");
971 case PRID_IMP_BMIPS43XX: {
972 int rev = c->processor_id & 0xff;
974 if (rev >= PRID_REV_BMIPS4380_LO &&
975 rev <= PRID_REV_BMIPS4380_HI) {
976 c->cputype = CPU_BMIPS4380;
977 __cpu_name[cpu] = "Broadcom BMIPS4380";
978 set_elf_platform(cpu, "bmips4380");
980 c->cputype = CPU_BMIPS4350;
981 __cpu_name[cpu] = "Broadcom BMIPS4350";
982 set_elf_platform(cpu, "bmips4350");
986 case PRID_IMP_BMIPS5000:
987 c->cputype = CPU_BMIPS5000;
988 __cpu_name[cpu] = "Broadcom BMIPS5000";
989 set_elf_platform(cpu, "bmips5000");
990 c->options |= MIPS_CPU_ULRI;
995 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
998 switch (c->processor_id & 0xff00) {
999 case PRID_IMP_CAVIUM_CN38XX:
1000 case PRID_IMP_CAVIUM_CN31XX:
1001 case PRID_IMP_CAVIUM_CN30XX:
1002 c->cputype = CPU_CAVIUM_OCTEON;
1003 __cpu_name[cpu] = "Cavium Octeon";
1005 case PRID_IMP_CAVIUM_CN58XX:
1006 case PRID_IMP_CAVIUM_CN56XX:
1007 case PRID_IMP_CAVIUM_CN50XX:
1008 case PRID_IMP_CAVIUM_CN52XX:
1009 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1010 __cpu_name[cpu] = "Cavium Octeon+";
1012 set_elf_platform(cpu, "octeon");
1014 case PRID_IMP_CAVIUM_CN61XX:
1015 case PRID_IMP_CAVIUM_CN63XX:
1016 case PRID_IMP_CAVIUM_CN66XX:
1017 case PRID_IMP_CAVIUM_CN68XX:
1018 c->cputype = CPU_CAVIUM_OCTEON2;
1019 __cpu_name[cpu] = "Cavium Octeon II";
1020 set_elf_platform(cpu, "octeon2");
1023 printk(KERN_INFO "Unknown Octeon chip!\n");
1024 c->cputype = CPU_UNKNOWN;
1029 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1032 /* JZRISC does not implement the CP0 counter. */
1033 c->options &= ~MIPS_CPU_COUNTER;
1034 switch (c->processor_id & 0xff00) {
1035 case PRID_IMP_JZRISC:
1036 c->cputype = CPU_JZRISC;
1037 __cpu_name[cpu] = "Ingenic JZRISC";
1040 panic("Unknown Ingenic Processor ID!");
1045 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1049 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1050 c->cputype = CPU_ALCHEMY;
1051 __cpu_name[cpu] = "Au1300";
1052 /* following stuff is not for Alchemy */
1056 c->options = (MIPS_CPU_TLB |
1064 switch (c->processor_id & 0xff00) {
1065 case PRID_IMP_NETLOGIC_XLP8XX:
1066 case PRID_IMP_NETLOGIC_XLP3XX:
1067 c->cputype = CPU_XLP;
1068 __cpu_name[cpu] = "Netlogic XLP";
1071 case PRID_IMP_NETLOGIC_XLR732:
1072 case PRID_IMP_NETLOGIC_XLR716:
1073 case PRID_IMP_NETLOGIC_XLR532:
1074 case PRID_IMP_NETLOGIC_XLR308:
1075 case PRID_IMP_NETLOGIC_XLR532C:
1076 case PRID_IMP_NETLOGIC_XLR516C:
1077 case PRID_IMP_NETLOGIC_XLR508C:
1078 case PRID_IMP_NETLOGIC_XLR308C:
1079 c->cputype = CPU_XLR;
1080 __cpu_name[cpu] = "Netlogic XLR";
1083 case PRID_IMP_NETLOGIC_XLS608:
1084 case PRID_IMP_NETLOGIC_XLS408:
1085 case PRID_IMP_NETLOGIC_XLS404:
1086 case PRID_IMP_NETLOGIC_XLS208:
1087 case PRID_IMP_NETLOGIC_XLS204:
1088 case PRID_IMP_NETLOGIC_XLS108:
1089 case PRID_IMP_NETLOGIC_XLS104:
1090 case PRID_IMP_NETLOGIC_XLS616B:
1091 case PRID_IMP_NETLOGIC_XLS608B:
1092 case PRID_IMP_NETLOGIC_XLS416B:
1093 case PRID_IMP_NETLOGIC_XLS412B:
1094 case PRID_IMP_NETLOGIC_XLS408B:
1095 case PRID_IMP_NETLOGIC_XLS404B:
1096 c->cputype = CPU_XLR;
1097 __cpu_name[cpu] = "Netlogic XLS";
1101 pr_info("Unknown Netlogic chip id [%02x]!\n",
1103 c->cputype = CPU_XLR;
1107 if (c->cputype == CPU_XLP) {
1108 c->isa_level = MIPS_CPU_ISA_M64R2;
1109 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1110 /* This will be updated again after all threads are woken up */
1111 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1113 c->isa_level = MIPS_CPU_ISA_M64R1;
1114 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1119 /* For use by uaccess.h */
1121 EXPORT_SYMBOL(__ua_limit);
1124 const char *__cpu_name[NR_CPUS];
1125 const char *__elf_platform;
1127 __cpuinit void cpu_probe(void)
1129 struct cpuinfo_mips *c = ¤t_cpu_data;
1130 unsigned int cpu = smp_processor_id();
1132 c->processor_id = PRID_IMP_UNKNOWN;
1133 c->fpu_id = FPIR_IMP_NONE;
1134 c->cputype = CPU_UNKNOWN;
1136 c->processor_id = read_c0_prid();
1137 switch (c->processor_id & 0xff0000) {
1138 case PRID_COMP_LEGACY:
1139 cpu_probe_legacy(c, cpu);
1141 case PRID_COMP_MIPS:
1142 cpu_probe_mips(c, cpu);
1144 case PRID_COMP_ALCHEMY:
1145 cpu_probe_alchemy(c, cpu);
1147 case PRID_COMP_SIBYTE:
1148 cpu_probe_sibyte(c, cpu);
1150 case PRID_COMP_BROADCOM:
1151 cpu_probe_broadcom(c, cpu);
1153 case PRID_COMP_SANDCRAFT:
1154 cpu_probe_sandcraft(c, cpu);
1157 cpu_probe_nxp(c, cpu);
1159 case PRID_COMP_CAVIUM:
1160 cpu_probe_cavium(c, cpu);
1162 case PRID_COMP_INGENIC:
1163 cpu_probe_ingenic(c, cpu);
1165 case PRID_COMP_NETLOGIC:
1166 cpu_probe_netlogic(c, cpu);
1170 BUG_ON(!__cpu_name[cpu]);
1171 BUG_ON(c->cputype == CPU_UNKNOWN);
1174 * Platform code can force the cpu type to optimize code
1175 * generation. In that case be sure the cpu type is correctly
1176 * manually setup otherwise it could trigger some nasty bugs.
1178 BUG_ON(current_cpu_type() != c->cputype);
1180 if (mips_fpu_disabled)
1181 c->options &= ~MIPS_CPU_FPU;
1183 if (mips_dsp_disabled)
1184 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1186 if (c->options & MIPS_CPU_FPU) {
1187 c->fpu_id = cpu_get_fpu_id();
1189 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1190 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1191 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1192 c->isa_level == MIPS_CPU_ISA_M64R2) {
1193 if (c->fpu_id & MIPS_FPIR_3D)
1194 c->ases |= MIPS_ASE_MIPS3D;
1198 if (cpu_has_mips_r2) {
1199 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1200 /* R2 has Performance Counter Interrupt indicator */
1201 c->options |= MIPS_CPU_PCI;
1206 cpu_probe_vmbits(c);
1210 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1214 __cpuinit void cpu_report(void)
1216 struct cpuinfo_mips *c = ¤t_cpu_data;
1218 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1219 c->processor_id, cpu_name_string());
1220 if (c->options & MIPS_CPU_FPU)
1221 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);