1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2012 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_SPXX_DEFS_H__
29 #define __CVMX_SPXX_DEFS_H__
31 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
48 union cvmx_spxx_bckprs_cnt {
50 struct cvmx_spxx_bckprs_cnt_s {
51 #ifdef __BIG_ENDIAN_BITFIELD
52 uint64_t reserved_32_63:32;
56 uint64_t reserved_32_63:32;
59 struct cvmx_spxx_bckprs_cnt_s cn38xx;
60 struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
61 struct cvmx_spxx_bckprs_cnt_s cn58xx;
62 struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
65 union cvmx_spxx_bist_stat {
67 struct cvmx_spxx_bist_stat_s {
68 #ifdef __BIG_ENDIAN_BITFIELD
69 uint64_t reserved_3_63:61;
77 uint64_t reserved_3_63:61;
80 struct cvmx_spxx_bist_stat_s cn38xx;
81 struct cvmx_spxx_bist_stat_s cn38xxp2;
82 struct cvmx_spxx_bist_stat_s cn58xx;
83 struct cvmx_spxx_bist_stat_s cn58xxp1;
86 union cvmx_spxx_clk_ctl {
88 struct cvmx_spxx_clk_ctl_s {
89 #ifdef __BIG_ENDIAN_BITFIELD
90 uint64_t reserved_17_63:47;
92 uint64_t reserved_12_15:4;
110 uint64_t reserved_12_15:4;
112 uint64_t reserved_17_63:47;
115 struct cvmx_spxx_clk_ctl_s cn38xx;
116 struct cvmx_spxx_clk_ctl_s cn38xxp2;
117 struct cvmx_spxx_clk_ctl_s cn58xx;
118 struct cvmx_spxx_clk_ctl_s cn58xxp1;
121 union cvmx_spxx_clk_stat {
123 struct cvmx_spxx_clk_stat_s {
124 #ifdef __BIG_ENDIAN_BITFIELD
125 uint64_t reserved_11_63:53;
127 uint64_t reserved_9_9:1;
133 uint64_t reserved_0_3:4;
135 uint64_t reserved_0_3:4;
141 uint64_t reserved_9_9:1;
143 uint64_t reserved_11_63:53;
146 struct cvmx_spxx_clk_stat_s cn38xx;
147 struct cvmx_spxx_clk_stat_s cn38xxp2;
148 struct cvmx_spxx_clk_stat_s cn58xx;
149 struct cvmx_spxx_clk_stat_s cn58xxp1;
152 union cvmx_spxx_dbg_deskew_ctl {
154 struct cvmx_spxx_dbg_deskew_ctl_s {
155 #ifdef __BIG_ENDIAN_BITFIELD
156 uint64_t reserved_30_63:34;
159 uint64_t reserved_26_27:2;
162 uint64_t reserved_22_23:2;
182 uint64_t reserved_22_23:2;
185 uint64_t reserved_26_27:2;
188 uint64_t reserved_30_63:34;
191 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
192 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
193 struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
194 struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
197 union cvmx_spxx_dbg_deskew_state {
199 struct cvmx_spxx_dbg_deskew_state_s {
200 #ifdef __BIG_ENDIAN_BITFIELD
201 uint64_t reserved_9_63:55;
211 uint64_t reserved_9_63:55;
214 struct cvmx_spxx_dbg_deskew_state_s cn38xx;
215 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
216 struct cvmx_spxx_dbg_deskew_state_s cn58xx;
217 struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
220 union cvmx_spxx_drv_ctl {
222 struct cvmx_spxx_drv_ctl_s {
223 #ifdef __BIG_ENDIAN_BITFIELD
224 uint64_t reserved_0_63:64;
226 uint64_t reserved_0_63:64;
229 struct cvmx_spxx_drv_ctl_cn38xx {
230 #ifdef __BIG_ENDIAN_BITFIELD
231 uint64_t reserved_16_63:48;
239 uint64_t reserved_16_63:48;
242 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
243 struct cvmx_spxx_drv_ctl_cn58xx {
244 #ifdef __BIG_ENDIAN_BITFIELD
245 uint64_t reserved_24_63:40;
248 uint64_t reserved_10_15:6;
252 uint64_t reserved_10_15:6;
255 uint64_t reserved_24_63:40;
258 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
261 union cvmx_spxx_err_ctl {
263 struct cvmx_spxx_err_ctl_s {
264 #ifdef __BIG_ENDIAN_BITFIELD
265 uint64_t reserved_9_63:55;
269 uint64_t reserved_4_5:2;
273 uint64_t reserved_4_5:2;
277 uint64_t reserved_9_63:55;
280 struct cvmx_spxx_err_ctl_s cn38xx;
281 struct cvmx_spxx_err_ctl_s cn38xxp2;
282 struct cvmx_spxx_err_ctl_s cn58xx;
283 struct cvmx_spxx_err_ctl_s cn58xxp1;
286 union cvmx_spxx_int_dat {
288 struct cvmx_spxx_int_dat_s {
289 #ifdef __BIG_ENDIAN_BITFIELD
290 uint64_t reserved_32_63:32;
292 uint64_t reserved_14_30:17;
300 uint64_t reserved_14_30:17;
302 uint64_t reserved_32_63:32;
305 struct cvmx_spxx_int_dat_s cn38xx;
306 struct cvmx_spxx_int_dat_s cn38xxp2;
307 struct cvmx_spxx_int_dat_s cn58xx;
308 struct cvmx_spxx_int_dat_s cn58xxp1;
311 union cvmx_spxx_int_msk {
313 struct cvmx_spxx_int_msk_s {
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint64_t reserved_12_63:52;
324 uint64_t reserved_2_3:2;
330 uint64_t reserved_2_3:2;
339 uint64_t reserved_12_63:52;
342 struct cvmx_spxx_int_msk_s cn38xx;
343 struct cvmx_spxx_int_msk_s cn38xxp2;
344 struct cvmx_spxx_int_msk_s cn58xx;
345 struct cvmx_spxx_int_msk_s cn58xxp1;
348 union cvmx_spxx_int_reg {
350 struct cvmx_spxx_int_reg_s {
351 #ifdef __BIG_ENDIAN_BITFIELD
352 uint64_t reserved_32_63:32;
354 uint64_t reserved_12_30:19;
363 uint64_t reserved_2_3:2;
369 uint64_t reserved_2_3:2;
378 uint64_t reserved_12_30:19;
380 uint64_t reserved_32_63:32;
383 struct cvmx_spxx_int_reg_s cn38xx;
384 struct cvmx_spxx_int_reg_s cn38xxp2;
385 struct cvmx_spxx_int_reg_s cn58xx;
386 struct cvmx_spxx_int_reg_s cn58xxp1;
389 union cvmx_spxx_int_sync {
391 struct cvmx_spxx_int_sync_s {
392 #ifdef __BIG_ENDIAN_BITFIELD
393 uint64_t reserved_12_63:52;
402 uint64_t reserved_2_3:2;
408 uint64_t reserved_2_3:2;
417 uint64_t reserved_12_63:52;
420 struct cvmx_spxx_int_sync_s cn38xx;
421 struct cvmx_spxx_int_sync_s cn38xxp2;
422 struct cvmx_spxx_int_sync_s cn58xx;
423 struct cvmx_spxx_int_sync_s cn58xxp1;
426 union cvmx_spxx_tpa_acc {
428 struct cvmx_spxx_tpa_acc_s {
429 #ifdef __BIG_ENDIAN_BITFIELD
430 uint64_t reserved_32_63:32;
434 uint64_t reserved_32_63:32;
437 struct cvmx_spxx_tpa_acc_s cn38xx;
438 struct cvmx_spxx_tpa_acc_s cn38xxp2;
439 struct cvmx_spxx_tpa_acc_s cn58xx;
440 struct cvmx_spxx_tpa_acc_s cn58xxp1;
443 union cvmx_spxx_tpa_max {
445 struct cvmx_spxx_tpa_max_s {
446 #ifdef __BIG_ENDIAN_BITFIELD
447 uint64_t reserved_32_63:32;
451 uint64_t reserved_32_63:32;
454 struct cvmx_spxx_tpa_max_s cn38xx;
455 struct cvmx_spxx_tpa_max_s cn38xxp2;
456 struct cvmx_spxx_tpa_max_s cn58xx;
457 struct cvmx_spxx_tpa_max_s cn58xxp1;
460 union cvmx_spxx_tpa_sel {
462 struct cvmx_spxx_tpa_sel_s {
463 #ifdef __BIG_ENDIAN_BITFIELD
464 uint64_t reserved_4_63:60;
468 uint64_t reserved_4_63:60;
471 struct cvmx_spxx_tpa_sel_s cn38xx;
472 struct cvmx_spxx_tpa_sel_s cn38xxp2;
473 struct cvmx_spxx_tpa_sel_s cn58xx;
474 struct cvmx_spxx_tpa_sel_s cn58xxp1;
477 union cvmx_spxx_trn4_ctl {
479 struct cvmx_spxx_trn4_ctl_s {
480 #ifdef __BIG_ENDIAN_BITFIELD
481 uint64_t reserved_13_63:51;
497 uint64_t reserved_13_63:51;
500 struct cvmx_spxx_trn4_ctl_s cn38xx;
501 struct cvmx_spxx_trn4_ctl_s cn38xxp2;
502 struct cvmx_spxx_trn4_ctl_s cn58xx;
503 struct cvmx_spxx_trn4_ctl_s cn58xxp1;