arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_SEGCTL0 $5, 2
  52 #define CP0_SEGCTL1 $5, 3
  53 #define CP0_SEGCTL2 $5, 4
  54 #define CP0_WIRED $6
  55 #define CP0_INFO $7
  56 #define CP0_HWRENA $7
  57 #define CP0_BADVADDR $8
  58 #define CP0_BADINSTR $8, 1
  59 #define CP0_COUNT $9
  60 #define CP0_ENTRYHI $10
  61 #define CP0_GUESTCTL1 $10, 4
  62 #define CP0_GUESTCTL2 $10, 5
  63 #define CP0_GUESTCTL3 $10, 6
  64 #define CP0_COMPARE $11
  65 #define CP0_GUESTCTL0EXT $11, 4
  66 #define CP0_STATUS $12
  67 #define CP0_GUESTCTL0 $12, 6
  68 #define CP0_GTOFFSET $12, 7
  69 #define CP0_CAUSE $13
  70 #define CP0_EPC $14
  71 #define CP0_PRID $15
  72 #define CP0_EBASE $15, 1
  73 #define CP0_CMGCRBASE $15, 3
  74 #define CP0_CONFIG $16
  75 #define CP0_CONFIG3 $16, 3
  76 #define CP0_CONFIG5 $16, 5
  77 #define CP0_LLADDR $17
  78 #define CP0_WATCHLO $18
  79 #define CP0_WATCHHI $19
  80 #define CP0_XCONTEXT $20
  81 #define CP0_FRAMEMASK $21
  82 #define CP0_DIAGNOSTIC $22
  83 #define CP0_DEBUG $23
  84 #define CP0_DEPC $24
  85 #define CP0_PERFORMANCE $25
  86 #define CP0_ECC $26
  87 #define CP0_CACHEERR $27
  88 #define CP0_TAGLO $28
  89 #define CP0_TAGHI $29
  90 #define CP0_ERROREPC $30
  91 #define CP0_DESAVE $31
  92
  93 /*
  94  * R4640/R4650 cp0 register names.  These registers are listed
  95  * here only for completeness; without MMU these CPUs are not useable
  96  * by Linux.  A future ELKS port might take make Linux run on them
  97  * though ...
  98  */
  99 #define CP0_IBASE $0
 100 #define CP0_IBOUND $1
 101 #define CP0_DBASE $2
 102 #define CP0_DBOUND $3
 103 #define CP0_CALG $17
 104 #define CP0_IWATCH $18
 105 #define CP0_DWATCH $19
 106
 107 /*
 108  * Coprocessor 0 Set 1 register names
 109  */
 110 #define CP0_S1_DERRADDR0  $26
 111 #define CP0_S1_DERRADDR1  $27
 112 #define CP0_S1_INTCONTROL $20
 113
 114 /*
 115  * Coprocessor 0 Set 2 register names
 116  */
 117 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 118
 119 /*
 120  * Coprocessor 0 Set 3 register names
 121  */
 122 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 123
 124 /*
 125  *  TX39 Series
 126  */
 127 #define CP0_TX39_CACHE  $7
 128
 129
 130 /* Generic EntryLo bit definitions */
 131 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 132 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 133 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 134 #define ENTRYLO_C_SHIFT         3
 135 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 136
 137 /* R3000 EntryLo bit definitions */
 138 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 139 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 140 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 141 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 142
 143 /* MIPS32/64 EntryLo bit definitions */
 144 #define MIPS_ENTRYLO_PFN_SHIFT  6
 145 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 146 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 147
 148 /*
 149  * Values for PageMask register
 150  */
 151 #ifdef CONFIG_CPU_VR41XX
 152
 153 /* Why doesn't stupidity hurt ... */
 154
 155 #define PM_1K           0x00000000
 156 #define PM_4K           0x00001800
 157 #define PM_16K          0x00007800
 158 #define PM_64K          0x0001f800
 159 #define PM_256K         0x0007f800
 160
 161 #else
 162
 163 #define PM_4K           0x00000000
 164 #define PM_8K           0x00002000
 165 #define PM_16K          0x00006000
 166 #define PM_32K          0x0000e000
 167 #define PM_64K          0x0001e000
 168 #define PM_128K         0x0003e000
 169 #define PM_256K         0x0007e000
 170 #define PM_512K         0x000fe000
 171 #define PM_1M           0x001fe000
 172 #define PM_2M           0x003fe000
 173 #define PM_4M           0x007fe000
 174 #define PM_8M           0x00ffe000
 175 #define PM_16M          0x01ffe000
 176 #define PM_32M          0x03ffe000
 177 #define PM_64M          0x07ffe000
 178 #define PM_256M         0x1fffe000
 179 #define PM_1G           0x7fffe000
 180
 181 #endif
 182
 183 /*
 184  * Default page size for a given kernel configuration
 185  */
 186 #ifdef CONFIG_PAGE_SIZE_4KB
 187 #define PM_DEFAULT_MASK PM_4K
 188 #elif defined(CONFIG_PAGE_SIZE_8KB)
 189 #define PM_DEFAULT_MASK PM_8K
 190 #elif defined(CONFIG_PAGE_SIZE_16KB)
 191 #define PM_DEFAULT_MASK PM_16K
 192 #elif defined(CONFIG_PAGE_SIZE_32KB)
 193 #define PM_DEFAULT_MASK PM_32K
 194 #elif defined(CONFIG_PAGE_SIZE_64KB)
 195 #define PM_DEFAULT_MASK PM_64K
 196 #else
 197 #error Bad page size configuration!
 198 #endif
 199
 200 /*
 201  * Default huge tlb size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_HUGE_MASK    PM_1M
 205 #elif defined(CONFIG_PAGE_SIZE_8KB)
 206 #define PM_HUGE_MASK    PM_4M
 207 #elif defined(CONFIG_PAGE_SIZE_16KB)
 208 #define PM_HUGE_MASK    PM_16M
 209 #elif defined(CONFIG_PAGE_SIZE_32KB)
 210 #define PM_HUGE_MASK    PM_64M
 211 #elif defined(CONFIG_PAGE_SIZE_64KB)
 212 #define PM_HUGE_MASK    PM_256M
 213 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 214 #error Bad page size configuration for hugetlbfs!
 215 #endif
 216
 217 /*
 218  * Values used for computation of new tlb entries
 219  */
 220 #define PL_4K           12
 221 #define PL_16K          14
 222 #define PL_64K          16
 223 #define PL_256K         18
 224 #define PL_1M           20
 225 #define PL_4M           22
 226 #define PL_16M          24
 227 #define PL_64M          26
 228 #define PL_256M         28
 229
 230 /*
 231  * PageGrain bits
 232  */
 233 #define PG_RIE          (_ULCAST_(1) <<  31)
 234 #define PG_XIE          (_ULCAST_(1) <<  30)
 235 #define PG_ELPA         (_ULCAST_(1) <<  29)
 236 #define PG_ESP          (_ULCAST_(1) <<  28)
 237 #define PG_IEC          (_ULCAST_(1) <<  27)
 238
 239 /* MIPS32/64 EntryHI bit definitions */
 240 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 241 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 242 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 243
 244 /*
 245  * R4x00 interrupt enable / cause bits
 246  */
 247 #define IE_SW0          (_ULCAST_(1) <<  8)
 248 #define IE_SW1          (_ULCAST_(1) <<  9)
 249 #define IE_IRQ0         (_ULCAST_(1) << 10)
 250 #define IE_IRQ1         (_ULCAST_(1) << 11)
 251 #define IE_IRQ2         (_ULCAST_(1) << 12)
 252 #define IE_IRQ3         (_ULCAST_(1) << 13)
 253 #define IE_IRQ4         (_ULCAST_(1) << 14)
 254 #define IE_IRQ5         (_ULCAST_(1) << 15)
 255
 256 /*
 257  * R4x00 interrupt cause bits
 258  */
 259 #define C_SW0           (_ULCAST_(1) <<  8)
 260 #define C_SW1           (_ULCAST_(1) <<  9)
 261 #define C_IRQ0          (_ULCAST_(1) << 10)
 262 #define C_IRQ1          (_ULCAST_(1) << 11)
 263 #define C_IRQ2          (_ULCAST_(1) << 12)
 264 #define C_IRQ3          (_ULCAST_(1) << 13)
 265 #define C_IRQ4          (_ULCAST_(1) << 14)
 266 #define C_IRQ5          (_ULCAST_(1) << 15)
 267
 268 /*
 269  * Bitfields in the R4xx0 cp0 status register
 270  */
 271 #define ST0_IE                  0x00000001
 272 #define ST0_EXL                 0x00000002
 273 #define ST0_ERL                 0x00000004
 274 #define ST0_KSU                 0x00000018
 275 #  define KSU_USER              0x00000010
 276 #  define KSU_SUPERVISOR        0x00000008
 277 #  define KSU_KERNEL            0x00000000
 278 #define ST0_UX                  0x00000020
 279 #define ST0_SX                  0x00000040
 280 #define ST0_KX                  0x00000080
 281 #define ST0_DE                  0x00010000
 282 #define ST0_CE                  0x00020000
 283
 284 /*
 285  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 286  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 287  * processors.
 288  */
 289 #define ST0_CO                  0x08000000
 290
 291 /*
 292  * Bitfields in the R[23]000 cp0 status register.
 293  */
 294 #define ST0_IEC                 0x00000001
 295 #define ST0_KUC                 0x00000002
 296 #define ST0_IEP                 0x00000004
 297 #define ST0_KUP                 0x00000008
 298 #define ST0_IEO                 0x00000010
 299 #define ST0_KUO                 0x00000020
 300 /* bits 6 & 7 are reserved on R[23]000 */
 301 #define ST0_ISC                 0x00010000
 302 #define ST0_SWC                 0x00020000
 303 #define ST0_CM                  0x00080000
 304
 305 /*
 306  * Bits specific to the R4640/R4650
 307  */
 308 #define ST0_UM                  (_ULCAST_(1) <<  4)
 309 #define ST0_IL                  (_ULCAST_(1) << 23)
 310 #define ST0_DL                  (_ULCAST_(1) << 24)
 311
 312 /*
 313  * Enable the MIPS MDMX and DSP ASEs
 314  */
 315 #define ST0_MX                  0x01000000
 316
 317 /*
 318  * Status register bits available in all MIPS CPUs.
 319  */
 320 #define ST0_IM                  0x0000ff00
 321 #define  STATUSB_IP0            8
 322 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 323 #define  STATUSB_IP1            9
 324 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 325 #define  STATUSB_IP2            10
 326 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 327 #define  STATUSB_IP3            11
 328 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 329 #define  STATUSB_IP4            12
 330 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 331 #define  STATUSB_IP5            13
 332 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 333 #define  STATUSB_IP6            14
 334 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 335 #define  STATUSB_IP7            15
 336 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 337 #define  STATUSB_IP8            0
 338 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 339 #define  STATUSB_IP9            1
 340 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 341 #define  STATUSB_IP10           2
 342 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 343 #define  STATUSB_IP11           3
 344 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 345 #define  STATUSB_IP12           4
 346 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 347 #define  STATUSB_IP13           5
 348 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 349 #define  STATUSB_IP14           6
 350 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 351 #define  STATUSB_IP15           7
 352 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 353 #define ST0_CH                  0x00040000
 354 #define ST0_NMI                 0x00080000
 355 #define ST0_SR                  0x00100000
 356 #define ST0_TS                  0x00200000
 357 #define ST0_BEV                 0x00400000
 358 #define ST0_RE                  0x02000000
 359 #define ST0_FR                  0x04000000
 360 #define ST0_CU                  0xf0000000
 361 #define ST0_CU0                 0x10000000
 362 #define ST0_CU1                 0x20000000
 363 #define ST0_CU2                 0x40000000
 364 #define ST0_CU3                 0x80000000
 365 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 366
 367 /*
 368  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 369  */
 370 #define INTCTLB_IPFDC           23
 371 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 372 #define INTCTLB_IPPCI           26
 373 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 374 #define INTCTLB_IPTI            29
 375 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 376
 377 /*
 378  * Bitfields and bit numbers in the coprocessor 0 cause register.
 379  *
 380  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 381  */
 382 #define CAUSEB_EXCCODE          2
 383 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 384 #define CAUSEB_IP               8
 385 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 386 #define  CAUSEB_IP0             8
 387 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 388 #define  CAUSEB_IP1             9
 389 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 390 #define  CAUSEB_IP2             10
 391 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 392 #define  CAUSEB_IP3             11
 393 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 394 #define  CAUSEB_IP4             12
 395 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 396 #define  CAUSEB_IP5             13
 397 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 398 #define  CAUSEB_IP6             14
 399 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 400 #define  CAUSEB_IP7             15
 401 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 402 #define CAUSEB_FDCI             21
 403 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 404 #define CAUSEB_WP               22
 405 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 406 #define CAUSEB_IV               23
 407 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 408 #define CAUSEB_PCI              26
 409 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 410 #define CAUSEB_DC               27
 411 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 412 #define CAUSEB_CE               28
 413 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 414 #define CAUSEB_TI               30
 415 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 416 #define CAUSEB_BD               31
 417 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 418
 419 /*
 420  * Cause.ExcCode trap codes.
 421  */
 422 #define EXCCODE_INT             0       /* Interrupt pending */
 423 #define EXCCODE_MOD             1       /* TLB modified fault */
 424 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 425 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 426 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 427 #define EXCCODE_ADES            5       /* Address error on a store */
 428 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 429 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 430 #define EXCCODE_SYS             8       /* System call */
 431 #define EXCCODE_BP              9       /* Breakpoint */
 432 #define EXCCODE_RI              10      /* Reserved instruction exception */
 433 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 434 #define EXCCODE_OV              12      /* Arithmetic overflow */
 435 #define EXCCODE_TR              13      /* Trap instruction */
 436 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 437 #define EXCCODE_FPE             15      /* Floating point exception */
 438 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 439 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 440 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 441 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 442 #define EXCCODE_WATCH           23      /* Watch address reference */
 443 #define EXCCODE_MCHECK          24      /* Machine check */
 444 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 445 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 446 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 447
 448 /* Implementation specific trap codes used by MIPS cores */
 449 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 450
 451 /*
 452  * Bits in the coprocessor 0 config register.
 453  */
 454 /* Generic bits.  */
 455 #define CONF_CM_CACHABLE_NO_WA          0
 456 #define CONF_CM_CACHABLE_WA             1
 457 #define CONF_CM_UNCACHED                2
 458 #define CONF_CM_CACHABLE_NONCOHERENT    3
 459 #define CONF_CM_CACHABLE_CE             4
 460 #define CONF_CM_CACHABLE_COW            5
 461 #define CONF_CM_CACHABLE_CUW            6
 462 #define CONF_CM_CACHABLE_ACCELERATED    7
 463 #define CONF_CM_CMASK                   7
 464 #define CONF_BE                 (_ULCAST_(1) << 15)
 465
 466 /* Bits common to various processors.  */
 467 #define CONF_CU                 (_ULCAST_(1) <<  3)
 468 #define CONF_DB                 (_ULCAST_(1) <<  4)
 469 #define CONF_IB                 (_ULCAST_(1) <<  5)
 470 #define CONF_DC                 (_ULCAST_(7) <<  6)
 471 #define CONF_IC                 (_ULCAST_(7) <<  9)
 472 #define CONF_EB                 (_ULCAST_(1) << 13)
 473 #define CONF_EM                 (_ULCAST_(1) << 14)
 474 #define CONF_SM                 (_ULCAST_(1) << 16)
 475 #define CONF_SC                 (_ULCAST_(1) << 17)
 476 #define CONF_EW                 (_ULCAST_(3) << 18)
 477 #define CONF_EP                 (_ULCAST_(15)<< 24)
 478 #define CONF_EC                 (_ULCAST_(7) << 28)
 479 #define CONF_CM                 (_ULCAST_(1) << 31)
 480
 481 /* Bits specific to the R4xx0.  */
 482 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 483 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 484 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 485
 486 /* Bits specific to the R5000.  */
 487 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 488 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 489
 490 /* Bits specific to the RM7000.  */
 491 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 492 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 493 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 494 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 495 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 496 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 497
 498 /* Bits specific to the R10000.  */
 499 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 500 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 501 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 502 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 503 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 504 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 505 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 506 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 507 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 508 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 509 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 510
 511 /* Bits specific to the VR41xx.  */
 512 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 513 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 514 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 515 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 516 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 517
 518 /* Bits specific to the R30xx.  */
 519 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 520 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 521 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 522 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 523 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 524 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 525 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 526 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 527 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 528
 529 /* Bits specific to the TX49.  */
 530 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 531 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 532 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 533 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 534
 535 /* Bits specific to the MIPS32/64 PRA.  */
 536 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 537 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 538 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 539 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 540 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 541 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 542 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 543
 544 /*
 545  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 546  */
 547 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 548 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 549 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 550 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 551 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 552 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 553 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 554 #define MIPS_CONF1_DA_SHF       7
 555 #define MIPS_CONF1_DA_SZ        3
 556 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 557 #define MIPS_CONF1_DL_SHF       10
 558 #define MIPS_CONF1_DL_SZ        3
 559 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 560 #define MIPS_CONF1_DS_SHF       13
 561 #define MIPS_CONF1_DS_SZ        3
 562 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 563 #define MIPS_CONF1_IA_SHF       16
 564 #define MIPS_CONF1_IA_SZ        3
 565 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 566 #define MIPS_CONF1_IL_SHF       19
 567 #define MIPS_CONF1_IL_SZ        3
 568 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 569 #define MIPS_CONF1_IS_SHF       22
 570 #define MIPS_CONF1_IS_SZ        3
 571 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 572 #define MIPS_CONF1_TLBS_SHIFT   (25)
 573 #define MIPS_CONF1_TLBS_SIZE    (6)
 574 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 575
 576 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 577 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 578 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 579 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 580 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 581 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 582 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 583 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 584
 585 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 586 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 587 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 588 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 589 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 590 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 591 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 592 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 593 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 594 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 595 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 596 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 597 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 598 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 599 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 600 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 601 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 602 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 603 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 604 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 605 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 606 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 607 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 608 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 609 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 610 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 611 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 612
 613 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 614 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 615 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 616 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 617 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 618 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 619 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 620 /* bits 10:8 in FTLB-only configurations */
 621 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 622 /* bits 12:8 in VTLB-FTLB only configurations */
 623 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 624 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 625 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 626 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 627 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 628 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 629 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 630 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 631 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 632 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 633 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 634 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 635
 636 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 637 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 638 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 639 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 640 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 641 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 642 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 643 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 644 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 645 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 646 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 647 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 648
 649 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 650 /* proAptiv FTLB on/off bit */
 651 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 652 /* Loongson-3 FTLB on/off bit */
 653 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 654 /* FTLB probability bits */
 655 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 656
 657 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 658
 659 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 660
 661 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 662 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 663
 664 /* WatchLo* register definitions */
 665 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 666
 667 /* WatchHi* register definitions */
 668 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 669 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 670 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 671 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 672 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 673 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 674 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 675 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 676 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 677 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 678 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 679 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 680 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 681
 682 /* MAAR bit definitions */
 683 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 684 #define MIPS_MAAR_ADDR_SHIFT    12
 685 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 686 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 687
 688 /* EBase bit definitions */
 689 #define MIPS_EBASE_CPUNUM_SHIFT 0
 690 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 691 #define MIPS_EBASE_WG_SHIFT     11
 692 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 693 #define MIPS_EBASE_BASE_SHIFT   12
 694 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 695
 696 /* CMGCRBase bit definitions */
 697 #define MIPS_CMGCRB_BASE        11
 698 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 699
 700 /*
 701  * Bits in the MIPS32 Memory Segmentation registers.
 702  */
 703 #define MIPS_SEGCFG_PA_SHIFT    9
 704 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 705 #define MIPS_SEGCFG_AM_SHIFT    4
 706 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 707 #define MIPS_SEGCFG_EU_SHIFT    3
 708 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 709 #define MIPS_SEGCFG_C_SHIFT     0
 710 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 711
 712 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 713 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 714 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 715 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 716 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 717 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 718 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 719
 720 #define MIPS_PWFIELD_GDI_SHIFT  24
 721 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 722 #define MIPS_PWFIELD_UDI_SHIFT  18
 723 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 724 #define MIPS_PWFIELD_MDI_SHIFT  12
 725 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 726 #define MIPS_PWFIELD_PTI_SHIFT  6
 727 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 728 #define MIPS_PWFIELD_PTEI_SHIFT 0
 729 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 730
 731 #define MIPS_PWSIZE_PS_SHIFT    30
 732 #define MIPS_PWSIZE_PS_MASK     0x40000000
 733 #define MIPS_PWSIZE_GDW_SHIFT   24
 734 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 735 #define MIPS_PWSIZE_UDW_SHIFT   18
 736 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 737 #define MIPS_PWSIZE_MDW_SHIFT   12
 738 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 739 #define MIPS_PWSIZE_PTW_SHIFT   6
 740 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 741 #define MIPS_PWSIZE_PTEW_SHIFT  0
 742 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 743
 744 #define MIPS_PWCTL_PWEN_SHIFT   31
 745 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 746 #define MIPS_PWCTL_XK_SHIFT     28
 747 #define MIPS_PWCTL_XK_MASK      0x10000000
 748 #define MIPS_PWCTL_XS_SHIFT     27
 749 #define MIPS_PWCTL_XS_MASK      0x08000000
 750 #define MIPS_PWCTL_XU_SHIFT     26
 751 #define MIPS_PWCTL_XU_MASK      0x04000000
 752 #define MIPS_PWCTL_DPH_SHIFT    7
 753 #define MIPS_PWCTL_DPH_MASK     0x00000080
 754 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 755 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 756 #define MIPS_PWCTL_PSN_SHIFT    0
 757 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 758
 759 /* GuestCtl0 fields */
 760 #define MIPS_GCTL0_GM_SHIFT     31
 761 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 762 #define MIPS_GCTL0_RI_SHIFT     30
 763 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 764 #define MIPS_GCTL0_MC_SHIFT     29
 765 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 766 #define MIPS_GCTL0_CP0_SHIFT    28
 767 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 768 #define MIPS_GCTL0_AT_SHIFT     26
 769 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 770 #define MIPS_GCTL0_GT_SHIFT     25
 771 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 772 #define MIPS_GCTL0_CG_SHIFT     24
 773 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 774 #define MIPS_GCTL0_CF_SHIFT     23
 775 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 776 #define MIPS_GCTL0_G1_SHIFT     22
 777 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 778 #define MIPS_GCTL0_G0E_SHIFT    19
 779 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 780 #define MIPS_GCTL0_PT_SHIFT     18
 781 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 782 #define MIPS_GCTL0_RAD_SHIFT    9
 783 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 784 #define MIPS_GCTL0_DRG_SHIFT    8
 785 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 786 #define MIPS_GCTL0_G2_SHIFT     7
 787 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 788 #define MIPS_GCTL0_GEXC_SHIFT   2
 789 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 790 #define MIPS_GCTL0_SFC2_SHIFT   1
 791 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 792 #define MIPS_GCTL0_SFC1_SHIFT   0
 793 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 794
 795 /* GuestCtl0.AT Guest address translation control */
 796 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 797 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 798
 799 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 800 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 801 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 802 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 803 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 804 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 805 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 806 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 807
 808 /* GuestCtl0Ext fields */
 809 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 810 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 811 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 812 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 813 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 814 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 815 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 816 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 817 #define MIPS_GCTL0EXT_OG_SHIFT  2
 818 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 819 #define MIPS_GCTL0EXT_BG_SHIFT  1
 820 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 821 #define MIPS_GCTL0EXT_MG_SHIFT  0
 822 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 823
 824 /* GuestCtl0Ext.RPW Root page walk configuration */
 825 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 826 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 827 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 828
 829 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 830 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 831 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 832
 833 /* GuestCtl1 fields */
 834 #define MIPS_GCTL1_ID_SHIFT     0
 835 #define MIPS_GCTL1_ID_WIDTH     8
 836 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 837 #define MIPS_GCTL1_RID_SHIFT    16
 838 #define MIPS_GCTL1_RID_WIDTH    8
 839 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 840 #define MIPS_GCTL1_EID_SHIFT    24
 841 #define MIPS_GCTL1_EID_WIDTH    8
 842 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 843
 844 /* GuestID reserved for root context */
 845 #define MIPS_GCTL1_ROOT_GUESTID 0
 846
 847 /* CDMMBase register bit definitions */
 848 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 849 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 850 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 851 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 852 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 853 #define MIPS_CDMMBASE_ADDR_START 15
 854
 855 /* RDHWR register numbers */
 856 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 857 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 858 #define MIPS_HWR_CC             2       /* Cycle counter */
 859 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 860 #define MIPS_HWR_ULR            29      /* UserLocal */
 861 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 862 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 863
 864 /* Bits in HWREna register */
 865 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 866 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 867 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 868 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 869 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 870 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 871 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 872
 873 /*
 874  * Bitfields in the TX39 family CP0 Configuration Register 3
 875  */
 876 #define TX39_CONF_ICS_SHIFT     19
 877 #define TX39_CONF_ICS_MASK      0x00380000
 878 #define TX39_CONF_ICS_1KB       0x00000000
 879 #define TX39_CONF_ICS_2KB       0x00080000
 880 #define TX39_CONF_ICS_4KB       0x00100000
 881 #define TX39_CONF_ICS_8KB       0x00180000
 882 #define TX39_CONF_ICS_16KB      0x00200000
 883
 884 #define TX39_CONF_DCS_SHIFT     16
 885 #define TX39_CONF_DCS_MASK      0x00070000
 886 #define TX39_CONF_DCS_1KB       0x00000000
 887 #define TX39_CONF_DCS_2KB       0x00010000
 888 #define TX39_CONF_DCS_4KB       0x00020000
 889 #define TX39_CONF_DCS_8KB       0x00030000
 890 #define TX39_CONF_DCS_16KB      0x00040000
 891
 892 #define TX39_CONF_CWFON         0x00004000
 893 #define TX39_CONF_WBON          0x00002000
 894 #define TX39_CONF_RF_SHIFT      10
 895 #define TX39_CONF_RF_MASK       0x00000c00
 896 #define TX39_CONF_DOZE          0x00000200
 897 #define TX39_CONF_HALT          0x00000100
 898 #define TX39_CONF_LOCK          0x00000080
 899 #define TX39_CONF_ICE           0x00000020
 900 #define TX39_CONF_DCE           0x00000010
 901 #define TX39_CONF_IRSIZE_SHIFT  2
 902 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 903 #define TX39_CONF_DRSIZE_SHIFT  0
 904 #define TX39_CONF_DRSIZE_MASK   0x00000003
 905
 906 /*
 907  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 908  */
 909 /* Disable Branch Target Address Cache */
 910 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 911 /* Enable Branch Prediction Global History */
 912 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 913 /* Disable Branch Return Cache */
 914 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 915
 916 /* Flush ITLB */
 917 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 918 /* Flush DTLB */
 919 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 920 /* Flush VTLB */
 921 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 922 /* Flush FTLB */
 923 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 924
 925 /*
 926  * Coprocessor 1 (FPU) register names
 927  */
 928 #define CP1_REVISION    $0
 929 #define CP1_UFR         $1
 930 #define CP1_UNFR        $4
 931 #define CP1_FCCR        $25
 932 #define CP1_FEXR        $26
 933 #define CP1_FENR        $28
 934 #define CP1_STATUS      $31
 935
 936
 937 /*
 938  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 939  */
 940 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 941 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 942 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 943 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 944 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 945 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 946 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 947 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 948 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 949 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 950
 951 /*
 952  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 953  */
 954 #define MIPS_FCCR_CONDX_S       0
 955 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 956 #define MIPS_FCCR_COND0_S       0
 957 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 958 #define MIPS_FCCR_COND1_S       1
 959 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 960 #define MIPS_FCCR_COND2_S       2
 961 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 962 #define MIPS_FCCR_COND3_S       3
 963 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 964 #define MIPS_FCCR_COND4_S       4
 965 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 966 #define MIPS_FCCR_COND5_S       5
 967 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 968 #define MIPS_FCCR_COND6_S       6
 969 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 970 #define MIPS_FCCR_COND7_S       7
 971 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 972
 973 /*
 974  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 975  */
 976 #define MIPS_FENR_FS_S          2
 977 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 978
 979 /*
 980  * FPU Status Register Values
 981  */
 982 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 983 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 984
 985 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 986 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 987
 988 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 989 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 990 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 991 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 992 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 993 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 994 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 995 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 996 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 997 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 998 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 999 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1000 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1001 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1002 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1003 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1004
1005 /*
1006  * Bits 22:20 of the FPU Status Register will be read as 0,
1007  * and should be written as zero.
1008  */
1009 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1010
1011 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1012 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1013
1014 /*
1015  * X the exception cause indicator
1016  * E the exception enable
1017  * S the sticky/flag bit
1018 */
1019 #define FPU_CSR_ALL_X   0x0003f000
1020 #define FPU_CSR_UNI_X   0x00020000
1021 #define FPU_CSR_INV_X   0x00010000
1022 #define FPU_CSR_DIV_X   0x00008000
1023 #define FPU_CSR_OVF_X   0x00004000
1024 #define FPU_CSR_UDF_X   0x00002000
1025 #define FPU_CSR_INE_X   0x00001000
1026
1027 #define FPU_CSR_ALL_E   0x00000f80
1028 #define FPU_CSR_INV_E   0x00000800
1029 #define FPU_CSR_DIV_E   0x00000400
1030 #define FPU_CSR_OVF_E   0x00000200
1031 #define FPU_CSR_UDF_E   0x00000100
1032 #define FPU_CSR_INE_E   0x00000080
1033
1034 #define FPU_CSR_ALL_S   0x0000007c
1035 #define FPU_CSR_INV_S   0x00000040
1036 #define FPU_CSR_DIV_S   0x00000020
1037 #define FPU_CSR_OVF_S   0x00000010
1038 #define FPU_CSR_UDF_S   0x00000008
1039 #define FPU_CSR_INE_S   0x00000004
1040
1041 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1042 #define FPU_CSR_RM      0x00000003
1043 #define FPU_CSR_RN      0x0     /* nearest */
1044 #define FPU_CSR_RZ      0x1     /* towards zero */
1045 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1046 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1047
1048
1049 #ifndef __ASSEMBLY__
1050
1051 /*
1052  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1053  */
1054 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1055     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1056 #define get_isa16_mode(x)               ((x) & 0x1)
1057 #define msk_isa16_mode(x)               ((x) & ~0x1)
1058 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1059 #else
1060 #define get_isa16_mode(x)               0
1061 #define msk_isa16_mode(x)               (x)
1062 #define set_isa16_mode(x)               do { } while(0)
1063 #endif
1064
1065 /*
1066  * microMIPS instructions can be 16-bit or 32-bit in length. This
1067  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1068  */
1069 static inline int mm_insn_16bit(u16 insn)
1070 {
1071         u16 opcode = (insn >> 10) & 0x7;
1072
1073         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1074 }
1075
1076 /*
1077  * Helper macros for generating raw instruction encodings in inline asm.
1078  */
1079 #ifdef CONFIG_CPU_MICROMIPS
1080 #define _ASM_INSN16_IF_MM(_enc)                 \
1081         ".insn\n\t"                             \
1082         ".hword (" #_enc ")\n\t"
1083 #define _ASM_INSN32_IF_MM(_enc)                 \
1084         ".insn\n\t"                             \
1085         ".hword ((" #_enc ") >> 16)\n\t"        \
1086         ".hword ((" #_enc ") & 0xffff)\n\t"
1087 #else
1088 #define _ASM_INSN_IF_MIPS(_enc)                 \
1089         ".insn\n\t"                             \
1090         ".word (" #_enc ")\n\t"
1091 #endif
1092
1093 #ifndef _ASM_INSN16_IF_MM
1094 #define _ASM_INSN16_IF_MM(_enc)
1095 #endif
1096 #ifndef _ASM_INSN32_IF_MM
1097 #define _ASM_INSN32_IF_MM(_enc)
1098 #endif
1099 #ifndef _ASM_INSN_IF_MIPS
1100 #define _ASM_INSN_IF_MIPS(_enc)
1101 #endif
1102
1103 /*
1104  * TLB Invalidate Flush
1105  */
1106 static inline void tlbinvf(void)
1107 {
1108         __asm__ __volatile__(
1109                 ".set push\n\t"
1110                 ".set noreorder\n\t"
1111                 "# tlbinvf\n\t"
1112                 _ASM_INSN_IF_MIPS(0x42000004)
1113                 _ASM_INSN32_IF_MM(0x0000537c)
1114                 ".set pop");
1115 }
1116
1117
1118 /*
1119  * Functions to access the R10000 performance counters.  These are basically
1120  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1121  * performance counter number encoded into bits 1 ... 5 of the instruction.
1122  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1123  * disassembler these will look like an access to sel 0 or 1.
1124  */
1125 #define read_r10k_perf_cntr(counter)                            \
1126 ({                                                              \
1127         unsigned int __res;                                     \
1128         __asm__ __volatile__(                                   \
1129         "mfpc\t%0, %1"                                          \
1130         : "=r" (__res)                                          \
1131         : "i" (counter));                                       \
1132                                                                 \
1133         __res;                                                  \
1134 })
1135
1136 #define write_r10k_perf_cntr(counter,val)                       \
1137 do {                                                            \
1138         __asm__ __volatile__(                                   \
1139         "mtpc\t%0, %1"                                          \
1140         :                                                       \
1141         : "r" (val), "i" (counter));                            \
1142 } while (0)
1143
1144 #define read_r10k_perf_event(counter)                           \
1145 ({                                                              \
1146         unsigned int __res;                                     \
1147         __asm__ __volatile__(                                   \
1148         "mfps\t%0, %1"                                          \
1149         : "=r" (__res)                                          \
1150         : "i" (counter));                                       \
1151                                                                 \
1152         __res;                                                  \
1153 })
1154
1155 #define write_r10k_perf_cntl(counter,val)                       \
1156 do {                                                            \
1157         __asm__ __volatile__(                                   \
1158         "mtps\t%0, %1"                                          \
1159         :                                                       \
1160         : "r" (val), "i" (counter));                            \
1161 } while (0)
1162
1163
1164 /*
1165  * Macros to access the system control coprocessor
1166  */
1167
1168 #define __read_32bit_c0_register(source, sel)                           \
1169 ({ unsigned int __res;                                                  \
1170         if (sel == 0)                                                   \
1171                 __asm__ __volatile__(                                   \
1172                         "mfc0\t%0, " #source "\n\t"                     \
1173                         : "=r" (__res));                                \
1174         else                                                            \
1175                 __asm__ __volatile__(                                   \
1176                         ".set\tmips32\n\t"                              \
1177                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1178                         ".set\tmips0\n\t"                               \
1179                         : "=r" (__res));                                \
1180         __res;                                                          \
1181 })
1182
1183 #define __read_64bit_c0_register(source, sel)                           \
1184 ({ unsigned long long __res;                                            \
1185         if (sizeof(unsigned long) == 4)                                 \
1186                 __res = __read_64bit_c0_split(source, sel);             \
1187         else if (sel == 0)                                              \
1188                 __asm__ __volatile__(                                   \
1189                         ".set\tmips3\n\t"                               \
1190                         "dmfc0\t%0, " #source "\n\t"                    \
1191                         ".set\tmips0"                                   \
1192                         : "=r" (__res));                                \
1193         else                                                            \
1194                 __asm__ __volatile__(                                   \
1195                         ".set\tmips64\n\t"                              \
1196                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1197                         ".set\tmips0"                                   \
1198                         : "=r" (__res));                                \
1199         __res;                                                          \
1200 })
1201
1202 #define __write_32bit_c0_register(register, sel, value)                 \
1203 do {                                                                    \
1204         if (sel == 0)                                                   \
1205                 __asm__ __volatile__(                                   \
1206                         "mtc0\t%z0, " #register "\n\t"                  \
1207                         : : "Jr" ((unsigned int)(value)));              \
1208         else                                                            \
1209                 __asm__ __volatile__(                                   \
1210                         ".set\tmips32\n\t"                              \
1211                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1212                         ".set\tmips0"                                   \
1213                         : : "Jr" ((unsigned int)(value)));              \
1214 } while (0)
1215
1216 #define __write_64bit_c0_register(register, sel, value)                 \
1217 do {                                                                    \
1218         if (sizeof(unsigned long) == 4)                                 \
1219                 __write_64bit_c0_split(register, sel, value);           \
1220         else if (sel == 0)                                              \
1221                 __asm__ __volatile__(                                   \
1222                         ".set\tmips3\n\t"                               \
1223                         "dmtc0\t%z0, " #register "\n\t"                 \
1224                         ".set\tmips0"                                   \
1225                         : : "Jr" (value));                              \
1226         else                                                            \
1227                 __asm__ __volatile__(                                   \
1228                         ".set\tmips64\n\t"                              \
1229                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1230                         ".set\tmips0"                                   \
1231                         : : "Jr" (value));                              \
1232 } while (0)
1233
1234 #define __read_ulong_c0_register(reg, sel)                              \
1235         ((sizeof(unsigned long) == 4) ?                                 \
1236         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1237         (unsigned long) __read_64bit_c0_register(reg, sel))
1238
1239 #define __write_ulong_c0_register(reg, sel, val)                        \
1240 do {                                                                    \
1241         if (sizeof(unsigned long) == 4)                                 \
1242                 __write_32bit_c0_register(reg, sel, val);               \
1243         else                                                            \
1244                 __write_64bit_c0_register(reg, sel, val);               \
1245 } while (0)
1246
1247 /*
1248  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1249  */
1250 #define __read_32bit_c0_ctrl_register(source)                           \
1251 ({ unsigned int __res;                                                  \
1252         __asm__ __volatile__(                                           \
1253                 "cfc0\t%0, " #source "\n\t"                             \
1254                 : "=r" (__res));                                        \
1255         __res;                                                          \
1256 })
1257
1258 #define __write_32bit_c0_ctrl_register(register, value)                 \
1259 do {                                                                    \
1260         __asm__ __volatile__(                                           \
1261                 "ctc0\t%z0, " #register "\n\t"                          \
1262                 : : "Jr" ((unsigned int)(value)));                      \
1263 } while (0)
1264
1265 /*
1266  * These versions are only needed for systems with more than 38 bits of
1267  * physical address space running the 32-bit kernel.  That's none atm :-)
1268  */
1269 #define __read_64bit_c0_split(source, sel)                              \
1270 ({                                                                      \
1271         unsigned long long __val;                                       \
1272         unsigned long __flags;                                          \
1273                                                                         \
1274         local_irq_save(__flags);                                        \
1275         if (sel == 0)                                                   \
1276                 __asm__ __volatile__(                                   \
1277                         ".set\tmips64\n\t"                              \
1278                         "dmfc0\t%M0, " #source "\n\t"                   \
1279                         "dsll\t%L0, %M0, 32\n\t"                        \
1280                         "dsra\t%M0, %M0, 32\n\t"                        \
1281                         "dsra\t%L0, %L0, 32\n\t"                        \
1282                         ".set\tmips0"                                   \
1283                         : "=r" (__val));                                \
1284         else                                                            \
1285                 __asm__ __volatile__(                                   \
1286                         ".set\tmips64\n\t"                              \
1287                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1288                         "dsll\t%L0, %M0, 32\n\t"                        \
1289                         "dsra\t%M0, %M0, 32\n\t"                        \
1290                         "dsra\t%L0, %L0, 32\n\t"                        \
1291                         ".set\tmips0"                                   \
1292                         : "=r" (__val));                                \
1293         local_irq_restore(__flags);                                     \
1294                                                                         \
1295         __val;                                                          \
1296 })
1297
1298 #define __write_64bit_c0_split(source, sel, val)                        \
1299 do {                                                                    \
1300         unsigned long __flags;                                          \
1301                                                                         \
1302         local_irq_save(__flags);                                        \
1303         if (sel == 0)                                                   \
1304                 __asm__ __volatile__(                                   \
1305                         ".set\tmips64\n\t"                              \
1306                         "dsll\t%L0, %L0, 32\n\t"                        \
1307                         "dsrl\t%L0, %L0, 32\n\t"                        \
1308                         "dsll\t%M0, %M0, 32\n\t"                        \
1309                         "or\t%L0, %L0, %M0\n\t"                         \
1310                         "dmtc0\t%L0, " #source "\n\t"                   \
1311                         ".set\tmips0"                                   \
1312                         : : "r" (val));                                 \
1313         else                                                            \
1314                 __asm__ __volatile__(                                   \
1315                         ".set\tmips64\n\t"                              \
1316                         "dsll\t%L0, %L0, 32\n\t"                        \
1317                         "dsrl\t%L0, %L0, 32\n\t"                        \
1318                         "dsll\t%M0, %M0, 32\n\t"                        \
1319                         "or\t%L0, %L0, %M0\n\t"                         \
1320                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1321                         ".set\tmips0"                                   \
1322                         : : "r" (val));                                 \
1323         local_irq_restore(__flags);                                     \
1324 } while (0)
1325
1326 #define __readx_32bit_c0_register(source)                               \
1327 ({                                                                      \
1328         unsigned int __res;                                             \
1329                                                                         \
1330         __asm__ __volatile__(                                           \
1331         "       .set    push                                    \n"     \
1332         "       .set    noat                                    \n"     \
1333         "       .set    mips32r2                                \n"     \
1334         "       # mfhc0 $1, %1                                  \n"     \
1335         _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
1336         _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
1337         "       move    %0, $1                                  \n"     \
1338         "       .set    pop                                     \n"     \
1339         : "=r" (__res)                                                  \
1340         : "i" (source));                                                \
1341         __res;                                                          \
1342 })
1343
1344 #define __writex_32bit_c0_register(register, value)                     \
1345 do {                                                                    \
1346         __asm__ __volatile__(                                           \
1347         "       .set    push                                    \n"     \
1348         "       .set    noat                                    \n"     \
1349         "       .set    mips32r2                                \n"     \
1350         "       move    $1, %0                                  \n"     \
1351         "       # mthc0 $1, %1                                  \n"     \
1352         _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
1353         _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
1354         "       .set    pop                                     \n"     \
1355         :                                                               \
1356         : "r" (value), "i" (register));                                 \
1357 } while (0)
1358
1359 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1360 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1361
1362 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1363 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1364
1365 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1366 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1367
1368 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1369 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1370
1371 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1372 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1373
1374 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1375 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1376
1377 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1378 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1379
1380 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1381 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1382
1383 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1384 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1385
1386 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1387 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1388
1389 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1390 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1391
1392 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1393 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1394
1395 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1396 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1397
1398 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1399 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1400
1401 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1402
1403 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1404 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1405
1406 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1407 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1408
1409 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1410 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1411
1412 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1413 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1414
1415 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1416 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1417
1418 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1419 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1420
1421 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1422 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1423
1424 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1425 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1426
1427 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1428 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1429
1430 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1431 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1432
1433 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1434 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1435
1436 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1437 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1438
1439 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1440 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1441
1442 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1443 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1444
1445 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1446
1447 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1448
1449 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1450 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1451
1452 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1453 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1454
1455 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1456 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1457
1458 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1459 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1460
1461 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1462
1463 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1464
1465 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1466 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1467 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1468 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1469 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1470 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1471 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1472 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1473 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1474 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1475 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1476 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1477 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1478 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1479 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1480 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1481
1482 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1483 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1484 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1485 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1486 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1487 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1488
1489 /*
1490  * The WatchLo register.  There may be up to 8 of them.
1491  */
1492 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1493 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1494 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1495 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1496 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1497 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1498 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1499 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1500 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1501 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1502 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1503 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1504 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1505 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1506 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1507 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1508
1509 /*
1510  * The WatchHi register.  There may be up to 8 of them.
1511  */
1512 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1513 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1514 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1515 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1516 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1517 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1518 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1519 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1520
1521 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1522 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1523 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1524 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1525 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1526 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1527 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1528 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1529
1530 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1531 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1532
1533 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1534 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1535
1536 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1537 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1538
1539 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1540 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1541
1542 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1543 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1544 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1545
1546 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1547 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1548
1549 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1550 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1551
1552 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1553 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1554
1555 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1556 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1557
1558 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1559 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1560
1561 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1562 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1563
1564 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1565 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1566
1567 /*
1568  * MIPS32 / MIPS64 performance counters
1569  */
1570 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1571 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1572 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1573 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1574 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1575 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1576 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1577 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1578 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1579 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1580 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1581 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1582 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1583 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1584 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1585 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1586 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1587 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1588 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1589 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1590 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1591 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1592 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1593 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1594
1595 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1596 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1597
1598 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1599 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1600
1601 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1602
1603 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1604 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1605
1606 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1607 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1608
1609 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1610 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1611
1612 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1613 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1614
1615 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1616 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1617
1618 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1619 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1620
1621 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1622 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1623
1624 /* MIPSR2 */
1625 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1626 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1627
1628 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1629 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1630
1631 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1632 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1633
1634 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1635 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1636
1637 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1638 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1639
1640 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1641 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1642
1643 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1644 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1645
1646 /* MIPSR3 */
1647 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1648 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1649
1650 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1651 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1652
1653 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1654 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1655
1656 /* Hardware Page Table Walker */
1657 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1658 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1659
1660 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1661 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1662
1663 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1664 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1665
1666 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1667 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1668
1669 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1670 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1671
1672 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1673 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1674
1675 /* Cavium OCTEON (cnMIPS) */
1676 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1677 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1678
1679 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1680 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1681
1682 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1683 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1684 /*
1685  * The cacheerr registers are not standardized.  On OCTEON, they are
1686  * 64 bits wide.
1687  */
1688 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1689 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1690
1691 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1692 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1693
1694 /* BMIPS3300 */
1695 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1696 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1697
1698 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1699 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1700
1701 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1702 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1703
1704 /* BMIPS43xx */
1705 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1706 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1707
1708 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1709 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1710
1711 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1712 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1713
1714 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1715 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1716
1717 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1718 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1719
1720 /* BMIPS5000 */
1721 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1722 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1723
1724 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1725 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1726
1727 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1728 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1729
1730 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1731 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1732
1733 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1734 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1735
1736 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1737 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1738
1739 /*
1740  * Macros to access the guest system control coprocessor
1741  */
1742
1743 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1744
1745 #define __read_32bit_gc0_register(source, sel)                          \
1746 ({ int __res;                                                           \
1747         __asm__ __volatile__(                                           \
1748                 ".set\tpush\n\t"                                        \
1749                 ".set\tmips32r2\n\t"                                    \
1750                 ".set\tvirt\n\t"                                        \
1751                 "mfgc0\t%0, $%1, %2\n\t"                                \
1752                 ".set\tpop"                                             \
1753                 : "=r" (__res)                                          \
1754                 : "i" (source), "i" (sel));                             \
1755         __res;                                                          \
1756 })
1757
1758 #define __read_64bit_gc0_register(source, sel)                          \
1759 ({ unsigned long long __res;                                            \
1760         __asm__ __volatile__(                                           \
1761                 ".set\tpush\n\t"                                        \
1762                 ".set\tmips64r2\n\t"                                    \
1763                 ".set\tvirt\n\t"                                        \
1764                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1765                 ".set\tpop"                                             \
1766                 : "=r" (__res)                                          \
1767                 : "i" (source), "i" (sel));                             \
1768         __res;                                                          \
1769 })
1770
1771 #define __write_32bit_gc0_register(register, sel, value)                \
1772 do {                                                                    \
1773         __asm__ __volatile__(                                           \
1774                 ".set\tpush\n\t"                                        \
1775                 ".set\tmips32r2\n\t"                                    \
1776                 ".set\tvirt\n\t"                                        \
1777                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1778                 ".set\tpop"                                             \
1779                 : : "Jr" ((unsigned int)(value)),                       \
1780                     "i" (register), "i" (sel));                         \
1781 } while (0)
1782
1783 #define __write_64bit_gc0_register(register, sel, value)                \
1784 do {                                                                    \
1785         __asm__ __volatile__(                                           \
1786                 ".set\tpush\n\t"                                        \
1787                 ".set\tmips64r2\n\t"                                    \
1788                 ".set\tvirt\n\t"                                        \
1789                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1790                 ".set\tpop"                                             \
1791                 : : "Jr" (value),                                       \
1792                     "i" (register), "i" (sel));                         \
1793 } while (0)
1794
1795 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1796
1797 #define __read_32bit_gc0_register(source, sel)                          \
1798 ({ int __res;                                                           \
1799         __asm__ __volatile__(                                           \
1800                 ".set\tpush\n\t"                                        \
1801                 ".set\tnoat\n\t"                                        \
1802                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1803                 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
1804                 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
1805                 "move\t%0, $1\n\t"                                      \
1806                 ".set\tpop"                                             \
1807                 : "=r" (__res)                                          \
1808                 : "i" (source), "i" (sel));                             \
1809         __res;                                                          \
1810 })
1811
1812 #define __read_64bit_gc0_register(source, sel)                          \
1813 ({ unsigned long long __res;                                            \
1814         __asm__ __volatile__(                                           \
1815                 ".set\tpush\n\t"                                        \
1816                 ".set\tnoat\n\t"                                        \
1817                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1818                 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
1819                 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
1820                 "move\t%0, $1\n\t"                                      \
1821                 ".set\tpop"                                             \
1822                 : "=r" (__res)                                          \
1823                 : "i" (source), "i" (sel));                             \
1824         __res;                                                          \
1825 })
1826
1827 #define __write_32bit_gc0_register(register, sel, value)                \
1828 do {                                                                    \
1829         __asm__ __volatile__(                                           \
1830                 ".set\tpush\n\t"                                        \
1831                 ".set\tnoat\n\t"                                        \
1832                 "move\t$1, %z0\n\t"                                     \
1833                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1834                 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
1835                 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
1836                 ".set\tpop"                                             \
1837                 : : "Jr" ((unsigned int)(value)),                       \
1838                     "i" (register), "i" (sel));                         \
1839 } while (0)
1840
1841 #define __write_64bit_gc0_register(register, sel, value)                \
1842 do {                                                                    \
1843         __asm__ __volatile__(                                           \
1844                 ".set\tpush\n\t"                                        \
1845                 ".set\tnoat\n\t"                                        \
1846                 "move\t$1, %z0\n\t"                                     \
1847                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1848                 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
1849                 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
1850                 ".set\tpop"                                             \
1851                 : : "Jr" (value),                                       \
1852                     "i" (register), "i" (sel));                         \
1853 } while (0)
1854
1855 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1856
1857 #define __read_ulong_gc0_register(reg, sel)                             \
1858         ((sizeof(unsigned long) == 4) ?                                 \
1859         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1860         (unsigned long) __read_64bit_gc0_register(reg, sel))
1861
1862 #define __write_ulong_gc0_register(reg, sel, val)                       \
1863 do {                                                                    \
1864         if (sizeof(unsigned long) == 4)                                 \
1865                 __write_32bit_gc0_register(reg, sel, val);              \
1866         else                                                            \
1867                 __write_64bit_gc0_register(reg, sel, val);              \
1868 } while (0)
1869
1870 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1871 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1872
1873 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1874 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1875
1876 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1877 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1878
1879 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1880 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1881
1882 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1883 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1884
1885 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1886 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1887
1888 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1889 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1890
1891 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1892 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1893
1894 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1895 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1896
1897 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1898 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1899
1900 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1901 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1902
1903 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1904 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1905
1906 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1907 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
1908
1909 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
1910 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
1911
1912 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
1913 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
1914
1915 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
1916 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
1917
1918 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
1919 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
1920
1921 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
1922 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
1923
1924 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
1925 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
1926
1927 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
1928 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
1929
1930 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
1931 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
1932
1933 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
1934
1935 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
1936 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
1937
1938 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
1939 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
1940
1941 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
1942 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
1943
1944 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
1945 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
1946
1947 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
1948 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
1949
1950 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
1951 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
1952
1953 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
1954 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
1955
1956 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
1957 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
1958
1959 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
1960 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
1961 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
1962 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
1963 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
1964 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
1965 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
1966 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
1967 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
1968 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
1969 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
1970 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
1971 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
1972 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
1973 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
1974 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
1975
1976 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
1977 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
1978 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
1979 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
1980 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
1981 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
1982 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
1983 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
1984 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
1985 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
1986 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
1987 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
1988 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
1989 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
1990 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
1991 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
1992
1993 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
1994 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
1995 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
1996 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
1997 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
1998 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
1999 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
2000 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
2001 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
2002 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
2003 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
2004 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
2005 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
2006 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
2007 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
2008 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
2009
2010 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
2011 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
2012
2013 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
2014 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
2015 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
2016 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
2017 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
2018 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
2019 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
2020 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
2021 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
2022 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
2023 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
2024 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
2025 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
2026 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
2027 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
2028 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
2029 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
2030 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
2031 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
2032 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
2033 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
2034 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
2035 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
2036 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
2037
2038 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
2039 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
2040
2041 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
2042 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
2043 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
2044 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
2045 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
2046 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
2047 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
2048 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
2049 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
2050 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
2051 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
2052 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
2053
2054 /*
2055  * Macros to access the floating point coprocessor control registers
2056  */
2057 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2058 ({                                                                      \
2059         unsigned int __res;                                             \
2060                                                                         \
2061         __asm__ __volatile__(                                           \
2062         "       .set    push                                    \n"     \
2063         "       .set    reorder                                 \n"     \
2064         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2065         "       # like Octeon.                                  \n"     \
2066         "       .set    mips1                                   \n"     \
2067         "       "STR(gas_hardfloat)"                            \n"     \
2068         "       cfc1    %0,"STR(source)"                        \n"     \
2069         "       .set    pop                                     \n"     \
2070         : "=r" (__res));                                                \
2071         __res;                                                          \
2072 })
2073
2074 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2075 do {                                                                    \
2076         __asm__ __volatile__(                                           \
2077         "       .set    push                                    \n"     \
2078         "       .set    reorder                                 \n"     \
2079         "       "STR(gas_hardfloat)"                            \n"     \
2080         "       ctc1    %0,"STR(dest)"                          \n"     \
2081         "       .set    pop                                     \n"     \
2082         : : "r" (val));                                                 \
2083 } while (0)
2084
2085 #ifdef GAS_HAS_SET_HARDFLOAT
2086 #define read_32bit_cp1_register(source)                                 \
2087         _read_32bit_cp1_register(source, .set hardfloat)
2088 #define write_32bit_cp1_register(dest, val)                             \
2089         _write_32bit_cp1_register(dest, val, .set hardfloat)
2090 #else
2091 #define read_32bit_cp1_register(source)                                 \
2092         _read_32bit_cp1_register(source, )
2093 #define write_32bit_cp1_register(dest, val)                             \
2094         _write_32bit_cp1_register(dest, val, )
2095 #endif
2096
2097 #ifdef HAVE_AS_DSP
2098 #define rddsp(mask)                                                     \
2099 ({                                                                      \
2100         unsigned int __dspctl;                                          \
2101                                                                         \
2102         __asm__ __volatile__(                                           \
2103         "       .set push                                       \n"     \
2104         "       .set dsp                                        \n"     \
2105         "       rddsp   %0, %x1                                 \n"     \
2106         "       .set pop                                        \n"     \
2107         : "=r" (__dspctl)                                               \
2108         : "i" (mask));                                                  \
2109         __dspctl;                                                       \
2110 })
2111
2112 #define wrdsp(val, mask)                                                \
2113 do {                                                                    \
2114         __asm__ __volatile__(                                           \
2115         "       .set push                                       \n"     \
2116         "       .set dsp                                        \n"     \
2117         "       wrdsp   %0, %x1                                 \n"     \
2118         "       .set pop                                        \n"     \
2119         :                                                               \
2120         : "r" (val), "i" (mask));                                       \
2121 } while (0)
2122
2123 #define mflo0()                                                         \
2124 ({                                                                      \
2125         long mflo0;                                                     \
2126         __asm__(                                                        \
2127         "       .set push                                       \n"     \
2128         "       .set dsp                                        \n"     \
2129         "       mflo %0, $ac0                                   \n"     \
2130         "       .set pop                                        \n"     \
2131         : "=r" (mflo0));                                                \
2132         mflo0;                                                          \
2133 })
2134
2135 #define mflo1()                                                         \
2136 ({                                                                      \
2137         long mflo1;                                                     \
2138         __asm__(                                                        \
2139         "       .set push                                       \n"     \
2140         "       .set dsp                                        \n"     \
2141         "       mflo %0, $ac1                                   \n"     \
2142         "       .set pop                                        \n"     \
2143         : "=r" (mflo1));                                                \
2144         mflo1;                                                          \
2145 })
2146
2147 #define mflo2()                                                         \
2148 ({                                                                      \
2149         long mflo2;                                                     \
2150         __asm__(                                                        \
2151         "       .set push                                       \n"     \
2152         "       .set dsp                                        \n"     \
2153         "       mflo %0, $ac2                                   \n"     \
2154         "       .set pop                                        \n"     \
2155         : "=r" (mflo2));                                                \
2156         mflo2;                                                          \
2157 })
2158
2159 #define mflo3()                                                         \
2160 ({                                                                      \
2161         long mflo3;                                                     \
2162         __asm__(                                                        \
2163         "       .set push                                       \n"     \
2164         "       .set dsp                                        \n"     \
2165         "       mflo %0, $ac3                                   \n"     \
2166         "       .set pop                                        \n"     \
2167         : "=r" (mflo3));                                                \
2168         mflo3;                                                          \
2169 })
2170
2171 #define mfhi0()                                                         \
2172 ({                                                                      \
2173         long mfhi0;                                                     \
2174         __asm__(                                                        \
2175         "       .set push                                       \n"     \
2176         "       .set dsp                                        \n"     \
2177         "       mfhi %0, $ac0                                   \n"     \
2178         "       .set pop                                        \n"     \
2179         : "=r" (mfhi0));                                                \
2180         mfhi0;                                                          \
2181 })
2182
2183 #define mfhi1()                                                         \
2184 ({                                                                      \
2185         long mfhi1;                                                     \
2186         __asm__(                                                        \
2187         "       .set push                                       \n"     \
2188         "       .set dsp                                        \n"     \
2189         "       mfhi %0, $ac1                                   \n"     \
2190         "       .set pop                                        \n"     \
2191         : "=r" (mfhi1));                                                \
2192         mfhi1;                                                          \
2193 })
2194
2195 #define mfhi2()                                                         \
2196 ({                                                                      \
2197         long mfhi2;                                                     \
2198         __asm__(                                                        \
2199         "       .set push                                       \n"     \
2200         "       .set dsp                                        \n"     \
2201         "       mfhi %0, $ac2                                   \n"     \
2202         "       .set pop                                        \n"     \
2203         : "=r" (mfhi2));                                                \
2204         mfhi2;                                                          \
2205 })
2206
2207 #define mfhi3()                                                         \
2208 ({                                                                      \
2209         long mfhi3;                                                     \
2210         __asm__(                                                        \
2211         "       .set push                                       \n"     \
2212         "       .set dsp                                        \n"     \
2213         "       mfhi %0, $ac3                                   \n"     \
2214         "       .set pop                                        \n"     \
2215         : "=r" (mfhi3));                                                \
2216         mfhi3;                                                          \
2217 })
2218
2219
2220 #define mtlo0(x)                                                        \
2221 ({                                                                      \
2222         __asm__(                                                        \
2223         "       .set push                                       \n"     \
2224         "       .set dsp                                        \n"     \
2225         "       mtlo %0, $ac0                                   \n"     \
2226         "       .set pop                                        \n"     \
2227         :                                                               \
2228         : "r" (x));                                                     \
2229 })
2230
2231 #define mtlo1(x)                                                        \
2232 ({                                                                      \
2233         __asm__(                                                        \
2234         "       .set push                                       \n"     \
2235         "       .set dsp                                        \n"     \
2236         "       mtlo %0, $ac1                                   \n"     \
2237         "       .set pop                                        \n"     \
2238         :                                                               \
2239         : "r" (x));                                                     \
2240 })
2241
2242 #define mtlo2(x)                                                        \
2243 ({                                                                      \
2244         __asm__(                                                        \
2245         "       .set push                                       \n"     \
2246         "       .set dsp                                        \n"     \
2247         "       mtlo %0, $ac2                                   \n"     \
2248         "       .set pop                                        \n"     \
2249         :                                                               \
2250         : "r" (x));                                                     \
2251 })
2252
2253 #define mtlo3(x)                                                        \
2254 ({                                                                      \
2255         __asm__(                                                        \
2256         "       .set push                                       \n"     \
2257         "       .set dsp                                        \n"     \
2258         "       mtlo %0, $ac3                                   \n"     \
2259         "       .set pop                                        \n"     \
2260         :                                                               \
2261         : "r" (x));                                                     \
2262 })
2263
2264 #define mthi0(x)                                                        \
2265 ({                                                                      \
2266         __asm__(                                                        \
2267         "       .set push                                       \n"     \
2268         "       .set dsp                                        \n"     \
2269         "       mthi %0, $ac0                                   \n"     \
2270         "       .set pop                                        \n"     \
2271         :                                                               \
2272         : "r" (x));                                                     \
2273 })
2274
2275 #define mthi1(x)                                                        \
2276 ({                                                                      \
2277         __asm__(                                                        \
2278         "       .set push                                       \n"     \
2279         "       .set dsp                                        \n"     \
2280         "       mthi %0, $ac1                                   \n"     \
2281         "       .set pop                                        \n"     \
2282         :                                                               \
2283         : "r" (x));                                                     \
2284 })
2285
2286 #define mthi2(x)                                                        \
2287 ({                                                                      \
2288         __asm__(                                                        \
2289         "       .set push                                       \n"     \
2290         "       .set dsp                                        \n"     \
2291         "       mthi %0, $ac2                                   \n"     \
2292         "       .set pop                                        \n"     \
2293         :                                                               \
2294         : "r" (x));                                                     \
2295 })
2296
2297 #define mthi3(x)                                                        \
2298 ({                                                                      \
2299         __asm__(                                                        \
2300         "       .set push                                       \n"     \
2301         "       .set dsp                                        \n"     \
2302         "       mthi %0, $ac3                                   \n"     \
2303         "       .set pop                                        \n"     \
2304         :                                                               \
2305         : "r" (x));                                                     \
2306 })
2307
2308 #else
2309
2310 #define rddsp(mask)                                                     \
2311 ({                                                                      \
2312         unsigned int __res;                                             \
2313                                                                         \
2314         __asm__ __volatile__(                                           \
2315         "       .set    push                                    \n"     \
2316         "       .set    noat                                    \n"     \
2317         "       # rddsp $1, %x1                                 \n"     \
2318         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2319         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2320         "       move    %0, $1                                  \n"     \
2321         "       .set    pop                                     \n"     \
2322         : "=r" (__res)                                                  \
2323         : "i" (mask));                                                  \
2324         __res;                                                          \
2325 })
2326
2327 #define wrdsp(val, mask)                                                \
2328 do {                                                                    \
2329         __asm__ __volatile__(                                           \
2330         "       .set    push                                    \n"     \
2331         "       .set    noat                                    \n"     \
2332         "       move    $1, %0                                  \n"     \
2333         "       # wrdsp $1, %x1                                 \n"     \
2334         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2335         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2336         "       .set    pop                                     \n"     \
2337         :                                                               \
2338         : "r" (val), "i" (mask));                                       \
2339 } while (0)
2340
2341 #define _dsp_mfxxx(ins)                                                 \
2342 ({                                                                      \
2343         unsigned long __treg;                                           \
2344                                                                         \
2345         __asm__ __volatile__(                                           \
2346         "       .set    push                                    \n"     \
2347         "       .set    noat                                    \n"     \
2348         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2349         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2350         "       move    %0, $1                                  \n"     \
2351         "       .set    pop                                     \n"     \
2352         : "=r" (__treg)                                                 \
2353         : "i" (ins));                                                   \
2354         __treg;                                                         \
2355 })
2356
2357 #define _dsp_mtxxx(val, ins)                                            \
2358 do {                                                                    \
2359         __asm__ __volatile__(                                           \
2360         "       .set    push                                    \n"     \
2361         "       .set    noat                                    \n"     \
2362         "       move    $1, %0                                  \n"     \
2363         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2364         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2365         "       .set    pop                                     \n"     \
2366         :                                                               \
2367         : "r" (val), "i" (ins));                                        \
2368 } while (0)
2369
2370 #ifdef CONFIG_CPU_MICROMIPS
2371
2372 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2373 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2374
2375 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2376 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2377
2378 #else  /* !CONFIG_CPU_MICROMIPS */
2379
2380 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2381 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2382
2383 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2384 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2385
2386 #endif /* CONFIG_CPU_MICROMIPS */
2387
2388 #define mflo0() _dsp_mflo(0)
2389 #define mflo1() _dsp_mflo(1)
2390 #define mflo2() _dsp_mflo(2)
2391 #define mflo3() _dsp_mflo(3)
2392
2393 #define mfhi0() _dsp_mfhi(0)
2394 #define mfhi1() _dsp_mfhi(1)
2395 #define mfhi2() _dsp_mfhi(2)
2396 #define mfhi3() _dsp_mfhi(3)
2397
2398 #define mtlo0(x) _dsp_mtlo(x, 0)
2399 #define mtlo1(x) _dsp_mtlo(x, 1)
2400 #define mtlo2(x) _dsp_mtlo(x, 2)
2401 #define mtlo3(x) _dsp_mtlo(x, 3)
2402
2403 #define mthi0(x) _dsp_mthi(x, 0)
2404 #define mthi1(x) _dsp_mthi(x, 1)
2405 #define mthi2(x) _dsp_mthi(x, 2)
2406 #define mthi3(x) _dsp_mthi(x, 3)
2407
2408 #endif
2409
2410 /*
2411  * TLB operations.
2412  *
2413  * It is responsibility of the caller to take care of any TLB hazards.
2414  */
2415 static inline void tlb_probe(void)
2416 {
2417         __asm__ __volatile__(
2418                 ".set noreorder\n\t"
2419                 "tlbp\n\t"
2420                 ".set reorder");
2421 }
2422
2423 static inline void tlb_read(void)
2424 {
2425 #if MIPS34K_MISSED_ITLB_WAR
2426         int res = 0;
2427
2428         __asm__ __volatile__(
2429         "       .set    push                                    \n"
2430         "       .set    noreorder                               \n"
2431         "       .set    noat                                    \n"
2432         "       .set    mips32r2                                \n"
2433         "       .word   0x41610001              # dvpe $1       \n"
2434         "       move    %0, $1                                  \n"
2435         "       ehb                                             \n"
2436         "       .set    pop                                     \n"
2437         : "=r" (res));
2438
2439         instruction_hazard();
2440 #endif
2441
2442         __asm__ __volatile__(
2443                 ".set noreorder\n\t"
2444                 "tlbr\n\t"
2445                 ".set reorder");
2446
2447 #if MIPS34K_MISSED_ITLB_WAR
2448         if ((res & _ULCAST_(1)))
2449                 __asm__ __volatile__(
2450                 "       .set    push                            \n"
2451                 "       .set    noreorder                       \n"
2452                 "       .set    noat                            \n"
2453                 "       .set    mips32r2                        \n"
2454                 "       .word   0x41600021      # evpe          \n"
2455                 "       ehb                                     \n"
2456                 "       .set    pop                             \n");
2457 #endif
2458 }
2459
2460 static inline void tlb_write_indexed(void)
2461 {
2462         __asm__ __volatile__(
2463                 ".set noreorder\n\t"
2464                 "tlbwi\n\t"
2465                 ".set reorder");
2466 }
2467
2468 static inline void tlb_write_random(void)
2469 {
2470         __asm__ __volatile__(
2471                 ".set noreorder\n\t"
2472                 "tlbwr\n\t"
2473                 ".set reorder");
2474 }
2475
2476 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2477
2478 /*
2479  * Guest TLB operations.
2480  *
2481  * It is responsibility of the caller to take care of any TLB hazards.
2482  */
2483 static inline void guest_tlb_probe(void)
2484 {
2485         __asm__ __volatile__(
2486                 ".set push\n\t"
2487                 ".set noreorder\n\t"
2488                 ".set virt\n\t"
2489                 "tlbgp\n\t"
2490                 ".set pop");
2491 }
2492
2493 static inline void guest_tlb_read(void)
2494 {
2495         __asm__ __volatile__(
2496                 ".set push\n\t"
2497                 ".set noreorder\n\t"
2498                 ".set virt\n\t"
2499                 "tlbgr\n\t"
2500                 ".set pop");
2501 }
2502
2503 static inline void guest_tlb_write_indexed(void)
2504 {
2505         __asm__ __volatile__(
2506                 ".set push\n\t"
2507                 ".set noreorder\n\t"
2508                 ".set virt\n\t"
2509                 "tlbgwi\n\t"
2510                 ".set pop");
2511 }
2512
2513 static inline void guest_tlb_write_random(void)
2514 {
2515         __asm__ __volatile__(
2516                 ".set push\n\t"
2517                 ".set noreorder\n\t"
2518                 ".set virt\n\t"
2519                 "tlbgwr\n\t"
2520                 ".set pop");
2521 }
2522
2523 /*
2524  * Guest TLB Invalidate Flush
2525  */
2526 static inline void guest_tlbinvf(void)
2527 {
2528         __asm__ __volatile__(
2529                 ".set push\n\t"
2530                 ".set noreorder\n\t"
2531                 ".set virt\n\t"
2532                 "tlbginvf\n\t"
2533                 ".set pop");
2534 }
2535
2536 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2537
2538 /*
2539  * Guest TLB operations.
2540  *
2541  * It is responsibility of the caller to take care of any TLB hazards.
2542  */
2543 static inline void guest_tlb_probe(void)
2544 {
2545         __asm__ __volatile__(
2546                 "# tlbgp\n\t"
2547                 _ASM_INSN_IF_MIPS(0x42000010)
2548                 _ASM_INSN32_IF_MM(0x0000017c));
2549 }
2550
2551 static inline void guest_tlb_read(void)
2552 {
2553         __asm__ __volatile__(
2554                 "# tlbgr\n\t"
2555                 _ASM_INSN_IF_MIPS(0x42000009)
2556                 _ASM_INSN32_IF_MM(0x0000117c));
2557 }
2558
2559 static inline void guest_tlb_write_indexed(void)
2560 {
2561         __asm__ __volatile__(
2562                 "# tlbgwi\n\t"
2563                 _ASM_INSN_IF_MIPS(0x4200000a)
2564                 _ASM_INSN32_IF_MM(0x0000217c));
2565 }
2566
2567 static inline void guest_tlb_write_random(void)
2568 {
2569         __asm__ __volatile__(
2570                 "# tlbgwr\n\t"
2571                 _ASM_INSN_IF_MIPS(0x4200000e)
2572                 _ASM_INSN32_IF_MM(0x0000317c));
2573 }
2574
2575 /*
2576  * Guest TLB Invalidate Flush
2577  */
2578 static inline void guest_tlbinvf(void)
2579 {
2580         __asm__ __volatile__(
2581                 "# tlbginvf\n\t"
2582                 _ASM_INSN_IF_MIPS(0x4200000c)
2583                 _ASM_INSN32_IF_MM(0x0000517c));
2584 }
2585
2586 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2587
2588 /*
2589  * Manipulate bits in a register.
2590  */
2591 #define __BUILD_SET_COMMON(name)                                \
2592 static inline unsigned int                                      \
2593 set_##name(unsigned int set)                                    \
2594 {                                                               \
2595         unsigned int res, new;                                  \
2596                                                                 \
2597         res = read_##name();                                    \
2598         new = res | set;                                        \
2599         write_##name(new);                                      \
2600                                                                 \
2601         return res;                                             \
2602 }                                                               \
2603                                                                 \
2604 static inline unsigned int                                      \
2605 clear_##name(unsigned int clear)                                \
2606 {                                                               \
2607         unsigned int res, new;                                  \
2608                                                                 \
2609         res = read_##name();                                    \
2610         new = res & ~clear;                                     \
2611         write_##name(new);                                      \
2612                                                                 \
2613         return res;                                             \
2614 }                                                               \
2615                                                                 \
2616 static inline unsigned int                                      \
2617 change_##name(unsigned int change, unsigned int val)            \
2618 {                                                               \
2619         unsigned int res, new;                                  \
2620                                                                 \
2621         res = read_##name();                                    \
2622         new = res & ~change;                                    \
2623         new |= (val & change);                                  \
2624         write_##name(new);                                      \
2625                                                                 \
2626         return res;                                             \
2627 }
2628
2629 /*
2630  * Manipulate bits in a c0 register.
2631  */
2632 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2633
2634 __BUILD_SET_C0(status)
2635 __BUILD_SET_C0(cause)
2636 __BUILD_SET_C0(config)
2637 __BUILD_SET_C0(config5)
2638 __BUILD_SET_C0(intcontrol)
2639 __BUILD_SET_C0(intctl)
2640 __BUILD_SET_C0(srsmap)
2641 __BUILD_SET_C0(pagegrain)
2642 __BUILD_SET_C0(guestctl0)
2643 __BUILD_SET_C0(guestctl0ext)
2644 __BUILD_SET_C0(guestctl1)
2645 __BUILD_SET_C0(guestctl2)
2646 __BUILD_SET_C0(guestctl3)
2647 __BUILD_SET_C0(brcm_config_0)
2648 __BUILD_SET_C0(brcm_bus_pll)
2649 __BUILD_SET_C0(brcm_reset)
2650 __BUILD_SET_C0(brcm_cmt_intr)
2651 __BUILD_SET_C0(brcm_cmt_ctrl)
2652 __BUILD_SET_C0(brcm_config)
2653 __BUILD_SET_C0(brcm_mode)
2654
2655 /*
2656  * Manipulate bits in a guest c0 register.
2657  */
2658 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2659
2660 __BUILD_SET_GC0(status)
2661 __BUILD_SET_GC0(cause)
2662 __BUILD_SET_GC0(ebase)
2663
2664 /*
2665  * Return low 10 bits of ebase.
2666  * Note that under KVM (MIPSVZ) this returns vcpu id.
2667  */
2668 static inline unsigned int get_ebase_cpunum(void)
2669 {
2670         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2671 }
2672
2673 #endif /* !__ASSEMBLY__ */
2674
2675 #endif /* _ASM_MIPSREGS_H */