1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
18 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
19 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21 #define CKCTL_6328_ADSL_EN (1 << 3)
22 #define CKCTL_6328_MIPS_EN (1 << 4)
23 #define CKCTL_6328_SAR_EN (1 << 5)
24 #define CKCTL_6328_PCM_EN (1 << 6)
25 #define CKCTL_6328_USBD_EN (1 << 7)
26 #define CKCTL_6328_USBH_EN (1 << 8)
27 #define CKCTL_6328_HSSPI_EN (1 << 9)
28 #define CKCTL_6328_PCIE_EN (1 << 10)
29 #define CKCTL_6328_ROBOSW_EN (1 << 11)
31 #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
42 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
43 #define CKCTL_6338_MPI_EN (1 << 1)
44 #define CKCTL_6338_DRAM_EN (1 << 2)
45 #define CKCTL_6338_ENET_EN (1 << 4)
46 #define CKCTL_6338_USBS_EN (1 << 4)
47 #define CKCTL_6338_SAR_EN (1 << 5)
48 #define CKCTL_6338_SPI_EN (1 << 9)
50 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
52 CKCTL_6338_ENET_EN | \
56 #define CKCTL_6345_CPU_EN (1 << 0)
57 #define CKCTL_6345_BUS_EN (1 << 1)
58 #define CKCTL_6345_EBI_EN (1 << 2)
59 #define CKCTL_6345_UART_EN (1 << 3)
60 #define CKCTL_6345_ADSLPHY_EN (1 << 4)
61 #define CKCTL_6345_ENET_EN (1 << 7)
62 #define CKCTL_6345_USBH_EN (1 << 8)
64 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
65 CKCTL_6345_USBH_EN | \
66 CKCTL_6345_ADSLPHY_EN)
68 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
69 #define CKCTL_6348_MPI_EN (1 << 1)
70 #define CKCTL_6348_SDRAM_EN (1 << 2)
71 #define CKCTL_6348_M2M_EN (1 << 3)
72 #define CKCTL_6348_ENET_EN (1 << 4)
73 #define CKCTL_6348_SAR_EN (1 << 5)
74 #define CKCTL_6348_USBS_EN (1 << 6)
75 #define CKCTL_6348_USBH_EN (1 << 8)
76 #define CKCTL_6348_SPI_EN (1 << 9)
78 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
80 CKCTL_6348_ENET_EN | \
82 CKCTL_6348_USBS_EN | \
83 CKCTL_6348_USBH_EN | \
86 #define CKCTL_6358_ENET_EN (1 << 4)
87 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
88 #define CKCTL_6358_PCM_EN (1 << 8)
89 #define CKCTL_6358_SPI_EN (1 << 9)
90 #define CKCTL_6358_USBS_EN (1 << 10)
91 #define CKCTL_6358_SAR_EN (1 << 11)
92 #define CKCTL_6358_EMUSB_EN (1 << 17)
93 #define CKCTL_6358_ENET0_EN (1 << 18)
94 #define CKCTL_6358_ENET1_EN (1 << 19)
95 #define CKCTL_6358_USBSU_EN (1 << 20)
96 #define CKCTL_6358_EPHY_EN (1 << 21)
98 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
99 CKCTL_6358_ADSLPHY_EN | \
100 CKCTL_6358_PCM_EN | \
101 CKCTL_6358_SPI_EN | \
102 CKCTL_6358_USBS_EN | \
103 CKCTL_6358_SAR_EN | \
104 CKCTL_6358_EMUSB_EN | \
105 CKCTL_6358_ENET0_EN | \
106 CKCTL_6358_ENET1_EN | \
107 CKCTL_6358_USBSU_EN | \
110 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
111 #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
112 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
113 #define CKCTL_6368_VDSL_EN (1 << 5)
114 #define CKCTL_6368_PHYMIPS_EN (1 << 6)
115 #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
116 #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
117 #define CKCTL_6368_SPI_EN (1 << 9)
118 #define CKCTL_6368_USBD_EN (1 << 10)
119 #define CKCTL_6368_SAR_EN (1 << 11)
120 #define CKCTL_6368_ROBOSW_EN (1 << 12)
121 #define CKCTL_6368_UTOPIA_EN (1 << 13)
122 #define CKCTL_6368_PCM_EN (1 << 14)
123 #define CKCTL_6368_USBH_EN (1 << 15)
124 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
125 #define CKCTL_6368_NAND_EN (1 << 17)
126 #define CKCTL_6368_IPSEC_EN (1 << 18)
128 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
129 CKCTL_6368_SWPKT_SAR_EN | \
130 CKCTL_6368_SPI_EN | \
131 CKCTL_6368_USBD_EN | \
132 CKCTL_6368_SAR_EN | \
133 CKCTL_6368_ROBOSW_EN | \
134 CKCTL_6368_UTOPIA_EN | \
135 CKCTL_6368_PCM_EN | \
136 CKCTL_6368_USBH_EN | \
137 CKCTL_6368_DISABLE_GLESS_EN | \
138 CKCTL_6368_NAND_EN | \
141 /* System PLL Control register */
142 #define PERF_SYS_PLL_CTL_REG 0x8
143 #define SYS_PLL_SOFT_RESET 0x1
145 /* Interrupt Mask register */
146 #define PERF_IRQMASK_6328_REG 0x20
147 #define PERF_IRQMASK_6338_REG 0xc
148 #define PERF_IRQMASK_6345_REG 0xc
149 #define PERF_IRQMASK_6348_REG 0xc
150 #define PERF_IRQMASK_6358_REG 0xc
151 #define PERF_IRQMASK_6368_REG 0x20
153 /* Interrupt Status register */
154 #define PERF_IRQSTAT_6328_REG 0x28
155 #define PERF_IRQSTAT_6338_REG 0x10
156 #define PERF_IRQSTAT_6345_REG 0x10
157 #define PERF_IRQSTAT_6348_REG 0x10
158 #define PERF_IRQSTAT_6358_REG 0x10
159 #define PERF_IRQSTAT_6368_REG 0x28
161 /* External Interrupt Configuration register */
162 #define PERF_EXTIRQ_CFG_REG_6328 0x18
163 #define PERF_EXTIRQ_CFG_REG_6338 0x14
164 #define PERF_EXTIRQ_CFG_REG_6345 0x14
165 #define PERF_EXTIRQ_CFG_REG_6348 0x14
166 #define PERF_EXTIRQ_CFG_REG_6358 0x14
167 #define PERF_EXTIRQ_CFG_REG_6368 0x18
169 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
172 #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
173 #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
174 #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
175 #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
176 #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
177 #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
178 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
179 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
182 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
183 #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
184 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
185 #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
186 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
187 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
188 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
189 #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
191 /* Soft Reset register */
192 #define PERF_SOFTRESET_REG 0x28
193 #define PERF_SOFTRESET_6328_REG 0x10
194 #define PERF_SOFTRESET_6358_REG 0x34
195 #define PERF_SOFTRESET_6368_REG 0x10
197 #define SOFTRESET_6328_SPI_MASK (1 << 0)
198 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
199 #define SOFTRESET_6328_SAR_MASK (1 << 2)
200 #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
201 #define SOFTRESET_6328_USBS_MASK (1 << 4)
202 #define SOFTRESET_6328_USBH_MASK (1 << 5)
203 #define SOFTRESET_6328_PCM_MASK (1 << 6)
204 #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
205 #define SOFTRESET_6328_PCIE_MASK (1 << 8)
206 #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
207 #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
209 #define SOFTRESET_6338_SPI_MASK (1 << 0)
210 #define SOFTRESET_6338_ENET_MASK (1 << 2)
211 #define SOFTRESET_6338_USBH_MASK (1 << 3)
212 #define SOFTRESET_6338_USBS_MASK (1 << 4)
213 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
214 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
215 #define SOFTRESET_6338_SAR_MASK (1 << 7)
216 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
217 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
218 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
219 SOFTRESET_6338_ENET_MASK | \
220 SOFTRESET_6338_USBH_MASK | \
221 SOFTRESET_6338_USBS_MASK | \
222 SOFTRESET_6338_ADSL_MASK | \
223 SOFTRESET_6338_DMAMEM_MASK | \
224 SOFTRESET_6338_SAR_MASK | \
225 SOFTRESET_6338_ACLC_MASK | \
226 SOFTRESET_6338_ADSLMIPSPLL_MASK)
228 #define SOFTRESET_6348_SPI_MASK (1 << 0)
229 #define SOFTRESET_6348_ENET_MASK (1 << 2)
230 #define SOFTRESET_6348_USBH_MASK (1 << 3)
231 #define SOFTRESET_6348_USBS_MASK (1 << 4)
232 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
233 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
234 #define SOFTRESET_6348_SAR_MASK (1 << 7)
235 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
236 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
238 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
239 SOFTRESET_6348_ENET_MASK | \
240 SOFTRESET_6348_USBH_MASK | \
241 SOFTRESET_6348_USBS_MASK | \
242 SOFTRESET_6348_ADSL_MASK | \
243 SOFTRESET_6348_DMAMEM_MASK | \
244 SOFTRESET_6348_SAR_MASK | \
245 SOFTRESET_6348_ACLC_MASK | \
246 SOFTRESET_6348_ADSLMIPSPLL_MASK)
248 #define SOFTRESET_6358_SPI_MASK (1 << 0)
249 #define SOFTRESET_6358_ENET_MASK (1 << 2)
250 #define SOFTRESET_6358_MPI_MASK (1 << 3)
251 #define SOFTRESET_6358_EPHY_MASK (1 << 6)
252 #define SOFTRESET_6358_SAR_MASK (1 << 7)
253 #define SOFTRESET_6358_USBH_MASK (1 << 12)
254 #define SOFTRESET_6358_PCM_MASK (1 << 13)
255 #define SOFTRESET_6358_ADSL_MASK (1 << 14)
257 #define SOFTRESET_6368_SPI_MASK (1 << 0)
258 #define SOFTRESET_6368_MPI_MASK (1 << 3)
259 #define SOFTRESET_6368_EPHY_MASK (1 << 6)
260 #define SOFTRESET_6368_SAR_MASK (1 << 7)
261 #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
262 #define SOFTRESET_6368_USBS_MASK (1 << 11)
263 #define SOFTRESET_6368_USBH_MASK (1 << 12)
264 #define SOFTRESET_6368_PCM_MASK (1 << 13)
266 /* MIPS PLL control register */
267 #define PERF_MIPSPLLCTL_REG 0x34
268 #define MIPSPLLCTL_N1_SHIFT 20
269 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
270 #define MIPSPLLCTL_N2_SHIFT 15
271 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
272 #define MIPSPLLCTL_M1REF_SHIFT 12
273 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
274 #define MIPSPLLCTL_M2REF_SHIFT 9
275 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
276 #define MIPSPLLCTL_M1CPU_SHIFT 6
277 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
278 #define MIPSPLLCTL_M1BUS_SHIFT 3
279 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
280 #define MIPSPLLCTL_M2BUS_SHIFT 0
281 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
283 /* ADSL PHY PLL Control register */
284 #define PERF_ADSLPLLCTL_REG 0x38
285 #define ADSLPLLCTL_N1_SHIFT 20
286 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
287 #define ADSLPLLCTL_N2_SHIFT 15
288 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
289 #define ADSLPLLCTL_M1REF_SHIFT 12
290 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
291 #define ADSLPLLCTL_M2REF_SHIFT 9
292 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
293 #define ADSLPLLCTL_M1CPU_SHIFT 6
294 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
295 #define ADSLPLLCTL_M1BUS_SHIFT 3
296 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
297 #define ADSLPLLCTL_M2BUS_SHIFT 0
298 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
300 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
301 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
302 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
303 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
304 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
305 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
306 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
307 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
310 /*************************************************************************
311 * _REG relative to RSET_TIMER
312 *************************************************************************/
314 #define BCM63XX_TIMER_COUNT 4
315 #define TIMER_T0_ID 0
316 #define TIMER_T1_ID 1
317 #define TIMER_T2_ID 2
318 #define TIMER_WDT_ID 3
320 /* Timer irqstat register */
321 #define TIMER_IRQSTAT_REG 0
322 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
323 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
324 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
325 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
326 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
327 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
328 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
329 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
330 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
332 /* Timer control register */
333 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
334 #define TIMER_CTL0_REG 0x4
335 #define TIMER_CTL1_REG 0x8
336 #define TIMER_CTL2_REG 0xC
337 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
338 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
339 #define TIMER_CTL_ENABLE_MASK (1 << 31)
342 /*************************************************************************
343 * _REG relative to RSET_WDT
344 *************************************************************************/
346 /* Watchdog default count register */
347 #define WDT_DEFVAL_REG 0x0
349 /* Watchdog control register */
350 #define WDT_CTL_REG 0x4
352 /* Watchdog control register constants */
353 #define WDT_START_1 (0xff00)
354 #define WDT_START_2 (0x00ff)
355 #define WDT_STOP_1 (0xee00)
356 #define WDT_STOP_2 (0x00ee)
358 /* Watchdog reset length register */
359 #define WDT_RSTLEN_REG 0x8
361 /* Watchdog soft reset register (BCM6328 only) */
362 #define WDT_SOFTRESET_REG 0xc
364 /*************************************************************************
365 * _REG relative to RSET_UARTx
366 *************************************************************************/
368 /* UART Control Register */
369 #define UART_CTL_REG 0x0
370 #define UART_CTL_RXTMOUTCNT_SHIFT 0
371 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
372 #define UART_CTL_RSTTXDN_SHIFT 5
373 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
374 #define UART_CTL_RSTRXFIFO_SHIFT 6
375 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
376 #define UART_CTL_RSTTXFIFO_SHIFT 7
377 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
378 #define UART_CTL_STOPBITS_SHIFT 8
379 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
380 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
381 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
382 #define UART_CTL_BITSPERSYM_SHIFT 12
383 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
384 #define UART_CTL_XMITBRK_SHIFT 14
385 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
386 #define UART_CTL_RSVD_SHIFT 15
387 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
388 #define UART_CTL_RXPAREVEN_SHIFT 16
389 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
390 #define UART_CTL_RXPAREN_SHIFT 17
391 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
392 #define UART_CTL_TXPAREVEN_SHIFT 18
393 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
394 #define UART_CTL_TXPAREN_SHIFT 18
395 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
396 #define UART_CTL_LOOPBACK_SHIFT 20
397 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
398 #define UART_CTL_RXEN_SHIFT 21
399 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
400 #define UART_CTL_TXEN_SHIFT 22
401 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
402 #define UART_CTL_BRGEN_SHIFT 23
403 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
405 /* UART Baudword register */
406 #define UART_BAUD_REG 0x4
408 /* UART Misc Control register */
409 #define UART_MCTL_REG 0x8
410 #define UART_MCTL_DTR_SHIFT 0
411 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
412 #define UART_MCTL_RTS_SHIFT 1
413 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
414 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
415 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
416 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
417 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
418 #define UART_MCTL_RXFIFOFILL_SHIFT 16
419 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
420 #define UART_MCTL_TXFIFOFILL_SHIFT 24
421 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
423 /* UART External Input Configuration register */
424 #define UART_EXTINP_REG 0xc
425 #define UART_EXTINP_RI_SHIFT 0
426 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
427 #define UART_EXTINP_CTS_SHIFT 1
428 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
429 #define UART_EXTINP_DCD_SHIFT 2
430 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
431 #define UART_EXTINP_DSR_SHIFT 3
432 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
433 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
434 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
435 #define UART_EXTINP_IR_RI 0
436 #define UART_EXTINP_IR_CTS 1
437 #define UART_EXTINP_IR_DCD 2
438 #define UART_EXTINP_IR_DSR 3
439 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
440 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
441 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
442 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
443 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
444 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
445 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
446 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
448 /* UART Interrupt register */
449 #define UART_IR_REG 0x10
450 #define UART_IR_MASK(x) (1 << (x + 16))
451 #define UART_IR_STAT(x) (1 << (x))
452 #define UART_IR_EXTIP 0
453 #define UART_IR_TXUNDER 1
454 #define UART_IR_TXOVER 2
455 #define UART_IR_TXTRESH 3
456 #define UART_IR_TXRDLATCH 4
457 #define UART_IR_TXEMPTY 5
458 #define UART_IR_RXUNDER 6
459 #define UART_IR_RXOVER 7
460 #define UART_IR_RXTIMEOUT 8
461 #define UART_IR_RXFULL 9
462 #define UART_IR_RXTHRESH 10
463 #define UART_IR_RXNOTEMPTY 11
464 #define UART_IR_RXFRAMEERR 12
465 #define UART_IR_RXPARERR 13
466 #define UART_IR_RXBRK 14
467 #define UART_IR_TXDONE 15
469 /* UART Fifo register */
470 #define UART_FIFO_REG 0x14
471 #define UART_FIFO_VALID_SHIFT 0
472 #define UART_FIFO_VALID_MASK 0xff
473 #define UART_FIFO_FRAMEERR_SHIFT 8
474 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
475 #define UART_FIFO_PARERR_SHIFT 9
476 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
477 #define UART_FIFO_BRKDET_SHIFT 10
478 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
479 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
480 UART_FIFO_PARERR_MASK | \
481 UART_FIFO_BRKDET_MASK)
484 /*************************************************************************
485 * _REG relative to RSET_GPIO
486 *************************************************************************/
489 #define GPIO_CTL_HI_REG 0x0
490 #define GPIO_CTL_LO_REG 0x4
491 #define GPIO_DATA_HI_REG 0x8
492 #define GPIO_DATA_LO_REG 0xC
493 #define GPIO_DATA_LO_REG_6345 0x8
495 /* GPIO mux registers and constants */
496 #define GPIO_MODE_REG 0x18
498 #define GPIO_MODE_6348_G4_DIAG 0x00090000
499 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
500 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
501 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
502 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
503 #define GPIO_MODE_6348_G3_DIAG 0x00009000
504 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
505 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
506 #define GPIO_MODE_6348_G2_DIAG 0x00000900
507 #define GPIO_MODE_6348_G2_PCI 0x00000500
508 #define GPIO_MODE_6348_G1_DIAG 0x00000090
509 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
510 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
511 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
512 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
513 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
514 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
515 #define GPIO_MODE_6348_G0_DIAG 0x00000009
516 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
518 #define GPIO_MODE_6358_EXTRACS (1 << 5)
519 #define GPIO_MODE_6358_UART1 (1 << 6)
520 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
521 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
522 #define GPIO_MODE_6358_UTOPIA (1 << 12)
524 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
525 #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
526 #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
527 #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
528 #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
529 #define GPIO_MODE_6368_INET_LED (1 << 5)
530 #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
531 #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
532 #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
533 #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
534 #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
535 #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
536 #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
537 #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
538 #define GPIO_MODE_6368_USBD_LED (1 << 14)
539 #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
540 #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
541 #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
542 #define GPIO_MODE_6368_PCI_INTB (1 << 18)
543 #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
544 #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
545 #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
546 #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
547 #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
548 #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
549 #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
550 #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
551 #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
552 #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
553 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
554 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
557 #define GPIO_PINMUX_OTHR_REG 0x24
558 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
559 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
560 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
561 #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
563 #define GPIO_BASEMODE_6368_REG 0x38
564 #define GPIO_BASEMODE_6368_UART2 0x1
565 #define GPIO_BASEMODE_6368_GPIO 0x0
566 #define GPIO_BASEMODE_6368_MASK 0x7
567 /* those bits must be kept as read in gpio basemode register*/
569 #define GPIO_STRAPBUS_REG 0x40
570 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
571 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
572 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
573 #define STRAPBUS_6368_BOOT_SEL_NAND 0
574 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
575 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
578 /*************************************************************************
579 * _REG relative to RSET_ENET
580 *************************************************************************/
582 /* Receiver Configuration register */
583 #define ENET_RXCFG_REG 0x0
584 #define ENET_RXCFG_ALLMCAST_SHIFT 1
585 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
586 #define ENET_RXCFG_PROMISC_SHIFT 3
587 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
588 #define ENET_RXCFG_LOOPBACK_SHIFT 4
589 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
590 #define ENET_RXCFG_ENFLOW_SHIFT 5
591 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
593 /* Receive Maximum Length register */
594 #define ENET_RXMAXLEN_REG 0x4
595 #define ENET_RXMAXLEN_SHIFT 0
596 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
598 /* Transmit Maximum Length register */
599 #define ENET_TXMAXLEN_REG 0x8
600 #define ENET_TXMAXLEN_SHIFT 0
601 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
603 /* MII Status/Control register */
604 #define ENET_MIISC_REG 0x10
605 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
606 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
607 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
608 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
610 /* MII Data register */
611 #define ENET_MIIDATA_REG 0x14
612 #define ENET_MIIDATA_DATA_SHIFT 0
613 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
614 #define ENET_MIIDATA_TA_SHIFT 16
615 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
616 #define ENET_MIIDATA_REG_SHIFT 18
617 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
618 #define ENET_MIIDATA_PHYID_SHIFT 23
619 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
620 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
621 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
623 /* Ethernet Interrupt Mask register */
624 #define ENET_IRMASK_REG 0x18
626 /* Ethernet Interrupt register */
627 #define ENET_IR_REG 0x1c
628 #define ENET_IR_MII (1 << 0)
629 #define ENET_IR_MIB (1 << 1)
630 #define ENET_IR_FLOWC (1 << 2)
632 /* Ethernet Control register */
633 #define ENET_CTL_REG 0x2c
634 #define ENET_CTL_ENABLE_SHIFT 0
635 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
636 #define ENET_CTL_DISABLE_SHIFT 1
637 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
638 #define ENET_CTL_SRESET_SHIFT 2
639 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
640 #define ENET_CTL_EPHYSEL_SHIFT 3
641 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
643 /* Transmit Control register */
644 #define ENET_TXCTL_REG 0x30
645 #define ENET_TXCTL_FD_SHIFT 0
646 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
648 /* Transmit Watermask register */
649 #define ENET_TXWMARK_REG 0x34
650 #define ENET_TXWMARK_WM_SHIFT 0
651 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
653 /* MIB Control register */
654 #define ENET_MIBCTL_REG 0x38
655 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
656 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
658 /* Perfect Match Data Low register */
659 #define ENET_PML_REG(x) (0x58 + (x) * 8)
660 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
661 #define ENET_PMH_DATAVALID_SHIFT 16
662 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
665 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
666 #define ENET_MIB_REG_COUNT 55
669 /*************************************************************************
670 * _REG relative to RSET_ENETDMA
671 *************************************************************************/
673 /* Controller Configuration Register */
674 #define ENETDMA_CFG_REG (0x0)
675 #define ENETDMA_CFG_EN_SHIFT 0
676 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
677 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
679 /* Flow Control Descriptor Low Threshold register */
680 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
682 /* Flow Control Descriptor High Threshold register */
683 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
685 /* Flow Control Descriptor Buffer Alloca Threshold register */
686 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
687 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
688 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
690 /* Global interrupt status */
691 #define ENETDMA_GLB_IRQSTAT_REG (0x40)
693 /* Global interrupt mask */
694 #define ENETDMA_GLB_IRQMASK_REG (0x44)
696 /* Channel Configuration register */
697 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
698 #define ENETDMA_CHANCFG_EN_SHIFT 0
699 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
700 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
701 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
703 /* Interrupt Control/Status register */
704 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
705 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
706 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
707 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
709 /* Interrupt Mask register */
710 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
712 /* Maximum Burst Length */
713 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
715 /* Ring Start Address register */
716 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
718 /* State Ram Word 2 */
719 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
721 /* State Ram Word 3 */
722 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
724 /* State Ram Word 4 */
725 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
728 /*************************************************************************
729 * _REG relative to RSET_ENETDMAC
730 *************************************************************************/
732 /* Channel Configuration register */
733 #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
734 #define ENETDMAC_CHANCFG_EN_SHIFT 0
735 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
736 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
737 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
738 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
739 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
741 /* Interrupt Control/Status register */
742 #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
743 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
744 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
745 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
747 /* Interrupt Mask register */
748 #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
750 /* Maximum Burst Length */
751 #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
754 /*************************************************************************
755 * _REG relative to RSET_ENETDMAS
756 *************************************************************************/
758 /* Ring Start Address register */
759 #define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
761 /* State Ram Word 2 */
762 #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
764 /* State Ram Word 3 */
765 #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
767 /* State Ram Word 4 */
768 #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
771 /*************************************************************************
772 * _REG relative to RSET_ENETSW
773 *************************************************************************/
776 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
777 #define ENETSW_MIB_REG_COUNT 47
780 /*************************************************************************
781 * _REG relative to RSET_OHCI_PRIV
782 *************************************************************************/
784 #define OHCI_PRIV_REG 0x0
785 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
786 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
787 #define OHCI_PRIV_REG_SWAP_SHIFT 3
788 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
791 /*************************************************************************
792 * _REG relative to RSET_USBH_PRIV
793 *************************************************************************/
795 #define USBH_PRIV_SWAP_6358_REG 0x0
796 #define USBH_PRIV_SWAP_6368_REG 0x1c
798 #define USBH_PRIV_SWAP_USBD_SHIFT 6
799 #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
800 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
801 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
802 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
803 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
804 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
805 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
806 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
807 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
809 #define USBH_PRIV_UTMI_CTL_6368_REG 0x10
810 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
811 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
812 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
813 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
815 #define USBH_PRIV_TEST_6358_REG 0x24
816 #define USBH_PRIV_TEST_6368_REG 0x14
818 #define USBH_PRIV_SETUP_6368_REG 0x28
819 #define USBH_PRIV_SETUP_IOC_SHIFT 4
820 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
823 /*************************************************************************
824 * _REG relative to RSET_USBD
825 *************************************************************************/
827 /* General control */
828 #define USBD_CONTROL_REG 0x00
829 #define USBD_CONTROL_TXZLENINS_SHIFT 14
830 #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
831 #define USBD_CONTROL_AUTO_CSRS_SHIFT 13
832 #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
833 #define USBD_CONTROL_RXZSCFG_SHIFT 12
834 #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
835 #define USBD_CONTROL_INIT_SEL_SHIFT 8
836 #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
837 #define USBD_CONTROL_FIFO_RESET_SHIFT 6
838 #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
839 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
840 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
841 #define USBD_CONTROL_DONE_CSRS_SHIFT 0
842 #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
845 #define USBD_STRAPS_REG 0x04
846 #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
847 #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
848 #define USBD_STRAPS_APP_DISCON_SHIFT 9
849 #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
850 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
851 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
852 #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
853 #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
854 #define USBD_STRAPS_APP_RAM_IF_SHIFT 7
855 #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
856 #define USBD_STRAPS_APP_8BITPHY_SHIFT 2
857 #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
858 #define USBD_STRAPS_SPEED_SHIFT 0
859 #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
862 #define USBD_STALL_REG 0x08
863 #define USBD_STALL_UPDATE_SHIFT 7
864 #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
865 #define USBD_STALL_ENABLE_SHIFT 6
866 #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
867 #define USBD_STALL_EPNUM_SHIFT 0
868 #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
871 #define USBD_STATUS_REG 0x0c
872 #define USBD_STATUS_SOF_SHIFT 16
873 #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
874 #define USBD_STATUS_SPD_SHIFT 12
875 #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
876 #define USBD_STATUS_ALTINTF_SHIFT 8
877 #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
878 #define USBD_STATUS_INTF_SHIFT 4
879 #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
880 #define USBD_STATUS_CFG_SHIFT 0
881 #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
884 #define USBD_EVENTS_REG 0x10
885 #define USBD_EVENTS_USB_LINK_SHIFT 10
886 #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
889 #define USBD_EVENT_IRQ_STATUS_REG 0x14
891 /* IRQ level (2 bits per IRQ event) */
892 #define USBD_EVENT_IRQ_CFG_HI_REG 0x18
894 #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
896 #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
897 #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
898 #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
899 #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
901 /* IRQ mask (1=unmasked) */
902 #define USBD_EVENT_IRQ_MASK_REG 0x20
905 #define USBD_EVENT_IRQ_USB_LINK 10
906 #define USBD_EVENT_IRQ_SETCFG 9
907 #define USBD_EVENT_IRQ_SETINTF 8
908 #define USBD_EVENT_IRQ_ERRATIC_ERR 7
909 #define USBD_EVENT_IRQ_SET_CSRS 6
910 #define USBD_EVENT_IRQ_SUSPEND 5
911 #define USBD_EVENT_IRQ_EARLY_SUSPEND 4
912 #define USBD_EVENT_IRQ_SOF 3
913 #define USBD_EVENT_IRQ_ENUM_ON 2
914 #define USBD_EVENT_IRQ_SETUP 1
915 #define USBD_EVENT_IRQ_USB_RESET 0
917 /* TX FIFO partitioning */
918 #define USBD_TXFIFO_CONFIG_REG 0x40
919 #define USBD_TXFIFO_CONFIG_END_SHIFT 16
920 #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
921 #define USBD_TXFIFO_CONFIG_START_SHIFT 0
922 #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
924 /* RX FIFO partitioning */
925 #define USBD_RXFIFO_CONFIG_REG 0x44
926 #define USBD_RXFIFO_CONFIG_END_SHIFT 16
927 #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
928 #define USBD_RXFIFO_CONFIG_START_SHIFT 0
929 #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
931 /* TX FIFO/endpoint configuration */
932 #define USBD_TXFIFO_EPSIZE_REG 0x48
934 /* RX FIFO/endpoint configuration */
935 #define USBD_RXFIFO_EPSIZE_REG 0x4c
937 /* Endpoint<->DMA mappings */
938 #define USBD_EPNUM_TYPEMAP_REG 0x50
939 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
940 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
941 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
942 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
944 /* Misc per-endpoint settings */
945 #define USBD_CSR_SETUPADDR_REG 0x80
946 #define USBD_CSR_SETUPADDR_DEF 0xb550
948 #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
949 #define USBD_CSR_EP_MAXPKT_SHIFT 19
950 #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
951 #define USBD_CSR_EP_ALTIFACE_SHIFT 15
952 #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
953 #define USBD_CSR_EP_IFACE_SHIFT 11
954 #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
955 #define USBD_CSR_EP_CFG_SHIFT 7
956 #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
957 #define USBD_CSR_EP_TYPE_SHIFT 5
958 #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
959 #define USBD_CSR_EP_DIR_SHIFT 4
960 #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
961 #define USBD_CSR_EP_LOG_SHIFT 0
962 #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
965 /*************************************************************************
966 * _REG relative to RSET_MPI
967 *************************************************************************/
969 /* well known (hard wired) chip select */
970 #define MPI_CS_PCMCIA_COMMON 4
971 #define MPI_CS_PCMCIA_ATTR 5
972 #define MPI_CS_PCMCIA_IO 6
974 /* Chip select base register */
975 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
976 #define MPI_CSBASE_BASE_SHIFT 13
977 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
978 #define MPI_CSBASE_SIZE_SHIFT 0
979 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
981 #define MPI_CSBASE_SIZE_8K 0
982 #define MPI_CSBASE_SIZE_16K 1
983 #define MPI_CSBASE_SIZE_32K 2
984 #define MPI_CSBASE_SIZE_64K 3
985 #define MPI_CSBASE_SIZE_128K 4
986 #define MPI_CSBASE_SIZE_256K 5
987 #define MPI_CSBASE_SIZE_512K 6
988 #define MPI_CSBASE_SIZE_1M 7
989 #define MPI_CSBASE_SIZE_2M 8
990 #define MPI_CSBASE_SIZE_4M 9
991 #define MPI_CSBASE_SIZE_8M 10
992 #define MPI_CSBASE_SIZE_16M 11
993 #define MPI_CSBASE_SIZE_32M 12
994 #define MPI_CSBASE_SIZE_64M 13
995 #define MPI_CSBASE_SIZE_128M 14
996 #define MPI_CSBASE_SIZE_256M 15
998 /* Chip select control register */
999 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
1000 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
1001 #define MPI_CSCTL_WAIT_SHIFT 1
1002 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
1003 #define MPI_CSCTL_DATA16_MASK (1 << 4)
1004 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
1005 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
1006 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
1007 #define MPI_CSCTL_SETUP_SHIFT 16
1008 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
1009 #define MPI_CSCTL_HOLD_SHIFT 20
1010 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
1013 #define MPI_SP0_RANGE_REG 0x100
1014 #define MPI_SP0_REMAP_REG 0x104
1015 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
1016 #define MPI_SP1_RANGE_REG 0x10C
1017 #define MPI_SP1_REMAP_REG 0x110
1018 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
1020 #define MPI_L2PCFG_REG 0x11C
1021 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
1022 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1023 #define MPI_L2PCFG_REG_SHIFT 2
1024 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
1025 #define MPI_L2PCFG_FUNC_SHIFT 8
1026 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
1027 #define MPI_L2PCFG_DEVNUM_SHIFT 11
1028 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1029 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
1030 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
1032 #define MPI_L2PMEMRANGE1_REG 0x120
1033 #define MPI_L2PMEMBASE1_REG 0x124
1034 #define MPI_L2PMEMREMAP1_REG 0x128
1035 #define MPI_L2PMEMRANGE2_REG 0x12C
1036 #define MPI_L2PMEMBASE2_REG 0x130
1037 #define MPI_L2PMEMREMAP2_REG 0x134
1038 #define MPI_L2PIORANGE_REG 0x138
1039 #define MPI_L2PIOBASE_REG 0x13C
1040 #define MPI_L2PIOREMAP_REG 0x140
1041 #define MPI_L2P_BASE_MASK (0xffff8000)
1042 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
1043 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
1045 #define MPI_PCIMODESEL_REG 0x144
1046 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1047 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
1048 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
1049 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
1050 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1052 #define MPI_LOCBUSCTL_REG 0x14C
1053 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
1054 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
1056 #define MPI_LOCINT_REG 0x150
1057 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
1058 #define MPI_LOCINT_STAT(x) (1 << (x))
1059 #define MPI_LOCINT_DIR_FAILED 6
1060 #define MPI_LOCINT_EXT_PCI_INT 7
1061 #define MPI_LOCINT_SERR 8
1062 #define MPI_LOCINT_CSERR 9
1064 #define MPI_PCICFGCTL_REG 0x178
1065 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
1066 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1067 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
1069 #define MPI_PCICFGDATA_REG 0x17C
1071 /* PCI host bridge custom register */
1072 #define BCMPCI_REG_TIMERS 0x40
1073 #define REG_TIMER_TRDY_SHIFT 0
1074 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
1075 #define REG_TIMER_RETRY_SHIFT 8
1076 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
1079 /*************************************************************************
1080 * _REG relative to RSET_PCMCIA
1081 *************************************************************************/
1083 #define PCMCIA_C1_REG 0x0
1084 #define PCMCIA_C1_CD1_MASK (1 << 0)
1085 #define PCMCIA_C1_CD2_MASK (1 << 1)
1086 #define PCMCIA_C1_VS1_MASK (1 << 2)
1087 #define PCMCIA_C1_VS2_MASK (1 << 3)
1088 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
1089 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
1090 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
1091 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1092 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
1093 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
1094 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
1095 #define PCMCIA_C1_RESET_MASK (1 << 18)
1097 #define PCMCIA_C2_REG 0x8
1098 #define PCMCIA_C2_DATA16_MASK (1 << 0)
1099 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
1100 #define PCMCIA_C2_RWCOUNT_SHIFT 2
1101 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1102 #define PCMCIA_C2_INACTIVE_SHIFT 8
1103 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1104 #define PCMCIA_C2_SETUP_SHIFT 16
1105 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
1106 #define PCMCIA_C2_HOLD_SHIFT 24
1107 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
1110 /*************************************************************************
1111 * _REG relative to RSET_SDRAM
1112 *************************************************************************/
1114 #define SDRAM_CFG_REG 0x0
1115 #define SDRAM_CFG_ROW_SHIFT 4
1116 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
1117 #define SDRAM_CFG_COL_SHIFT 6
1118 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
1119 #define SDRAM_CFG_32B_SHIFT 10
1120 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
1121 #define SDRAM_CFG_BANK_SHIFT 13
1122 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
1124 #define SDRAM_MBASE_REG 0xc
1126 #define SDRAM_PRIO_REG 0x2C
1127 #define SDRAM_PRIO_MIPS_SHIFT 29
1128 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
1129 #define SDRAM_PRIO_ADSL_SHIFT 30
1130 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
1131 #define SDRAM_PRIO_EN_SHIFT 31
1132 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
1135 /*************************************************************************
1136 * _REG relative to RSET_MEMC
1137 *************************************************************************/
1139 #define MEMC_CFG_REG 0x4
1140 #define MEMC_CFG_32B_SHIFT 1
1141 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
1142 #define MEMC_CFG_COL_SHIFT 3
1143 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
1144 #define MEMC_CFG_ROW_SHIFT 6
1145 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
1148 /*************************************************************************
1149 * _REG relative to RSET_DDR
1150 *************************************************************************/
1152 #define DDR_CSEND_REG 0x8
1154 #define DDR_DMIPSPLLCFG_REG 0x18
1155 #define DMIPSPLLCFG_M1_SHIFT 0
1156 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
1157 #define DMIPSPLLCFG_N1_SHIFT 23
1158 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
1159 #define DMIPSPLLCFG_N2_SHIFT 29
1160 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
1162 #define DDR_DMIPSPLLCFG_6368_REG 0x20
1163 #define DMIPSPLLCFG_6368_P1_SHIFT 0
1164 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1165 #define DMIPSPLLCFG_6368_P2_SHIFT 4
1166 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1167 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
1168 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1170 #define DDR_DMIPSPLLDIV_6368_REG 0x24
1171 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
1172 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1175 /*************************************************************************
1176 * _REG relative to RSET_M2M
1177 *************************************************************************/
1182 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1183 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1184 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1186 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1187 #define M2M_CTRL_ENABLE_MASK (1 << 0)
1188 #define M2M_CTRL_IRQEN_MASK (1 << 1)
1189 #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
1190 #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
1191 #define M2M_CTRL_NOINC_MASK (1 << 8)
1192 #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
1193 #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
1194 #define M2M_CTRL_ENDIAN_MASK (1 << 11)
1196 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1197 #define M2M_STAT_DONE (1 << 0)
1198 #define M2M_STAT_ERROR (1 << 1)
1200 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1201 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1203 /*************************************************************************
1204 * _REG relative to RSET_RNG
1205 *************************************************************************/
1207 #define RNG_CTRL 0x00
1208 #define RNG_EN (1 << 0)
1210 #define RNG_STAT 0x04
1211 #define RNG_AVAIL_MASK (0xff000000)
1213 #define RNG_DATA 0x08
1214 #define RNG_THRES 0x0c
1215 #define RNG_MASK 0x10
1217 /*************************************************************************
1218 * _REG relative to RSET_SPI
1219 *************************************************************************/
1221 /* BCM 6338 SPI core */
1222 #define SPI_6338_CMD 0x00 /* 16-bits register */
1223 #define SPI_6338_INT_STATUS 0x02
1224 #define SPI_6338_INT_MASK_ST 0x03
1225 #define SPI_6338_INT_MASK 0x04
1226 #define SPI_6338_ST 0x05
1227 #define SPI_6338_CLK_CFG 0x06
1228 #define SPI_6338_FILL_BYTE 0x07
1229 #define SPI_6338_MSG_TAIL 0x09
1230 #define SPI_6338_RX_TAIL 0x0b
1231 #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1232 #define SPI_6338_MSG_CTL_WIDTH 8
1233 #define SPI_6338_MSG_DATA 0x41
1234 #define SPI_6338_MSG_DATA_SIZE 0x3f
1235 #define SPI_6338_RX_DATA 0x80
1236 #define SPI_6338_RX_DATA_SIZE 0x3f
1238 /* BCM 6348 SPI core */
1239 #define SPI_6348_CMD 0x00 /* 16-bits register */
1240 #define SPI_6348_INT_STATUS 0x02
1241 #define SPI_6348_INT_MASK_ST 0x03
1242 #define SPI_6348_INT_MASK 0x04
1243 #define SPI_6348_ST 0x05
1244 #define SPI_6348_CLK_CFG 0x06
1245 #define SPI_6348_FILL_BYTE 0x07
1246 #define SPI_6348_MSG_TAIL 0x09
1247 #define SPI_6348_RX_TAIL 0x0b
1248 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1249 #define SPI_6348_MSG_CTL_WIDTH 8
1250 #define SPI_6348_MSG_DATA 0x41
1251 #define SPI_6348_MSG_DATA_SIZE 0x3f
1252 #define SPI_6348_RX_DATA 0x80
1253 #define SPI_6348_RX_DATA_SIZE 0x3f
1255 /* BCM 6358 SPI core */
1256 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1257 #define SPI_6358_MSG_CTL_WIDTH 16
1258 #define SPI_6358_MSG_DATA 0x02
1259 #define SPI_6358_MSG_DATA_SIZE 0x21e
1260 #define SPI_6358_RX_DATA 0x400
1261 #define SPI_6358_RX_DATA_SIZE 0x220
1262 #define SPI_6358_CMD 0x700 /* 16-bits register */
1263 #define SPI_6358_INT_STATUS 0x702
1264 #define SPI_6358_INT_MASK_ST 0x703
1265 #define SPI_6358_INT_MASK 0x704
1266 #define SPI_6358_ST 0x705
1267 #define SPI_6358_CLK_CFG 0x706
1268 #define SPI_6358_FILL_BYTE 0x707
1269 #define SPI_6358_MSG_TAIL 0x709
1270 #define SPI_6358_RX_TAIL 0x70B
1272 /* BCM 6358 SPI core */
1273 #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1274 #define SPI_6368_MSG_CTL_WIDTH 16
1275 #define SPI_6368_MSG_DATA 0x02
1276 #define SPI_6368_MSG_DATA_SIZE 0x21e
1277 #define SPI_6368_RX_DATA 0x400
1278 #define SPI_6368_RX_DATA_SIZE 0x220
1279 #define SPI_6368_CMD 0x700 /* 16-bits register */
1280 #define SPI_6368_INT_STATUS 0x702
1281 #define SPI_6368_INT_MASK_ST 0x703
1282 #define SPI_6368_INT_MASK 0x704
1283 #define SPI_6368_ST 0x705
1284 #define SPI_6368_CLK_CFG 0x706
1285 #define SPI_6368_FILL_BYTE 0x707
1286 #define SPI_6368_MSG_TAIL 0x709
1287 #define SPI_6368_RX_TAIL 0x70B
1289 /* Shared SPI definitions */
1291 /* Message configuration */
1292 #define SPI_FD_RW 0x00
1293 #define SPI_HD_W 0x01
1294 #define SPI_HD_R 0x02
1295 #define SPI_BYTE_CNT_SHIFT 0
1296 #define SPI_6338_MSG_TYPE_SHIFT 6
1297 #define SPI_6348_MSG_TYPE_SHIFT 6
1298 #define SPI_6358_MSG_TYPE_SHIFT 14
1299 #define SPI_6368_MSG_TYPE_SHIFT 14
1302 #define SPI_CMD_NOOP 0x00
1303 #define SPI_CMD_SOFT_RESET 0x01
1304 #define SPI_CMD_HARD_RESET 0x02
1305 #define SPI_CMD_START_IMMEDIATE 0x03
1306 #define SPI_CMD_COMMAND_SHIFT 0
1307 #define SPI_CMD_COMMAND_MASK 0x000f
1308 #define SPI_CMD_DEVICE_ID_SHIFT 4
1309 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1310 #define SPI_CMD_ONE_BYTE_SHIFT 11
1311 #define SPI_CMD_ONE_WIRE_SHIFT 12
1312 #define SPI_DEV_ID_0 0
1313 #define SPI_DEV_ID_1 1
1314 #define SPI_DEV_ID_2 2
1315 #define SPI_DEV_ID_3 3
1317 /* Interrupt mask */
1318 #define SPI_INTR_CMD_DONE 0x01
1319 #define SPI_INTR_RX_OVERFLOW 0x02
1320 #define SPI_INTR_TX_UNDERFLOW 0x04
1321 #define SPI_INTR_TX_OVERFLOW 0x08
1322 #define SPI_INTR_RX_UNDERFLOW 0x10
1323 #define SPI_INTR_CLEAR_ALL 0x1f
1326 #define SPI_RX_EMPTY 0x02
1327 #define SPI_CMD_BUSY 0x04
1328 #define SPI_SERIAL_BUSY 0x08
1330 /* Clock configuration */
1331 #define SPI_CLK_20MHZ 0x00
1332 #define SPI_CLK_0_391MHZ 0x01
1333 #define SPI_CLK_0_781MHZ 0x02 /* default */
1334 #define SPI_CLK_1_563MHZ 0x03
1335 #define SPI_CLK_3_125MHZ 0x04
1336 #define SPI_CLK_6_250MHZ 0x05
1337 #define SPI_CLK_12_50MHZ 0x06
1338 #define SPI_CLK_MASK 0x07
1339 #define SPI_SSOFFTIME_MASK 0x38
1340 #define SPI_SSOFFTIME_SHIFT 3
1341 #define SPI_BYTE_SWAP 0x80
1343 /*************************************************************************
1344 * _REG relative to RSET_MISC
1345 *************************************************************************/
1346 #define MISC_SERDES_CTRL_REG 0x0
1347 #define SERDES_PCIE_EN (1 << 0)
1348 #define SERDES_PCIE_EXD_EN (1 << 15)
1350 #define MISC_STRAPBUS_6328_REG 0x240
1351 #define STRAPBUS_6328_FCVO_SHIFT 7
1352 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1353 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1354 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1356 /*************************************************************************
1357 * _REG relative to RSET_PCIE
1358 *************************************************************************/
1360 #define PCIE_CONFIG2_REG 0x408
1361 #define CONFIG2_BAR1_SIZE_EN 1
1362 #define CONFIG2_BAR1_SIZE_MASK 0xf
1364 #define PCIE_IDVAL3_REG 0x43c
1365 #define IDVAL3_CLASS_CODE_MASK 0xffffff
1366 #define IDVAL3_SUBCLASS_SHIFT 8
1367 #define IDVAL3_CLASS_SHIFT 16
1369 #define PCIE_DLSTATUS_REG 0x1048
1370 #define DLSTATUS_PHYLINKUP (1 << 13)
1372 #define PCIE_BRIDGE_OPT1_REG 0x2820
1373 #define OPT1_RD_BE_OPT_EN (1 << 7)
1374 #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1375 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1376 #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1378 #define PCIE_BRIDGE_OPT2_REG 0x2824
1379 #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1380 #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1381 #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1382 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1383 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1385 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1386 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1387 #define BASEMASK_REMAP_EN (1 << 0)
1388 #define BASEMASK_SWAP_EN (1 << 1)
1389 #define BASEMASK_MASK_SHIFT 4
1390 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1391 #define BASEMASK_BASE_SHIFT 20
1392 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1394 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1395 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1396 #define REBASE_ADDR_BASE_SHIFT 20
1397 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1399 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1400 #define PCIE_RC_INT_A (1 << 0)
1401 #define PCIE_RC_INT_B (1 << 1)
1402 #define PCIE_RC_INT_C (1 << 2)
1403 #define PCIE_RC_INT_D (1 << 3)
1405 #define PCIE_DEVICE_OFFSET 0x8000
1407 #endif /* BCM63XX_REGS_H_ */
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