arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/cpumask.h>
  14 #include <linux/mutex.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/types.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_types.h>
  20 #include <linux/threads.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <asm/inst.h>
  24 #include <asm/mipsregs.h>
  25
  26 #include <kvm/iodev.h>
  27
  28 /* MIPS KVM register ids */
  29 #define MIPS_CP0_32(_R, _S)                                     \
  30         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  31
  32 #define MIPS_CP0_64(_R, _S)                                     \
  33         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  34
  35 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  36 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  37 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  38 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  39 #define KVM_REG_MIPS_CP0_CONTEXTCONFIG  MIPS_CP0_32(4, 1)
  40 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  41 #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
  42 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  43 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  44 #define KVM_REG_MIPS_CP0_SEGCTL0        MIPS_CP0_64(5, 2)
  45 #define KVM_REG_MIPS_CP0_SEGCTL1        MIPS_CP0_64(5, 3)
  46 #define KVM_REG_MIPS_CP0_SEGCTL2        MIPS_CP0_64(5, 4)
  47 #define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)
  48 #define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)
  49 #define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)
  50 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  51 #define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)
  52 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  53 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  54 #define KVM_REG_MIPS_CP0_BADINSTR       MIPS_CP0_32(8, 1)
  55 #define KVM_REG_MIPS_CP0_BADINSTRP      MIPS_CP0_32(8, 2)
  56 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  57 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  58 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  59 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  60 #define KVM_REG_MIPS_CP0_INTCTL         MIPS_CP0_32(12, 1)
  61 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  62 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  63 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  64 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  65 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  66 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  67 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  68 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  69 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  70 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  71 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  72 #define KVM_REG_MIPS_CP0_MAARI          MIPS_CP0_64(17, 2)
  73 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  74 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  75 #define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
  76 #define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
  77 #define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
  78 #define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
  79 #define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
  80 #define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
  81
  82
  83 #define KVM_MAX_VCPUS           16
  84 #define KVM_USER_MEM_SLOTS      16
  85 /* memory slots that does not exposed to userspace */
  86 #define KVM_PRIVATE_MEM_SLOTS   0
  87
  88 #define KVM_HALT_POLL_NS_DEFAULT 500000
  89
  90 #ifdef CONFIG_KVM_MIPS_VZ
  91 extern unsigned long GUESTID_MASK;
  92 extern unsigned long GUESTID_FIRST_VERSION;
  93 extern unsigned long GUESTID_VERSION_MASK;
  94 #endif
  95
  96
  97 /*
  98  * Special address that contains the comm page, used for reducing # of traps
  99  * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
 100  * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
 101  * caught.
 102  */
 103 #define KVM_GUEST_COMMPAGE_ADDR         ((PAGE_SIZE > 0x8000) ? 0 : \
 104                                          (0x8000 - PAGE_SIZE))
 105
 106 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
 107                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
 108
 109 #define KVM_GUEST_KUSEG                 0x00000000UL
 110 #define KVM_GUEST_KSEG0                 0x40000000UL
 111 #define KVM_GUEST_KSEG1                 0x40000000UL
 112 #define KVM_GUEST_KSEG23                0x60000000UL
 113 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0xe0000000)
 114 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
 115
 116 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 117 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 118 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 119
 120 /*
 121  * Map an address to a certain kernel segment
 122  */
 123 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 124 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 125 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
 126
 127 #define KVM_INVALID_PAGE                0xdeadbeef
 128 #define KVM_INVALID_ADDR                0xdeadbeef
 129
 130 /*
 131  * EVA has overlapping user & kernel address spaces, so user VAs may be >
 132  * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
 133  * PAGE_OFFSET.
 134  */
 135
 136 #define KVM_HVA_ERR_BAD                 (-1UL)
 137 #define KVM_HVA_ERR_RO_BAD              (-2UL)
 138
 139 static inline bool kvm_is_error_hva(unsigned long addr)
 140 {
 141         return IS_ERR_VALUE(addr);
 142 }
 143
 144 struct kvm_vm_stat {
 145         ulong remote_tlb_flush;
 146 };
 147
 148 struct kvm_vcpu_stat {
 149         u64 wait_exits;
 150         u64 cache_exits;
 151         u64 signal_exits;
 152         u64 int_exits;
 153         u64 cop_unusable_exits;
 154         u64 tlbmod_exits;
 155         u64 tlbmiss_ld_exits;
 156         u64 tlbmiss_st_exits;
 157         u64 addrerr_st_exits;
 158         u64 addrerr_ld_exits;
 159         u64 syscall_exits;
 160         u64 resvd_inst_exits;
 161         u64 break_inst_exits;
 162         u64 trap_inst_exits;
 163         u64 msa_fpe_exits;
 164         u64 fpe_exits;
 165         u64 msa_disabled_exits;
 166         u64 flush_dcache_exits;
 167 #ifdef CONFIG_KVM_MIPS_VZ
 168         u64 vz_gpsi_exits;
 169         u64 vz_gsfc_exits;
 170         u64 vz_hc_exits;
 171         u64 vz_grr_exits;
 172         u64 vz_gva_exits;
 173         u64 vz_ghfc_exits;
 174         u64 vz_gpa_exits;
 175         u64 vz_resvd_exits;
 176 #ifdef CONFIG_CPU_LOONGSON64
 177         u64 vz_cpucfg_exits;
 178 #endif
 179 #endif
 180         u64 halt_successful_poll;
 181         u64 halt_attempted_poll;
 182         u64 halt_poll_success_ns;
 183         u64 halt_poll_fail_ns;
 184         u64 halt_poll_invalid;
 185         u64 halt_wakeup;
 186 };
 187
 188 struct kvm_arch_memory_slot {
 189 };
 190
 191 #ifdef CONFIG_CPU_LOONGSON64
 192 struct ipi_state {
 193         uint32_t status;
 194         uint32_t en;
 195         uint32_t set;
 196         uint32_t clear;
 197         uint64_t buf[4];
 198 };
 199
 200 struct loongson_kvm_ipi;
 201
 202 struct ipi_io_device {
 203         int node_id;
 204         struct loongson_kvm_ipi *ipi;
 205         struct kvm_io_device device;
 206 };
 207
 208 struct loongson_kvm_ipi {
 209         spinlock_t lock;
 210         struct kvm *kvm;
 211         struct ipi_state ipistate[16];
 212         struct ipi_io_device dev_ipi[4];
 213 };
 214 #endif
 215
 216 struct kvm_arch {
 217         /* Guest physical mm */
 218         struct mm_struct gpa_mm;
 219         /* Mask of CPUs needing GPA ASID flush */
 220         cpumask_t asid_flush_mask;
 221 #ifdef CONFIG_CPU_LOONGSON64
 222         struct loongson_kvm_ipi ipi;
 223 #endif
 224 };
 225
 226 #define N_MIPS_COPROC_REGS      32
 227 #define N_MIPS_COPROC_SEL       8
 228
 229 struct mips_coproc {
 230         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 231 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 232         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 233 #endif
 234 };
 235
 236 /*
 237  * Coprocessor 0 register names
 238  */
 239 #define MIPS_CP0_TLB_INDEX      0
 240 #define MIPS_CP0_TLB_RANDOM     1
 241 #define MIPS_CP0_TLB_LOW        2
 242 #define MIPS_CP0_TLB_LO0        2
 243 #define MIPS_CP0_TLB_LO1        3
 244 #define MIPS_CP0_TLB_CONTEXT    4
 245 #define MIPS_CP0_TLB_PG_MASK    5
 246 #define MIPS_CP0_TLB_WIRED      6
 247 #define MIPS_CP0_HWRENA         7
 248 #define MIPS_CP0_BAD_VADDR      8
 249 #define MIPS_CP0_COUNT          9
 250 #define MIPS_CP0_TLB_HI         10
 251 #define MIPS_CP0_COMPARE        11
 252 #define MIPS_CP0_STATUS         12
 253 #define MIPS_CP0_CAUSE          13
 254 #define MIPS_CP0_EXC_PC         14
 255 #define MIPS_CP0_PRID           15
 256 #define MIPS_CP0_CONFIG         16
 257 #define MIPS_CP0_LLADDR         17
 258 #define MIPS_CP0_WATCH_LO       18
 259 #define MIPS_CP0_WATCH_HI       19
 260 #define MIPS_CP0_TLB_XCONTEXT   20
 261 #define MIPS_CP0_ECC            26
 262 #define MIPS_CP0_CACHE_ERR      27
 263 #define MIPS_CP0_TAG_LO         28
 264 #define MIPS_CP0_TAG_HI         29
 265 #define MIPS_CP0_ERROR_PC       30
 266 #define MIPS_CP0_DEBUG          23
 267 #define MIPS_CP0_DEPC           24
 268 #define MIPS_CP0_PERFCNT        25
 269 #define MIPS_CP0_ERRCTL         26
 270 #define MIPS_CP0_DATA_LO        28
 271 #define MIPS_CP0_DATA_HI        29
 272 #define MIPS_CP0_DESAVE         31
 273
 274 #define MIPS_CP0_CONFIG_SEL     0
 275 #define MIPS_CP0_CONFIG1_SEL    1
 276 #define MIPS_CP0_CONFIG2_SEL    2
 277 #define MIPS_CP0_CONFIG3_SEL    3
 278 #define MIPS_CP0_CONFIG4_SEL    4
 279 #define MIPS_CP0_CONFIG5_SEL    5
 280
 281 #define MIPS_CP0_GUESTCTL2      10
 282 #define MIPS_CP0_GUESTCTL2_SEL  5
 283 #define MIPS_CP0_GTOFFSET       12
 284 #define MIPS_CP0_GTOFFSET_SEL   7
 285
 286 /* Resume Flags */
 287 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 288 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 289
 290 #define RESUME_GUEST            0
 291 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 292 #define RESUME_HOST             RESUME_FLAG_HOST
 293
 294 enum emulation_result {
 295         EMULATE_DONE,           /* no further processing */
 296         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 297         EMULATE_FAIL,           /* can't emulate this instruction */
 298         EMULATE_WAIT,           /* WAIT instruction */
 299         EMULATE_PRIV_FAIL,
 300         EMULATE_EXCEPT,         /* A guest exception has been generated */
 301         EMULATE_HYPERCALL,      /* HYPCALL instruction */
 302 };
 303
 304 #define mips3_paddr_to_tlbpfn(x) \
 305         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 306 #define mips3_tlbpfn_to_paddr(x) \
 307         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 308
 309 #define MIPS3_PG_SHIFT          6
 310 #define MIPS3_PG_FRAME          0x3fffffc0
 311
 312 #if defined(CONFIG_64BIT)
 313 #define VPN2_MASK               GENMASK(cpu_vmbits - 1, 13)
 314 #else
 315 #define VPN2_MASK               0xffffe000
 316 #endif
 317 #define KVM_ENTRYHI_ASID        cpu_asid_mask(&boot_cpu_data)
 318 #define TLB_IS_GLOBAL(x)        ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 319 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 320 #define TLB_ASID(x)             ((x).tlb_hi & KVM_ENTRYHI_ASID)
 321 #define TLB_LO_IDX(x, va)       (((va) >> PAGE_SHIFT) & 1)
 322 #define TLB_IS_VALID(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
 323 #define TLB_IS_DIRTY(x, va)     ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
 324 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 325                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 326 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 327                                  TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
 328
 329 struct kvm_mips_tlb {
 330         long tlb_mask;
 331         long tlb_hi;
 332         long tlb_lo[2];
 333 };
 334
 335 #define KVM_NR_MEM_OBJS     4
 336
 337 /*
 338  * We don't want allocation failures within the mmu code, so we preallocate
 339  * enough memory for a single page fault in a cache.
 340  */
 341 struct kvm_mmu_memory_cache {
 342         int nobjs;
 343         void *objects[KVM_NR_MEM_OBJS];
 344 };
 345
 346 #define KVM_MIPS_AUX_FPU        0x1
 347 #define KVM_MIPS_AUX_MSA        0x2
 348
 349 #define KVM_MIPS_GUEST_TLB_SIZE 64
 350 struct kvm_vcpu_arch {
 351         void *guest_ebase;
 352         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 353
 354         /* Host registers preserved across guest mode execution */
 355         unsigned long host_stack;
 356         unsigned long host_gp;
 357         unsigned long host_pgd;
 358         unsigned long host_entryhi;
 359
 360         /* Host CP0 registers used when handling exits from guest */
 361         unsigned long host_cp0_badvaddr;
 362         unsigned long host_cp0_epc;
 363         u32 host_cp0_cause;
 364         u32 host_cp0_guestctl0;
 365         u32 host_cp0_badinstr;
 366         u32 host_cp0_badinstrp;
 367
 368         /* GPRS */
 369         unsigned long gprs[32];
 370         unsigned long hi;
 371         unsigned long lo;
 372         unsigned long pc;
 373
 374         /* FPU State */
 375         struct mips_fpu_struct fpu;
 376         /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
 377         unsigned int aux_inuse;
 378
 379         /* COP0 State */
 380         struct mips_coproc *cop0;
 381
 382         /* Host KSEG0 address of the EI/DI offset */
 383         void *kseg0_commpage;
 384
 385         /* Resume PC after MMIO completion */
 386         unsigned long io_pc;
 387         /* GPR used as IO source/target */
 388         u32 io_gpr;
 389
 390         struct hrtimer comparecount_timer;
 391         /* Count timer control KVM register */
 392         u32 count_ctl;
 393         /* Count bias from the raw time */
 394         u32 count_bias;
 395         /* Frequency of timer in Hz */
 396         u32 count_hz;
 397         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 398         s64 count_dyn_bias;
 399         /* Resume time */
 400         ktime_t count_resume;
 401         /* Period of timer tick in ns */
 402         u64 count_period;
 403
 404         /* Bitmask of exceptions that are pending */
 405         unsigned long pending_exceptions;
 406
 407         /* Bitmask of pending exceptions to be cleared */
 408         unsigned long pending_exceptions_clr;
 409
 410         /* S/W Based TLB for guest */
 411         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 412
 413         /* Guest kernel/user [partial] mm */
 414         struct mm_struct guest_kernel_mm, guest_user_mm;
 415
 416         /* Guest ASID of last user mode execution */
 417         unsigned int last_user_gasid;
 418
 419         /* Cache some mmu pages needed inside spinlock regions */
 420         struct kvm_mmu_memory_cache mmu_page_cache;
 421
 422 #ifdef CONFIG_KVM_MIPS_VZ
 423         /* vcpu's vzguestid is different on each host cpu in an smp system */
 424         u32 vzguestid[NR_CPUS];
 425
 426         /* wired guest TLB entries */
 427         struct kvm_mips_tlb *wired_tlb;
 428         unsigned int wired_tlb_limit;
 429         unsigned int wired_tlb_used;
 430
 431         /* emulated guest MAAR registers */
 432         unsigned long maar[6];
 433 #endif
 434
 435         /* Last CPU the VCPU state was loaded on */
 436         int last_sched_cpu;
 437         /* Last CPU the VCPU actually executed guest code on */
 438         int last_exec_cpu;
 439
 440         /* WAIT executed */
 441         int wait;
 442
 443         u8 fpu_enabled;
 444         u8 msa_enabled;
 445 };
 446
 447 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 448                                                 unsigned long val)
 449 {
 450         unsigned long temp;
 451         do {
 452                 __asm__ __volatile__(
 453                 "       .set    push                            \n"
 454                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 455                 "       " __LL "%0, %1                          \n"
 456                 "       or      %0, %2                          \n"
 457                 "       " __SC  "%0, %1                         \n"
 458                 "       .set    pop                             \n"
 459                 : "=&r" (temp), "+m" (*reg)
 460                 : "r" (val));
 461         } while (unlikely(!temp));
 462 }
 463
 464 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 465                                                   unsigned long val)
 466 {
 467         unsigned long temp;
 468         do {
 469                 __asm__ __volatile__(
 470                 "       .set    push                            \n"
 471                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 472                 "       " __LL "%0, %1                          \n"
 473                 "       and     %0, %2                          \n"
 474                 "       " __SC  "%0, %1                         \n"
 475                 "       .set    pop                             \n"
 476                 : "=&r" (temp), "+m" (*reg)
 477                 : "r" (~val));
 478         } while (unlikely(!temp));
 479 }
 480
 481 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 482                                                    unsigned long change,
 483                                                    unsigned long val)
 484 {
 485         unsigned long temp;
 486         do {
 487                 __asm__ __volatile__(
 488                 "       .set    push                            \n"
 489                 "       .set    "MIPS_ISA_ARCH_LEVEL"           \n"
 490                 "       " __LL "%0, %1                          \n"
 491                 "       and     %0, %2                          \n"
 492                 "       or      %0, %3                          \n"
 493                 "       " __SC  "%0, %1                         \n"
 494                 "       .set    pop                             \n"
 495                 : "=&r" (temp), "+m" (*reg)
 496                 : "r" (~change), "r" (val & change));
 497         } while (unlikely(!temp));
 498 }
 499
 500 /* Guest register types, used in accessor build below */
 501 #define __KVMT32        u32
 502 #define __KVMTl unsigned long
 503
 504 /*
 505  * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
 506  * These operate on the saved guest C0 state in RAM.
 507  */
 508
 509 /* Generate saved context simple accessors */
 510 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 511 static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
 512 {                                                                       \
 513         return cop0->reg[(_reg)][(sel)];                                \
 514 }                                                                       \
 515 static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0,    \
 516                                            __KVMT##type val)            \
 517 {                                                                       \
 518         cop0->reg[(_reg)][(sel)] = val;                                 \
 519 }
 520
 521 /* Generate saved context bitwise modifiers */
 522 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 523 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 524                                          __KVMT##type val)              \
 525 {                                                                       \
 526         cop0->reg[(_reg)][(sel)] |= val;                                \
 527 }                                                                       \
 528 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 529                                            __KVMT##type val)            \
 530 {                                                                       \
 531         cop0->reg[(_reg)][(sel)] &= ~val;                               \
 532 }                                                                       \
 533 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 534                                             __KVMT##type mask,          \
 535                                             __KVMT##type val)           \
 536 {                                                                       \
 537         unsigned long _mask = mask;                                     \
 538         cop0->reg[(_reg)][(sel)] &= ~_mask;                             \
 539         cop0->reg[(_reg)][(sel)] |= val & _mask;                        \
 540 }
 541
 542 /* Generate saved context atomic bitwise modifiers */
 543 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 544 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0,      \
 545                                          __KVMT##type val)              \
 546 {                                                                       \
 547         _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val);   \
 548 }                                                                       \
 549 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0,    \
 550                                            __KVMT##type val)            \
 551 {                                                                       \
 552         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
 553 }                                                                       \
 554 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0,   \
 555                                             __KVMT##type mask,          \
 556                                             __KVMT##type val)           \
 557 {                                                                       \
 558         _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
 559                                         val);                           \
 560 }
 561
 562 /*
 563  * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
 564  * These operate on the VZ guest C0 context in hardware.
 565  */
 566
 567 /* Generate VZ guest context simple accessors */
 568 #define __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 569 static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
 570 {                                                                       \
 571         return read_gc0_##name();                                       \
 572 }                                                                       \
 573 static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0,    \
 574                                            __KVMT##type val)            \
 575 {                                                                       \
 576         write_gc0_##name(val);                                          \
 577 }
 578
 579 /* Generate VZ guest context bitwise modifiers */
 580 #define __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 581 static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0,      \
 582                                          __KVMT##type val)              \
 583 {                                                                       \
 584         set_gc0_##name(val);                                            \
 585 }                                                                       \
 586 static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0,    \
 587                                            __KVMT##type val)            \
 588 {                                                                       \
 589         clear_gc0_##name(val);                                          \
 590 }                                                                       \
 591 static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0,   \
 592                                             __KVMT##type mask,          \
 593                                             __KVMT##type val)           \
 594 {                                                                       \
 595         change_gc0_##name(mask, val);                                   \
 596 }
 597
 598 /* Generate VZ guest context save/restore to/from saved context */
 599 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel)                    \
 600 static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0)     \
 601 {                                                                       \
 602         write_gc0_##name(cop0->reg[(_reg)][(sel)]);                     \
 603 }                                                                       \
 604 static inline void kvm_save_gc0_##name(struct mips_coproc *cop0)        \
 605 {                                                                       \
 606         cop0->reg[(_reg)][(sel)] = read_gc0_##name();                   \
 607 }
 608
 609 /*
 610  * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
 611  * These wrap a set of operations to provide them with a different name.
 612  */
 613
 614 /* Generate simple accessor wrapper */
 615 #define __BUILD_KVM_RW_WRAP(name1, name2, type)                         \
 616 static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0)   \
 617 {                                                                       \
 618         return kvm_read_##name2(cop0);                                  \
 619 }                                                                       \
 620 static inline void kvm_write_##name1(struct mips_coproc *cop0,          \
 621                                      __KVMT##type val)                  \
 622 {                                                                       \
 623         kvm_write_##name2(cop0, val);                                   \
 624 }
 625
 626 /* Generate bitwise modifier wrapper */
 627 #define __BUILD_KVM_SET_WRAP(name1, name2, type)                        \
 628 static inline void kvm_set_##name1(struct mips_coproc *cop0,            \
 629                                    __KVMT##type val)                    \
 630 {                                                                       \
 631         kvm_set_##name2(cop0, val);                                     \
 632 }                                                                       \
 633 static inline void kvm_clear_##name1(struct mips_coproc *cop0,          \
 634                                      __KVMT##type val)                  \
 635 {                                                                       \
 636         kvm_clear_##name2(cop0, val);                                   \
 637 }                                                                       \
 638 static inline void kvm_change_##name1(struct mips_coproc *cop0,         \
 639                                       __KVMT##type mask,                \
 640                                       __KVMT##type val)                 \
 641 {                                                                       \
 642         kvm_change_##name2(cop0, mask, val);                            \
 643 }
 644
 645 /*
 646  * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
 647  * These generate accessors operating on the saved context in RAM, and wrap them
 648  * with the common guest C0 accessors (for use by common emulation code).
 649  */
 650
 651 #define __BUILD_KVM_RW_SW(name, type, _reg, sel)                        \
 652         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 653         __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
 654
 655 #define __BUILD_KVM_SET_SW(name, type, _reg, sel)                       \
 656         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 657         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 658
 659 #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel)                    \
 660         __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel)                 \
 661         __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
 662
 663 #ifndef CONFIG_KVM_MIPS_VZ
 664
 665 /*
 666  * T&E (trap & emulate software based virtualisation)
 667  * We generate the common accessors operating exclusively on the saved context
 668  * in RAM.
 669  */
 670
 671 #define __BUILD_KVM_RW_HW       __BUILD_KVM_RW_SW
 672 #define __BUILD_KVM_SET_HW      __BUILD_KVM_SET_SW
 673 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_ATOMIC_SW
 674
 675 #else
 676
 677 /*
 678  * VZ (hardware assisted virtualisation)
 679  * These macros use the active guest state in VZ mode (hardware registers),
 680  */
 681
 682 /*
 683  * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
 684  * These generate accessors operating on the VZ guest context in hardware, and
 685  * wrap them with the common guest C0 accessors (for use by common emulation
 686  * code).
 687  *
 688  * Accessors operating on the saved context in RAM are also generated to allow
 689  * convenient explicit saving and restoring of the state.
 690  */
 691
 692 #define __BUILD_KVM_RW_HW(name, type, _reg, sel)                        \
 693         __BUILD_KVM_RW_SAVED(name, type, _reg, sel)                     \
 694         __BUILD_KVM_RW_VZ(name, type, _reg, sel)                        \
 695         __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type)       \
 696         __BUILD_KVM_SAVE_VZ(name, _reg, sel)
 697
 698 #define __BUILD_KVM_SET_HW(name, type, _reg, sel)                       \
 699         __BUILD_KVM_SET_SAVED(name, type, _reg, sel)                    \
 700         __BUILD_KVM_SET_VZ(name, type, _reg, sel)                       \
 701         __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
 702
 703 /*
 704  * We can't do atomic modifications of COP0 state if hardware can modify it.
 705  * Races must be handled explicitly.
 706  */
 707 #define __BUILD_KVM_ATOMIC_HW   __BUILD_KVM_SET_HW
 708
 709 #endif
 710
 711 /*
 712  * Define accessors for CP0 registers that are accessible to the guest. These
 713  * are primarily used by common emulation code, which may need to access the
 714  * registers differently depending on the implementation.
 715  *
 716  *    fns_hw/sw    name     type    reg num         select
 717  */
 718 __BUILD_KVM_RW_HW(index,          32, MIPS_CP0_TLB_INDEX,    0)
 719 __BUILD_KVM_RW_HW(entrylo0,       l,  MIPS_CP0_TLB_LO0,      0)
 720 __BUILD_KVM_RW_HW(entrylo1,       l,  MIPS_CP0_TLB_LO1,      0)
 721 __BUILD_KVM_RW_HW(context,        l,  MIPS_CP0_TLB_CONTEXT,  0)
 722 __BUILD_KVM_RW_HW(contextconfig,  32, MIPS_CP0_TLB_CONTEXT,  1)
 723 __BUILD_KVM_RW_HW(userlocal,      l,  MIPS_CP0_TLB_CONTEXT,  2)
 724 __BUILD_KVM_RW_HW(xcontextconfig, l,  MIPS_CP0_TLB_CONTEXT,  3)
 725 __BUILD_KVM_RW_HW(pagemask,       l,  MIPS_CP0_TLB_PG_MASK,  0)
 726 __BUILD_KVM_RW_HW(pagegrain,      32, MIPS_CP0_TLB_PG_MASK,  1)
 727 __BUILD_KVM_RW_HW(segctl0,        l,  MIPS_CP0_TLB_PG_MASK,  2)
 728 __BUILD_KVM_RW_HW(segctl1,        l,  MIPS_CP0_TLB_PG_MASK,  3)
 729 __BUILD_KVM_RW_HW(segctl2,        l,  MIPS_CP0_TLB_PG_MASK,  4)
 730 __BUILD_KVM_RW_HW(pwbase,         l,  MIPS_CP0_TLB_PG_MASK,  5)
 731 __BUILD_KVM_RW_HW(pwfield,        l,  MIPS_CP0_TLB_PG_MASK,  6)
 732 __BUILD_KVM_RW_HW(pwsize,         l,  MIPS_CP0_TLB_PG_MASK,  7)
 733 __BUILD_KVM_RW_HW(wired,          32, MIPS_CP0_TLB_WIRED,    0)
 734 __BUILD_KVM_RW_HW(pwctl,          32, MIPS_CP0_TLB_WIRED,    6)
 735 __BUILD_KVM_RW_HW(hwrena,         32, MIPS_CP0_HWRENA,       0)
 736 __BUILD_KVM_RW_HW(badvaddr,       l,  MIPS_CP0_BAD_VADDR,    0)
 737 __BUILD_KVM_RW_HW(badinstr,       32, MIPS_CP0_BAD_VADDR,    1)
 738 __BUILD_KVM_RW_HW(badinstrp,      32, MIPS_CP0_BAD_VADDR,    2)
 739 __BUILD_KVM_RW_SW(count,          32, MIPS_CP0_COUNT,        0)
 740 __BUILD_KVM_RW_HW(entryhi,        l,  MIPS_CP0_TLB_HI,       0)
 741 __BUILD_KVM_RW_HW(compare,        32, MIPS_CP0_COMPARE,      0)
 742 __BUILD_KVM_RW_HW(status,         32, MIPS_CP0_STATUS,       0)
 743 __BUILD_KVM_RW_HW(intctl,         32, MIPS_CP0_STATUS,       1)
 744 __BUILD_KVM_RW_HW(cause,          32, MIPS_CP0_CAUSE,        0)
 745 __BUILD_KVM_RW_HW(epc,            l,  MIPS_CP0_EXC_PC,       0)
 746 __BUILD_KVM_RW_SW(prid,           32, MIPS_CP0_PRID,         0)
 747 __BUILD_KVM_RW_HW(ebase,          l,  MIPS_CP0_PRID,         1)
 748 __BUILD_KVM_RW_HW(config,         32, MIPS_CP0_CONFIG,       0)
 749 __BUILD_KVM_RW_HW(config1,        32, MIPS_CP0_CONFIG,       1)
 750 __BUILD_KVM_RW_HW(config2,        32, MIPS_CP0_CONFIG,       2)
 751 __BUILD_KVM_RW_HW(config3,        32, MIPS_CP0_CONFIG,       3)
 752 __BUILD_KVM_RW_HW(config4,        32, MIPS_CP0_CONFIG,       4)
 753 __BUILD_KVM_RW_HW(config5,        32, MIPS_CP0_CONFIG,       5)
 754 __BUILD_KVM_RW_HW(config6,        32, MIPS_CP0_CONFIG,       6)
 755 __BUILD_KVM_RW_HW(config7,        32, MIPS_CP0_CONFIG,       7)
 756 __BUILD_KVM_RW_SW(maari,          l,  MIPS_CP0_LLADDR,       2)
 757 __BUILD_KVM_RW_HW(xcontext,       l,  MIPS_CP0_TLB_XCONTEXT, 0)
 758 __BUILD_KVM_RW_HW(errorepc,       l,  MIPS_CP0_ERROR_PC,     0)
 759 __BUILD_KVM_RW_HW(kscratch1,      l,  MIPS_CP0_DESAVE,       2)
 760 __BUILD_KVM_RW_HW(kscratch2,      l,  MIPS_CP0_DESAVE,       3)
 761 __BUILD_KVM_RW_HW(kscratch3,      l,  MIPS_CP0_DESAVE,       4)
 762 __BUILD_KVM_RW_HW(kscratch4,      l,  MIPS_CP0_DESAVE,       5)
 763 __BUILD_KVM_RW_HW(kscratch5,      l,  MIPS_CP0_DESAVE,       6)
 764 __BUILD_KVM_RW_HW(kscratch6,      l,  MIPS_CP0_DESAVE,       7)
 765
 766 /* Bitwise operations (on HW state) */
 767 __BUILD_KVM_SET_HW(status,        32, MIPS_CP0_STATUS,       0)
 768 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 769 __BUILD_KVM_ATOMIC_HW(cause,      32, MIPS_CP0_CAUSE,        0)
 770 __BUILD_KVM_SET_HW(ebase,         l,  MIPS_CP0_PRID,         1)
 771
 772 /* Bitwise operations (on saved state) */
 773 __BUILD_KVM_SET_SAVED(config,     32, MIPS_CP0_CONFIG,       0)
 774 __BUILD_KVM_SET_SAVED(config1,    32, MIPS_CP0_CONFIG,       1)
 775 __BUILD_KVM_SET_SAVED(config2,    32, MIPS_CP0_CONFIG,       2)
 776 __BUILD_KVM_SET_SAVED(config3,    32, MIPS_CP0_CONFIG,       3)
 777 __BUILD_KVM_SET_SAVED(config4,    32, MIPS_CP0_CONFIG,       4)
 778 __BUILD_KVM_SET_SAVED(config5,    32, MIPS_CP0_CONFIG,       5)
 779
 780 /* Helpers */
 781
 782 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 783 {
 784         return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
 785                 vcpu->fpu_enabled;
 786 }
 787
 788 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 789 {
 790         return kvm_mips_guest_can_have_fpu(vcpu) &&
 791                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 792 }
 793
 794 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 795 {
 796         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 797                 vcpu->msa_enabled;
 798 }
 799
 800 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 801 {
 802         return kvm_mips_guest_can_have_msa(vcpu) &&
 803                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 804 }
 805
 806 struct kvm_mips_callbacks {
 807         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 808         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 809         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 810         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 811         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 812         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 813         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 814         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 815         int (*handle_break)(struct kvm_vcpu *vcpu);
 816         int (*handle_trap)(struct kvm_vcpu *vcpu);
 817         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 818         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 819         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 820         int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
 821         int (*hardware_enable)(void);
 822         void (*hardware_disable)(void);
 823         int (*check_extension)(struct kvm *kvm, long ext);
 824         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 825         void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
 826         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 827         void (*flush_shadow_all)(struct kvm *kvm);
 828         /*
 829          * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
 830          * VZ root TLB, or T&E GVA page tables and corresponding root TLB
 831          * mappings).
 832          */
 833         void (*flush_shadow_memslot)(struct kvm *kvm,
 834                                      const struct kvm_memory_slot *slot);
 835         gpa_t (*gva_to_gpa)(gva_t gva);
 836         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 837         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 838         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 839                              struct kvm_mips_interrupt *irq);
 840         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 841                                struct kvm_mips_interrupt *irq);
 842         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 843                            u32 cause);
 844         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 845                          u32 cause);
 846         unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
 847         int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
 848         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 849                            const struct kvm_one_reg *reg, s64 *v);
 850         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 851                            const struct kvm_one_reg *reg, s64 v);
 852         int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
 853         int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
 854         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 855         void (*vcpu_reenter)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 856 };
 857 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 858 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 859
 860 /* Debug: dump vcpu state */
 861 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 862
 863 extern int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu);
 864
 865 /* Building of entry/exception code */
 866 int kvm_mips_entry_setup(void);
 867 void *kvm_mips_build_vcpu_run(void *addr);
 868 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
 869 void *kvm_mips_build_exception(void *addr, void *handler);
 870 void *kvm_mips_build_exit(void *addr);
 871
 872 /* FPU/MSA context management */
 873 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 874 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 875 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 876 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 877 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 878 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 879 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 880 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 881 void kvm_own_msa(struct kvm_vcpu *vcpu);
 882 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 883 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 884
 885 /* TLB handling */
 886 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 887
 888 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
 889
 890 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 891
 892 #ifdef CONFIG_KVM_MIPS_VZ
 893 int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
 894                                       struct kvm_vcpu *vcpu, bool write_fault);
 895 #endif
 896 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 897                                            struct kvm_vcpu *vcpu,
 898                                            bool write_fault);
 899
 900 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 901                                               struct kvm_vcpu *vcpu);
 902
 903 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 904                                                 struct kvm_mips_tlb *tlb,
 905                                                 unsigned long gva,
 906                                                 bool write_fault);
 907
 908 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
 909                                                      u32 *opc,
 910                                                      struct kvm_run *run,
 911                                                      struct kvm_vcpu *vcpu,
 912                                                      bool write_fault);
 913
 914 extern void kvm_mips_dump_host_tlbs(void);
 915 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 916 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi,
 917                                  bool user, bool kernel);
 918
 919 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 920                                      unsigned long entryhi);
 921
 922 #ifdef CONFIG_KVM_MIPS_VZ
 923 int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 924 int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
 925                             unsigned long *gpa);
 926 void kvm_vz_local_flush_roottlb_all_guests(void);
 927 void kvm_vz_local_flush_guesttlb_all(void);
 928 void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
 929                           unsigned int count);
 930 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
 931                           unsigned int count);
 932 #endif
 933
 934 void kvm_mips_suspend_mm(int cpu);
 935 void kvm_mips_resume_mm(int cpu);
 936
 937 /* MMU handling */
 938
 939 /**
 940  * enum kvm_mips_flush - Types of MMU flushes.
 941  * @KMF_USER:   Flush guest user virtual memory mappings.
 942  *              Guest USeg only.
 943  * @KMF_KERN:   Flush guest kernel virtual memory mappings.
 944  *              Guest USeg and KSeg2/3.
 945  * @KMF_GPA:    Flush guest physical memory mappings.
 946  *              Also includes KSeg0 if KMF_KERN is set.
 947  */
 948 enum kvm_mips_flush {
 949         KMF_USER        = 0x0,
 950         KMF_KERN        = 0x1,
 951         KMF_GPA         = 0x2,
 952 };
 953 void kvm_mips_flush_gva_pt(pgd_t *pgd, enum kvm_mips_flush flags);
 954 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 955 int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
 956 pgd_t *kvm_pgd_alloc(void);
 957 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 958 void kvm_trap_emul_invalidate_gva(struct kvm_vcpu *vcpu, unsigned long addr,
 959                                   bool user);
 960 void kvm_trap_emul_gva_lockless_begin(struct kvm_vcpu *vcpu);
 961 void kvm_trap_emul_gva_lockless_end(struct kvm_vcpu *vcpu);
 962
 963 enum kvm_mips_fault_result {
 964         KVM_MIPS_MAPPED = 0,
 965         KVM_MIPS_GVA,
 966         KVM_MIPS_GPA,
 967         KVM_MIPS_TLB,
 968         KVM_MIPS_TLBINV,
 969         KVM_MIPS_TLBMOD,
 970 };
 971 enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu,
 972                                                    unsigned long gva,
 973                                                    bool write);
 974
 975 #define KVM_ARCH_WANT_MMU_NOTIFIER
 976 int kvm_unmap_hva_range(struct kvm *kvm,
 977                         unsigned long start, unsigned long end);
 978 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 979 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 980 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 981
 982 /* Emulation */
 983 int kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 984 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
 985 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 986 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
 987
 988 /**
 989  * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
 990  * @vcpu:       Virtual CPU.
 991  *
 992  * Returns:     Whether the TLBL exception was likely due to an instruction
 993  *              fetch fault rather than a data load fault.
 994  */
 995 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
 996 {
 997         unsigned long badvaddr = vcpu->host_cp0_badvaddr;
 998         unsigned long epc = msk_isa16_mode(vcpu->pc);
 999         u32 cause = vcpu->host_cp0_cause;
1000
1001         if (epc == badvaddr)
1002                 return true;
1003
1004         /*
1005          * Branches may be 32-bit or 16-bit instructions.
1006          * This isn't exact, but we don't really support MIPS16 or microMIPS yet
1007          * in KVM anyway.
1008          */
1009         if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
1010                 return true;
1011
1012         return false;
1013 }
1014
1015 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
1016                                                    u32 *opc,
1017                                                    struct kvm_run *run,
1018                                                    struct kvm_vcpu *vcpu);
1019
1020 long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu);
1021
1022 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
1023                                                       u32 *opc,
1024                                                       struct kvm_run *run,
1025                                                       struct kvm_vcpu *vcpu);
1026
1027 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
1028                                                          u32 *opc,
1029                                                          struct kvm_run *run,
1030                                                          struct kvm_vcpu *vcpu);
1031
1032 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
1033                                                         u32 *opc,
1034                                                         struct kvm_run *run,
1035                                                         struct kvm_vcpu *vcpu);
1036
1037 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
1038                                                          u32 *opc,
1039                                                          struct kvm_run *run,
1040                                                          struct kvm_vcpu *vcpu);
1041
1042 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
1043                                                         u32 *opc,
1044                                                         struct kvm_run *run,
1045                                                         struct kvm_vcpu *vcpu);
1046
1047 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1048                                                      u32 *opc,
1049                                                      struct kvm_run *run,
1050                                                      struct kvm_vcpu *vcpu);
1051
1052 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
1053                                                       u32 *opc,
1054                                                       struct kvm_run *run,
1055                                                       struct kvm_vcpu *vcpu);
1056
1057 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
1058                                                 u32 *opc,
1059                                                 struct kvm_run *run,
1060                                                 struct kvm_vcpu *vcpu);
1061
1062 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
1063                                                      u32 *opc,
1064                                                      struct kvm_run *run,
1065                                                      struct kvm_vcpu *vcpu);
1066
1067 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
1068                                                      u32 *opc,
1069                                                      struct kvm_run *run,
1070                                                      struct kvm_vcpu *vcpu);
1071
1072 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
1073                                                        u32 *opc,
1074                                                        struct kvm_run *run,
1075                                                        struct kvm_vcpu *vcpu);
1076
1077 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
1078                                                          u32 *opc,
1079                                                          struct kvm_run *run,
1080                                                          struct kvm_vcpu *vcpu);
1081
1082 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
1083                                                       u32 *opc,
1084                                                       struct kvm_run *run,
1085                                                       struct kvm_vcpu *vcpu);
1086
1087 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
1088                                                          u32 *opc,
1089                                                          struct kvm_run *run,
1090                                                          struct kvm_vcpu *vcpu);
1091
1092 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
1093                                                          struct kvm_run *run);
1094
1095 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
1096 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
1097 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
1098 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
1099 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
1100 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
1101 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
1102 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
1103 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
1104 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
1105
1106 /* fairly internal functions requiring some care to use */
1107 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
1108 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
1109 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
1110                              u32 count, int min_drift);
1111
1112 #ifdef CONFIG_KVM_MIPS_VZ
1113 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
1114 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
1115 #else
1116 static inline void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) {}
1117 static inline void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu) {}
1118 #endif
1119
1120 enum emulation_result kvm_mips_check_privilege(u32 cause,
1121                                                u32 *opc,
1122                                                struct kvm_run *run,
1123                                                struct kvm_vcpu *vcpu);
1124
1125 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
1126                                              u32 *opc,
1127                                              u32 cause,
1128                                              struct kvm_run *run,
1129                                              struct kvm_vcpu *vcpu);
1130 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
1131                                            u32 *opc,
1132                                            u32 cause,
1133                                            struct kvm_run *run,
1134                                            struct kvm_vcpu *vcpu);
1135 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1136                                              u32 cause,
1137                                              struct kvm_run *run,
1138                                              struct kvm_vcpu *vcpu);
1139 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1140                                             u32 cause,
1141                                             struct kvm_run *run,
1142                                             struct kvm_vcpu *vcpu);
1143
1144 /* COP0 */
1145 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
1146
1147 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
1148 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
1149 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
1150 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
1151
1152 /* Hypercalls (hypcall.c) */
1153
1154 enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
1155                                             union mips_instruction inst);
1156 int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
1157
1158 /* Dynamic binary translation */
1159 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
1160                                       u32 *opc, struct kvm_vcpu *vcpu);
1161 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
1162                                    struct kvm_vcpu *vcpu);
1163 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
1164                                struct kvm_vcpu *vcpu);
1165 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
1166                                struct kvm_vcpu *vcpu);
1167
1168 /* Misc */
1169 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
1170 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
1171 extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1172                              struct kvm_mips_interrupt *irq);
1173
1174 static inline void kvm_arch_hardware_unsetup(void) {}
1175 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1176 static inline void kvm_arch_free_memslot(struct kvm *kvm,
1177                                          struct kvm_memory_slot *slot) {}
1178 static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
1179 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1180 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
1181 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
1182 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1183
1184 #endif /* __MIPS_KVM_HOST_H__ */