2 * head file for Ingenic Semiconductor's JZ4740 CPU.
7 #include <asm/addrspace.h>
8 #include <asm/cacheops.h>
10 /* Boot ROM Specification */
12 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
13 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
14 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
15 /* NAND Boot config */
16 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
17 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
18 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
19 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
21 /* 1st-level interrupts */
22 #define JZ4740_IRQ_I2C 1
23 #define JZ4740_IRQ_UHC 3
24 #define JZ4740_IRQ_UART0 9
25 #define JZ4740_IRQ_SADC 12
26 #define JZ4740_IRQ_MSC 14
27 #define JZ4740_IRQ_RTC 15
28 #define JZ4740_IRQ_SSI 16
29 #define JZ4740_IRQ_CIM 17
30 #define JZ4740_IRQ_AIC 18
31 #define JZ4740_IRQ_ETH 19
32 #define JZ4740_IRQ_DMAC 20
33 #define JZ4740_IRQ_TCU2 21
34 #define JZ4740_IRQ_TCU1 22
35 #define JZ4740_IRQ_TCU0 23
36 #define JZ4740_IRQ_UDC 24
37 #define JZ4740_IRQ_GPIO3 25
38 #define JZ4740_IRQ_GPIO2 26
39 #define JZ4740_IRQ_GPIO1 27
40 #define JZ4740_IRQ_GPIO0 28
41 #define JZ4740_IRQ_IPU 29
42 #define JZ4740_IRQ_LCD 30
43 /* 2nd-level interrupts */
44 #define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
45 #define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
47 /* Register Definitions */
48 #define JZ4740_CPM_BASE 0x10000000
49 #define JZ4740_INTC_BASE 0x10001000
50 #define JZ4740_TCU_BASE 0x10002000
51 #define JZ4740_WDT_BASE 0x10002000
52 #define JZ4740_RTC_BASE 0x10003000
53 #define JZ4740_GPIO_BASE 0x10010000
54 #define JZ4740_AIC_BASE 0x10020000
55 #define JZ4740_ICDC_BASE 0x10020000
56 #define JZ4740_MSC_BASE 0x10021000
57 #define JZ4740_UART0_BASE 0x10030000
58 #define JZ4740_I2C_BASE 0x10042000
59 #define JZ4740_SSI_BASE 0x10043000
60 #define JZ4740_SADC_BASE 0x10070000
61 #define JZ4740_EMC_BASE 0x13010000
62 #define JZ4740_DMAC_BASE 0x13020000
63 #define JZ4740_UHC_BASE 0x13030000
64 #define JZ4740_UDC_BASE 0x13040000
65 #define JZ4740_LCD_BASE 0x13050000
66 #define JZ4740_SLCD_BASE 0x13050000
67 #define JZ4740_CIM_BASE 0x13060000
68 #define JZ4740_ETH_BASE 0x13100000
70 /* 8bit Mode Register of SDRAM bank 0 */
71 #define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000)
73 /* GPIO (General-Purpose I/O Ports) */
75 #define GPIO_PXPIN(n) \
76 (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
77 #define GPIO_PXDAT(n) \
78 (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
79 #define GPIO_PXDATS(n) \
80 (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
81 #define GPIO_PXDATC(n) \
82 (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
83 #define GPIO_PXIM(n) \
84 (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
85 #define GPIO_PXIMS(n) \
86 (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
87 #define GPIO_PXIMC(n) \
88 (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
89 #define GPIO_PXPE(n) \
90 (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
91 #define GPIO_PXPES(n) \
92 (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
93 #define GPIO_PXPEC(n) \
94 (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
95 #define GPIO_PXFUN(n) \
96 (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
97 #define GPIO_PXFUNS(n) \
98 (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
99 #define GPIO_PXFUNC(n) \
100 (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
101 #define GPIO_PXSEL(n) \
102 (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
103 #define GPIO_PXSELS(n) \
104 (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
105 #define GPIO_PXSELC(n) \
106 (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
107 #define GPIO_PXDIR(n) \
108 (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
109 #define GPIO_PXDIRS(n) \
110 (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
111 #define GPIO_PXDIRC(n) \
112 (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
113 #define GPIO_PXTRG(n) \
114 (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
115 #define GPIO_PXTRGS(n) \
116 (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
117 #define GPIO_PXTRGC(n) \
118 (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
120 /* Static Memory Control Register */
121 #define EMC_SMCR_STRV_BIT 24
122 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
123 #define EMC_SMCR_TAW_BIT 20
124 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
125 #define EMC_SMCR_TBP_BIT 16
126 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
127 #define EMC_SMCR_TAH_BIT 12
128 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
129 #define EMC_SMCR_TAS_BIT 8
130 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
131 #define EMC_SMCR_BW_BIT 6
132 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
133 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
134 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
135 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
136 #define EMC_SMCR_BCM (1 << 3)
137 #define EMC_SMCR_BL_BIT 1
138 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
139 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
140 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
141 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
142 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
143 #define EMC_SMCR_SMT (1 << 0)
145 /* Static Memory Bank Addr Config Reg */
146 #define EMC_SACR_BASE_BIT 8
147 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
148 #define EMC_SACR_MASK_BIT 0
149 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
151 /* NAND Flash Control/Status Register */
152 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
153 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
154 #define EMC_NFCSR_NFCE3 (1 << 5)
155 #define EMC_NFCSR_NFE3 (1 << 4)
156 #define EMC_NFCSR_NFCE2 (1 << 3)
157 #define EMC_NFCSR_NFE2 (1 << 2)
158 #define EMC_NFCSR_NFCE1 (1 << 1)
159 #define EMC_NFCSR_NFE1 (1 << 0)
161 /* NAND Flash ECC Control Register */
162 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
163 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
164 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
165 #define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */
166 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
167 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
168 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
170 /* NAND Flash ECC Data Register */
171 #define EMC_NFECC_ECC2_BIT 16
172 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
173 #define EMC_NFECC_ECC1_BIT 8
174 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
175 #define EMC_NFECC_ECC0_BIT 0
176 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
178 /* NAND Flash Interrupt Status Register */
179 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
180 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
181 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
182 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
183 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
184 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
185 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
187 /* NAND Flash Interrupt Enable Register */
188 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */
189 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */
190 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */
191 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */
192 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
194 /* NAND Flash RS Error Report Register */
195 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
196 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
197 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
198 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
200 /* DRAM Control Register */
201 #define EMC_DMCR_BW_BIT 31
202 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
203 #define EMC_DMCR_CA_BIT 26
204 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
205 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
206 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
207 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
208 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
209 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
210 #define EMC_DMCR_RMODE (1 << 25)
211 #define EMC_DMCR_RFSH (1 << 24)
212 #define EMC_DMCR_MRSET (1 << 23)
213 #define EMC_DMCR_RA_BIT 20
214 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
215 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
216 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
217 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
218 #define EMC_DMCR_BA_BIT 19
219 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
220 #define EMC_DMCR_PDM (1 << 18)
221 #define EMC_DMCR_EPIN (1 << 17)
222 #define EMC_DMCR_TRAS_BIT 13
223 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
224 #define EMC_DMCR_RCD_BIT 11
225 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
226 #define EMC_DMCR_TPC_BIT 8
227 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
228 #define EMC_DMCR_TRWL_BIT 5
229 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
230 #define EMC_DMCR_TRC_BIT 2
231 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
232 #define EMC_DMCR_TCL_BIT 0
233 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
235 /* Refresh Time Control/Status Register */
236 #define EMC_RTCSR_CMF (1 << 7)
237 #define EMC_RTCSR_CKS_BIT 0
238 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
239 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
240 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
241 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
242 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
243 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
244 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
245 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
246 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
248 /* SDRAM Bank Address Configuration Register */
249 #define EMC_DMAR_BASE_BIT 8
250 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
251 #define EMC_DMAR_MASK_BIT 0
252 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
254 /* Mode Register of SDRAM bank 0 */
255 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
256 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */
257 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
258 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
259 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
260 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
261 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
262 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
263 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
264 #define EMC_SDMR_BT_BIT 3 /* Burst Type */
265 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
266 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
267 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
268 #define EMC_SDMR_BL_BIT 0 /* Burst Length */
269 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
270 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
271 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
272 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
273 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
275 #define EMC_SDMR_CAS2_16BIT \
276 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
277 #define EMC_SDMR_CAS2_32BIT \
278 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
279 #define EMC_SDMR_CAS3_16BIT \
280 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
281 #define EMC_SDMR_CAS3_32BIT \
282 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
284 /* RTC Control Register */
285 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
286 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
287 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
288 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */
289 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
290 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */
291 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
293 /* RTC Regulator Register */
294 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
295 #define RTC_RGR_ADJC_BIT 16
296 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
297 #define RTC_RGR_NC1HZ_BIT 0
298 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
300 /* Hibernate Control Register */
301 #define RTC_HCR_PD (1 << 0) /* Power Down */
303 /* Hibernate Wakeup Filter Counter Register */
304 #define RTC_HWFCR_BIT 5
305 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
307 /* Hibernate Reset Counter Register */
308 #define RTC_HRCR_BIT 5
309 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
311 /* Hibernate Wakeup Control Register */
312 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
314 /* Hibernate Wakeup Status Register */
315 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
316 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
317 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
318 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
320 /* Clock Control Register */
321 #define CPM_CPCCR_I2CS (1 << 31)
322 #define CPM_CPCCR_CLKOEN (1 << 30)
323 #define CPM_CPCCR_UCS (1 << 29)
324 #define CPM_CPCCR_UDIV_BIT 23
325 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
326 #define CPM_CPCCR_CE (1 << 22)
327 #define CPM_CPCCR_PCS (1 << 21)
328 #define CPM_CPCCR_LDIV_BIT 16
329 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
330 #define CPM_CPCCR_MDIV_BIT 12
331 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
332 #define CPM_CPCCR_PDIV_BIT 8
333 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
334 #define CPM_CPCCR_HDIV_BIT 4
335 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
336 #define CPM_CPCCR_CDIV_BIT 0
337 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
339 /* I2S Clock Divider Register */
340 #define CPM_I2SCDR_I2SDIV_BIT 0
341 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
343 /* LCD Pixel Clock Divider Register */
344 #define CPM_LPCDR_PIXDIV_BIT 0
345 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
347 /* MSC Clock Divider Register */
348 #define CPM_MSCCDR_MSCDIV_BIT 0
349 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
351 /* PLL Control Register */
352 #define CPM_CPPCR_PLLM_BIT 23
353 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
354 #define CPM_CPPCR_PLLN_BIT 18
355 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
356 #define CPM_CPPCR_PLLOD_BIT 16
357 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
358 #define CPM_CPPCR_PLLS (1 << 10)
359 #define CPM_CPPCR_PLLBP (1 << 9)
360 #define CPM_CPPCR_PLLEN (1 << 8)
361 #define CPM_CPPCR_PLLST_BIT 0
362 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
364 /* Low Power Control Register */
365 #define CPM_LCR_DOZE_DUTY_BIT 3
366 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
367 #define CPM_LCR_DOZE_ON (1 << 2)
368 #define CPM_LCR_LPM_BIT 0
369 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
370 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
371 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
373 /* Clock Gate Register */
374 #define CPM_CLKGR_UART1 (1 << 15)
375 #define CPM_CLKGR_UHC (1 << 14)
376 #define CPM_CLKGR_IPU (1 << 13)
377 #define CPM_CLKGR_DMAC (1 << 12)
378 #define CPM_CLKGR_UDC (1 << 11)
379 #define CPM_CLKGR_LCD (1 << 10)
380 #define CPM_CLKGR_CIM (1 << 9)
381 #define CPM_CLKGR_SADC (1 << 8)
382 #define CPM_CLKGR_MSC (1 << 7)
383 #define CPM_CLKGR_AIC1 (1 << 6)
384 #define CPM_CLKGR_AIC2 (1 << 5)
385 #define CPM_CLKGR_SSI (1 << 4)
386 #define CPM_CLKGR_I2C (1 << 3)
387 #define CPM_CLKGR_RTC (1 << 2)
388 #define CPM_CLKGR_TCU (1 << 1)
389 #define CPM_CLKGR_UART0 (1 << 0)
391 /* Sleep Control Register */
392 #define CPM_SCR_O1ST_BIT 8
393 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
394 #define CPM_SCR_UDCPHY_ENABLE (1 << 6)
395 #define CPM_SCR_USBPHY_DISABLE (1 << 7)
396 #define CPM_SCR_OSC_ENABLE (1 << 4)
398 /* Hibernate Control Register */
399 #define CPM_HCR_PD (1 << 0)
401 /* Wakeup Filter Counter Register in Hibernate Mode */
402 #define CPM_HWFCR_TIME_BIT 0
403 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
405 /* Reset Counter Register in Hibernate Mode */
406 #define CPM_HRCR_TIME_BIT 0
407 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
409 /* Wakeup Control Register in Hibernate Mode */
410 #define CPM_HWCR_WLE_LOW (0 << 2)
411 #define CPM_HWCR_WLE_HIGH (1 << 2)
412 #define CPM_HWCR_PIN_WAKEUP (1 << 1)
413 #define CPM_HWCR_RTC_WAKEUP (1 << 0)
415 /* Wakeup Status Register in Hibernate Mode */
416 #define CPM_HWSR_WSR_PIN (1 << 1)
417 #define CPM_HWSR_WSR_RTC (1 << 0)
419 /* Reset Status Register */
420 #define CPM_RSR_HR (1 << 2)
421 #define CPM_RSR_WR (1 << 1)
422 #define CPM_RSR_PR (1 << 0)
424 /* Register definitions */
425 #define TCU_TCSR_PWM_SD (1 << 9)
426 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
427 #define TCU_TCSR_PWM_EN (1 << 7)
428 #define TCU_TCSR_PRESCALE_BIT 3
429 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
430 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
431 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
432 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
433 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
434 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
435 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
436 #define TCU_TCSR_EXT_EN (1 << 2)
437 #define TCU_TCSR_RTC_EN (1 << 1)
438 #define TCU_TCSR_PCK_EN (1 << 0)
440 #define TCU_TER_TCEN5 (1 << 5)
441 #define TCU_TER_TCEN4 (1 << 4)
442 #define TCU_TER_TCEN3 (1 << 3)
443 #define TCU_TER_TCEN2 (1 << 2)
444 #define TCU_TER_TCEN1 (1 << 1)
445 #define TCU_TER_TCEN0 (1 << 0)
447 #define TCU_TESR_TCST5 (1 << 5)
448 #define TCU_TESR_TCST4 (1 << 4)
449 #define TCU_TESR_TCST3 (1 << 3)
450 #define TCU_TESR_TCST2 (1 << 2)
451 #define TCU_TESR_TCST1 (1 << 1)
452 #define TCU_TESR_TCST0 (1 << 0)
454 #define TCU_TECR_TCCL5 (1 << 5)
455 #define TCU_TECR_TCCL4 (1 << 4)
456 #define TCU_TECR_TCCL3 (1 << 3)
457 #define TCU_TECR_TCCL2 (1 << 2)
458 #define TCU_TECR_TCCL1 (1 << 1)
459 #define TCU_TECR_TCCL0 (1 << 0)
461 #define TCU_TFR_HFLAG5 (1 << 21)
462 #define TCU_TFR_HFLAG4 (1 << 20)
463 #define TCU_TFR_HFLAG3 (1 << 19)
464 #define TCU_TFR_HFLAG2 (1 << 18)
465 #define TCU_TFR_HFLAG1 (1 << 17)
466 #define TCU_TFR_HFLAG0 (1 << 16)
467 #define TCU_TFR_FFLAG5 (1 << 5)
468 #define TCU_TFR_FFLAG4 (1 << 4)
469 #define TCU_TFR_FFLAG3 (1 << 3)
470 #define TCU_TFR_FFLAG2 (1 << 2)
471 #define TCU_TFR_FFLAG1 (1 << 1)
472 #define TCU_TFR_FFLAG0 (1 << 0)
474 #define TCU_TFSR_HFLAG5 (1 << 21)
475 #define TCU_TFSR_HFLAG4 (1 << 20)
476 #define TCU_TFSR_HFLAG3 (1 << 19)
477 #define TCU_TFSR_HFLAG2 (1 << 18)
478 #define TCU_TFSR_HFLAG1 (1 << 17)
479 #define TCU_TFSR_HFLAG0 (1 << 16)
480 #define TCU_TFSR_FFLAG5 (1 << 5)
481 #define TCU_TFSR_FFLAG4 (1 << 4)
482 #define TCU_TFSR_FFLAG3 (1 << 3)
483 #define TCU_TFSR_FFLAG2 (1 << 2)
484 #define TCU_TFSR_FFLAG1 (1 << 1)
485 #define TCU_TFSR_FFLAG0 (1 << 0)
487 #define TCU_TFCR_HFLAG5 (1 << 21)
488 #define TCU_TFCR_HFLAG4 (1 << 20)
489 #define TCU_TFCR_HFLAG3 (1 << 19)
490 #define TCU_TFCR_HFLAG2 (1 << 18)
491 #define TCU_TFCR_HFLAG1 (1 << 17)
492 #define TCU_TFCR_HFLAG0 (1 << 16)
493 #define TCU_TFCR_FFLAG5 (1 << 5)
494 #define TCU_TFCR_FFLAG4 (1 << 4)
495 #define TCU_TFCR_FFLAG3 (1 << 3)
496 #define TCU_TFCR_FFLAG2 (1 << 2)
497 #define TCU_TFCR_FFLAG1 (1 << 1)
498 #define TCU_TFCR_FFLAG0 (1 << 0)
500 #define TCU_TMR_HMASK5 (1 << 21)
501 #define TCU_TMR_HMASK4 (1 << 20)
502 #define TCU_TMR_HMASK3 (1 << 19)
503 #define TCU_TMR_HMASK2 (1 << 18)
504 #define TCU_TMR_HMASK1 (1 << 17)
505 #define TCU_TMR_HMASK0 (1 << 16)
506 #define TCU_TMR_FMASK5 (1 << 5)
507 #define TCU_TMR_FMASK4 (1 << 4)
508 #define TCU_TMR_FMASK3 (1 << 3)
509 #define TCU_TMR_FMASK2 (1 << 2)
510 #define TCU_TMR_FMASK1 (1 << 1)
511 #define TCU_TMR_FMASK0 (1 << 0)
513 #define TCU_TMSR_HMST5 (1 << 21)
514 #define TCU_TMSR_HMST4 (1 << 20)
515 #define TCU_TMSR_HMST3 (1 << 19)
516 #define TCU_TMSR_HMST2 (1 << 18)
517 #define TCU_TMSR_HMST1 (1 << 17)
518 #define TCU_TMSR_HMST0 (1 << 16)
519 #define TCU_TMSR_FMST5 (1 << 5)
520 #define TCU_TMSR_FMST4 (1 << 4)
521 #define TCU_TMSR_FMST3 (1 << 3)
522 #define TCU_TMSR_FMST2 (1 << 2)
523 #define TCU_TMSR_FMST1 (1 << 1)
524 #define TCU_TMSR_FMST0 (1 << 0)
526 #define TCU_TMCR_HMCL5 (1 << 21)
527 #define TCU_TMCR_HMCL4 (1 << 20)
528 #define TCU_TMCR_HMCL3 (1 << 19)
529 #define TCU_TMCR_HMCL2 (1 << 18)
530 #define TCU_TMCR_HMCL1 (1 << 17)
531 #define TCU_TMCR_HMCL0 (1 << 16)
532 #define TCU_TMCR_FMCL5 (1 << 5)
533 #define TCU_TMCR_FMCL4 (1 << 4)
534 #define TCU_TMCR_FMCL3 (1 << 3)
535 #define TCU_TMCR_FMCL2 (1 << 2)
536 #define TCU_TMCR_FMCL1 (1 << 1)
537 #define TCU_TMCR_FMCL0 (1 << 0)
539 #define TCU_TSR_WDTS (1 << 16)
540 #define TCU_TSR_STOP5 (1 << 5)
541 #define TCU_TSR_STOP4 (1 << 4)
542 #define TCU_TSR_STOP3 (1 << 3)
543 #define TCU_TSR_STOP2 (1 << 2)
544 #define TCU_TSR_STOP1 (1 << 1)
545 #define TCU_TSR_STOP0 (1 << 0)
547 #define TCU_TSSR_WDTSS (1 << 16)
548 #define TCU_TSSR_STPS5 (1 << 5)
549 #define TCU_TSSR_STPS4 (1 << 4)
550 #define TCU_TSSR_STPS3 (1 << 3)
551 #define TCU_TSSR_STPS2 (1 << 2)
552 #define TCU_TSSR_STPS1 (1 << 1)
553 #define TCU_TSSR_STPS0 (1 << 0)
555 #define TCU_TSSR_WDTSC (1 << 16)
556 #define TCU_TSSR_STPC5 (1 << 5)
557 #define TCU_TSSR_STPC4 (1 << 4)
558 #define TCU_TSSR_STPC3 (1 << 3)
559 #define TCU_TSSR_STPC2 (1 << 2)
560 #define TCU_TSSR_STPC1 (1 << 1)
561 #define TCU_TSSR_STPC0 (1 << 0)
563 /* Register definition */
564 #define WDT_TCSR_PRESCALE_BIT 3
565 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
566 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
567 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
568 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
569 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
570 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
571 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
572 #define WDT_TCSR_EXT_EN (1 << 2)
573 #define WDT_TCSR_RTC_EN (1 << 1)
574 #define WDT_TCSR_PCK_EN (1 << 0)
575 #define WDT_TCER_TCEN (1 << 0)
578 * Define macros for UART_IER
579 * UART Interrupt Enable Register
581 #define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */
582 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */
583 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
584 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
585 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
588 * Define macros for UART_ISR
589 * UART Interrupt Status Register
591 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
592 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */
593 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
594 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
595 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
596 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
597 /* FIFO mode select, set when UART_FCR.FE is set to 1 */
598 #define UART_ISR_FFMS (3 << 6)
599 #define UART_ISR_FFMS_NO_FIFO (0 << 6)
600 #define UART_ISR_FFMS_FIFO_MODE (3 << 6)
603 * Define macros for UART_FCR
604 * UART FIFO Control Register
606 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
607 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
608 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
609 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
610 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */
611 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
612 #define UART_FCR_RTRG_1 (0 << 6)
613 #define UART_FCR_RTRG_4 (1 << 6)
614 #define UART_FCR_RTRG_8 (2 << 6)
615 #define UART_FCR_RTRG_15 (3 << 6)
618 * Define macros for UART_LCR
619 * UART Line Control Register
621 #define UART_LCR_WLEN (3 << 0) /* word length */
622 #define UART_LCR_WLEN_5 (0 << 0)
623 #define UART_LCR_WLEN_6 (1 << 0)
624 #define UART_LCR_WLEN_7 (2 << 0)
625 #define UART_LCR_WLEN_8 (3 << 0)
626 #define UART_LCR_STOP (1 << 2)
627 /* 0: 1 stop bit when word length is 5,6,7,8
628 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
629 #define UART_LCR_STOP_1 (0 << 2)
630 /* 0: 1 stop bit when word length is 5,6,7,8
631 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
632 #define UART_LCR_STOP_2 (1 << 2)
633 /* 0: 1 stop bit when word length is 5,6,7,8
634 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
636 #define UART_LCR_PE (1 << 3) /* 0: parity disable */
637 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
638 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
639 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
640 /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
641 #define UART_LCR_DLAB (1 << 7)
644 * Define macros for UART_LSR
645 * UART Line Status Register
647 /* 0: receive FIFO is empty 1: receive data is ready */
648 #define UART_LSR_DR (1 << 0)
649 /* 0: no overrun error */
650 #define UART_LSR_ORER (1 << 1)
651 /* 0: no parity error */
652 #define UART_LSR_PER (1 << 2)
653 /* 0; no framing error */
654 #define UART_LSR_FER (1 << 3)
655 /* 0: no break detected 1: receive a break signal */
656 #define UART_LSR_BRK (1 << 4)
657 /* 1: transmit FIFO half "empty" */
658 #define UART_LSR_TDRQ (1 << 5)
659 /* 1: transmit FIFO and shift registers empty */
660 #define UART_LSR_TEMT (1 << 6)
661 /* 0: no receive error 1: receive error in FIFO mode */
662 #define UART_LSR_RFER (1 << 7)
665 * Define macros for UART_MCR
666 * UART Modem Control Register
668 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
669 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
670 /* 0: UART_MSR.RI is set to 0 and RI_ input high */
671 #define UART_MCR_OUT1 (1 << 2)
672 /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
673 #define UART_MCR_OUT2 (1 << 3)
674 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
675 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
678 * Define macros for UART_MSR
679 * UART Modem Status Register
681 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */
682 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */
683 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */
684 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */
685 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
686 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
687 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
688 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
691 * Define macros for SIRCR
692 * Slow IrDA Control Register
694 #define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
695 #define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
696 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
697 1: 0 pulse width is 1.6us for 115.2Kbps */
698 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
699 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
701 /* MSC Clock and Control Register (MSC_STRPCL) */
702 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
703 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
704 #define MSC_STRPCL_START_READWAIT (1 << 5)
705 #define MSC_STRPCL_STOP_READWAIT (1 << 4)
706 #define MSC_STRPCL_RESET (1 << 3)
707 #define MSC_STRPCL_START_OP (1 << 2)
708 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0
709 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
710 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
711 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
713 /* MSC Status Register (MSC_STAT) */
714 #define MSC_STAT_IS_RESETTING (1 << 15)
715 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
716 #define MSC_STAT_PRG_DONE (1 << 13)
717 #define MSC_STAT_DATA_TRAN_DONE (1 << 12)
718 #define MSC_STAT_END_CMD_RES (1 << 11)
719 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
720 #define MSC_STAT_IS_READWAIT (1 << 9)
721 #define MSC_STAT_CLK_EN (1 << 8)
722 #define MSC_STAT_DATA_FIFO_FULL (1 << 7)
723 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
724 #define MSC_STAT_CRC_RES_ERR (1 << 5)
725 #define MSC_STAT_CRC_READ_ERROR (1 << 4)
726 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2
727 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
728 /* No error on transmission of data */
729 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
730 /* Card observed erroneous transmission of data */
731 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
732 /* No CRC status is sent back */
733 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
734 #define MSC_STAT_TIME_OUT_RES (1 << 1)
735 #define MSC_STAT_TIME_OUT_READ (1 << 0)
737 /* MSC Bus Clock Control Register (MSC_CLKRT) */
738 #define MSC_CLKRT_CLK_RATE_BIT 0
739 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
740 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT)
741 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT)
742 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT)
743 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT)
744 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT)
745 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT)
746 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT)
747 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
749 /* MSC Command Sequence Control Register (MSC_CMDAT) */
750 #define MSC_CMDAT_IO_ABORT (1 << 11)
751 #define MSC_CMDAT_BUS_WIDTH_BIT 9
752 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
753 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
754 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
755 #define MSC_CMDAT_DMA_EN (1 << 8)
756 #define MSC_CMDAT_INIT (1 << 7)
757 #define MSC_CMDAT_BUSY (1 << 6)
758 #define MSC_CMDAT_STREAM_BLOCK (1 << 5)
759 #define MSC_CMDAT_WRITE (1 << 4)
760 #define MSC_CMDAT_READ (0 << 4)
761 #define MSC_CMDAT_DATA_EN (1 << 3)
762 #define MSC_CMDAT_RESPONSE_BIT 0
763 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
764 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
765 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
766 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
767 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
768 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
769 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
770 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
772 /* MSC Interrupts Mask Register (MSC_IMASK) */
773 #define MSC_IMASK_SDIO (1 << 7)
774 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
775 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
776 #define MSC_IMASK_END_CMD_RES (1 << 2)
777 #define MSC_IMASK_PRG_DONE (1 << 1)
778 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
781 /* INTC (Interrupt Controller) */
783 uint32_t isr; /* interrupt source register */
784 uint32_t imr; /* interrupt mask register */
785 uint32_t imsr; /* interrupt mask set register */
786 uint32_t imcr; /* interrupt mask clear register */
787 uint32_t ipr; /* interrupt pending register */
792 uint32_t rcr; /* rtc control register */
793 uint32_t rsr; /* rtc second register */
794 uint32_t rsar; /* rtc second alarm register */
795 uint32_t rgr; /* rtc regulator register */
796 uint32_t hcr; /* hibernate control register */
797 uint32_t hwfcr; /* hibernate wakeup filter counter reg */
798 uint32_t hrcr; /* hibernate reset counter reg */
799 uint32_t hwcr; /* hibernate wakeup control register */
800 uint32_t hwrsr; /* hibernate wakeup status reg */
801 uint32_t hspr; /* scratch pattern register */
804 /* CPM (Clock reset and Power control Management) */
806 uint32_t cpccr; /* 0x00 clock control reg */
807 uint32_t lcr; /* 0x04 low power control reg */
808 uint32_t rsr; /* 0x08 reset status reg */
810 uint32_t cppcr; /* 0x10 pll control reg */
812 uint32_t clkgr; /* 0x20 clock gate reg */
813 uint32_t scr; /* 0x24 sleep control reg */
815 uint32_t i2scd; /* 0x60 I2S device clock divider reg */
816 uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
817 uint32_t msccdr; /* 0x68 MSC device clock divider reg */
818 uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
819 uint32_t uhcts; /* 0x70 UHC PHY test point reg */
820 uint32_t ssicd; /* 0x74 SSI clock divider reg */
823 /* TCU (Timer Counter Unit) */
826 uint32_t ter; /* 0x10 Timer Counter Enable Register */
827 uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */
828 uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */
829 uint32_t tsr; /* 0x1C Timer Stop Register */
830 uint32_t tfr; /* 0x20 Timer Flag Register */
831 uint32_t tfsr; /* 0x24 Timer Flag Set Register */
832 uint32_t tfcr; /* 0x28 Timer Flag Clear Register */
833 uint32_t tssr; /* 0x2C Timer Stop Set Register */
834 uint32_t tmr; /* 0x30 Timer Mask Register */
835 uint32_t tmsr; /* 0x34 Timer Mask Set Register */
836 uint32_t tmcr; /* 0x38 Timer Mask Clear Register */
837 uint32_t tscr; /* 0x3C Timer Stop Clear Register */
838 uint32_t tdfr0; /* 0x40 Timer Data Full Register */
839 uint32_t tdhr0; /* 0x44 Timer Data Half Register */
840 uint32_t tcnt0; /* 0x48 Timer Counter Register */
841 uint32_t tcsr0; /* 0x4C Timer Control Register */
842 uint32_t tdfr1; /* 0x50 */
843 uint32_t tdhr1; /* 0x54 */
844 uint32_t tcnt1; /* 0x58 */
845 uint32_t tcsr1; /* 0x5C */
846 uint32_t tdfr2; /* 0x60 */
847 uint32_t tdhr2; /* 0x64 */
848 uint32_t tcnt2; /* 0x68 */
849 uint32_t tcsr2; /* 0x6C */
850 uint32_t tdfr3; /* 0x70 */
851 uint32_t tdhr3; /* 0x74 */
852 uint32_t tcnt3; /* 0x78 */
853 uint32_t tcsr3; /* 0x7C */
854 uint32_t tdfr4; /* 0x80 */
855 uint32_t tdhr4; /* 0x84 */
856 uint32_t tcnt4; /* 0x88 */
857 uint32_t tcsr4; /* 0x8C */
858 uint32_t tdfr5; /* 0x90 */
859 uint32_t tdhr5; /* 0x94 */
860 uint32_t tcnt5; /* 0x98 */
861 uint32_t tcsr5; /* 0x9C */
864 /* WDT (WatchDog Timer) */
866 uint16_t tdr; /* 0x00 watchdog timer data reg*/
868 uint8_t tcer; /* 0x04 watchdog counter enable reg*/
870 uint16_t tcnt; /* 0x08 watchdog timer counter*/
872 uint16_t tcsr; /* 0x0C watchdog timer control reg*/
877 uint8_t rbr_thr_dllr;
878 /* 0x00 R 8b receive buffer reg */
879 /* 0x00 W 8b transmit hold reg */
880 /* 0x00 RW 8b divisor latch low reg */
883 /* 0x04 RW 8b divisor latch high reg */
884 /* 0x04 RW 8b interrupt enable reg */
887 /* 0x08 R 8b interrupt identification reg */
888 /* 0x08 W 8b FIFO control reg */
890 uint8_t lcr; /* 0x0C RW 8b Line control reg */
892 uint8_t mcr; /* 0x10 RW 8b modem control reg */
894 uint8_t lsr; /* 0x14 R 8b line status reg */
896 uint8_t msr; /* 0x18 R 8b modem status reg */
898 uint8_t spr; /* 0x1C RW 8b scratch pad reg */
900 uint8_t isr; /* 0x20 RW 8b infrared selection reg */
902 uint8_t umr; /* 0x24 RW 8b */
907 uint16_t strpcl;/* 0x00 */
908 uint32_t stat; /* 0x04 */
909 uint16_t clkrt; /* 0x08 */
910 uint32_t cmdat; /* 0x0C */
911 uint16_t resto; /* 0x10 */
912 uint16_t rdto; /* 0x14 */
913 uint16_t blklen;/* 0x18 */
914 uint16_t nob; /* 0x1C */
915 uint16_t snob; /* 0x20 */
916 uint16_t imask; /* 0x24 */
917 uint16_t ireg; /* 0x28 */
918 uint8_t cmd; /* 0x2C */
919 uint32_t arg; /* 0x30 */
920 uint16_t res; /* 0x34 */
921 uint32_t rxfifo;/* 0x38 */
922 uint32_t txfifo;/* 0x3C */
925 /* External Memory Controller */
927 uint32_t bcr; /* 0x00 BCR */
930 /* x10 Static Memory Control Register 0 */
931 /* x14 Static Memory Control Register 1 */
932 /* x18 Static Memory Control Register 2 */
933 /* x1c Static Memory Control Register 3 */
934 /* x20 Static Memory Control Register 4 */
937 /* x30 Static Memory Bank 0 Addr Config Reg */
938 /* x34 Static Memory Bank 1 Addr Config Reg */
939 /* x38 Static Memory Bank 2 Addr Config Reg */
940 /* x3c Static Memory Bank 3 Addr Config Reg */
941 /* x40 Static Memory Bank 4 Addr Config Reg */
943 uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
946 uint32_t dmcr; /* x80 DRAM Control Register */
947 uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
949 uint16_t rtcnt; /* x88 Refresh Timer Counter */
951 uint16_t rtcor; /* x8c Refresh Time Constant Register */
953 uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
955 uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
956 uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
958 /* x108 NAND Flash RS Parity 0 Register */
959 /* x10c NAND Flash RS Parity 1 Register */
960 /* x110 NAND Flash RS Parity 2 Register */
961 uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
962 uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
964 /* x11c NAND Flash RS Error Report 0 Register */
965 /* x120 NAND Flash RS Error Report 1 Register */
966 /* x124 NAND Flash RS Error Report 2 Register */
967 /* x128 NAND Flash RS Error Report 3 Register */
970 #define __gpio_as_nand() \
972 writel(0x02018000, GPIO_PXFUNS(1)); \
973 writel(0x02018000, GPIO_PXSELC(1)); \
974 writel(0x02018000, GPIO_PXPES(1)); \
975 writel(0x30000000, GPIO_PXFUNS(2)); \
976 writel(0x30000000, GPIO_PXSELC(2)); \
977 writel(0x30000000, GPIO_PXPES(2)); \
978 writel(0x40000000, GPIO_PXFUNC(2)); \
979 writel(0x40000000, GPIO_PXSELC(2)); \
980 writel(0x40000000, GPIO_PXDIRC(2)); \
981 writel(0x40000000, GPIO_PXPES(2)); \
982 writel(0x00400000, GPIO_PXFUNS(1)); \
983 writel(0x00400000, GPIO_PXSELC(1)); \
986 #define __gpio_as_sdram_16bit_4720() \
988 writel(0x5442bfaa, GPIO_PXFUNS(0)); \
989 writel(0x5442bfaa, GPIO_PXSELC(0)); \
990 writel(0x5442bfaa, GPIO_PXPES(0)); \
991 writel(0x81f9ffff, GPIO_PXFUNS(1)); \
992 writel(0x81f9ffff, GPIO_PXSELC(1)); \
993 writel(0x81f9ffff, GPIO_PXPES(1)); \
994 writel(0x01000000, GPIO_PXFUNS(2)); \
995 writel(0x01000000, GPIO_PXSELC(2)); \
996 writel(0x01000000, GPIO_PXPES(2)); \
999 #define __gpio_as_lcd_18bit() \
1001 writel(0x003fffff, GPIO_PXFUNS(2)); \
1002 writel(0x003fffff, GPIO_PXSELC(2)); \
1003 writel(0x003fffff, GPIO_PXPES(2)); \
1006 /* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
1007 #define __gpio_as_msc() \
1009 writel(0x00003f00, GPIO_PXFUNS(3)); \
1010 writel(0x00003f00, GPIO_PXSELC(3)); \
1011 writel(0x00003f00, GPIO_PXPES(3)); \
1014 #define __gpio_get_port(p) (readl(GPIO_PXPIN(p)))
1016 #define __gpio_disable_pull(n) \
1018 unsigned int p, o; \
1021 writel((1 << o), GPIO_PXPES(p)); \
1024 #define __gpio_enable_pull(n) \
1026 unsigned int p, o; \
1029 writel(1 << (o), GPIO_PXPEC(p)); \
1032 #define __gpio_port_as_output(p, o) \
1034 writel(1 << (o), GPIO_PXFUNC(p)); \
1035 writel(1 << (o), GPIO_PXSELC(p)); \
1036 writel(1 << (o), GPIO_PXDIRS(p)); \
1039 #define __gpio_port_as_input(p, o) \
1041 writel(1 << (o), GPIO_PXFUNC(p)); \
1042 writel(1 << (o), GPIO_PXSELC(p)); \
1043 writel(1 << (o), GPIO_PXDIRC(p)); \
1046 #define __gpio_as_output(n) \
1048 unsigned int p, o; \
1051 __gpio_port_as_output(p, o); \
1054 #define __gpio_as_input(n) \
1056 unsigned int p, o; \
1059 __gpio_port_as_input(p, o); \
1062 #define __gpio_set_pin(n) \
1064 unsigned int p, o; \
1067 writel((1 << o), GPIO_PXDATS(p)); \
1070 #define __gpio_clear_pin(n) \
1072 unsigned int p, o; \
1075 writel((1 << o), GPIO_PXDATC(p)); \
1078 #define __gpio_get_pin(n) \
1080 unsigned int p, o, v; \
1083 if (__gpio_get_port(p) & (1 << o)) \
1090 #define __gpio_as_uart0() \
1092 writel(0x06000000, GPIO_PXFUNS(3)); \
1093 writel(0x06000000, GPIO_PXSELS(3)); \
1094 writel(0x06000000, GPIO_PXPES(3)); \
1097 #define __gpio_jtag_to_uart0() \
1099 writel(0x80000000, GPIO_PXSELS(2)); \
1102 /* Clock Control Register */
1103 #define __cpm_get_pllm() \
1104 ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \
1105 >> CPM_CPPCR_PLLM_BIT)
1106 #define __cpm_get_plln() \
1107 ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \
1108 >> CPM_CPPCR_PLLN_BIT)
1109 #define __cpm_get_pllod() \
1110 ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \
1111 >> CPM_CPPCR_PLLOD_BIT)
1112 #define __cpm_get_hdiv() \
1113 ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \
1114 >> CPM_CPCCR_HDIV_BIT)
1115 #define __cpm_get_pdiv() \
1116 ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \
1117 >> CPM_CPCCR_PDIV_BIT)
1118 #define __cpm_get_cdiv() \
1119 ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \
1120 >> CPM_CPCCR_CDIV_BIT)
1121 #define __cpm_get_mdiv() \
1122 ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \
1123 >> CPM_CPCCR_MDIV_BIT)
1125 static inline unsigned int __cpm_get_pllout(void)
1127 uint32_t m, n, no, pllout;
1128 uint32_t od[4] = {1, 2, 2, 4};
1130 struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
1131 uint32_t cppcr = readl(&cpm->cppcr);
1133 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
1134 m = __cpm_get_pllm() + 2;
1135 n = __cpm_get_plln() + 2;
1136 no = od[__cpm_get_pllod()];
1137 pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
1139 pllout = CONFIG_SYS_EXTAL;
1144 extern void pll_init(void);
1145 extern void sdram_init(void);
1146 extern void calc_clocks(void);
1147 extern void rtc_init(void);
1149 #endif /* !__ASSEMBLY__ */
1150 #endif /* __JZ4740_H__ */
projects / platform / kernel / u-boot.git / blob