2 * Format of an instruction in memory.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
15 * Major opcodes; before MIPS IV cop1x was called cop3.
18 spec_op, bcond_op, j_op, jal_op,
19 beq_op, bne_op, blez_op, bgtz_op,
20 addi_op, addiu_op, slti_op, sltiu_op,
21 andi_op, ori_op, xori_op, lui_op,
22 cop0_op, cop1_op, cop2_op, cop1x_op,
23 beql_op, bnel_op, blezl_op, bgtzl_op,
24 daddi_op, daddiu_op, ldl_op, ldr_op,
25 spec2_op, jalx_op, mdmx_op, spec3_op,
26 lb_op, lh_op, lwl_op, lw_op,
27 lbu_op, lhu_op, lwr_op, lwu_op,
28 sb_op, sh_op, swl_op, sw_op,
29 sdl_op, sdr_op, swr_op, cache_op,
30 ll_op, lwc1_op, lwc2_op, pref_op,
31 lld_op, ldc1_op, ldc2_op, ld_op,
32 sc_op, swc1_op, swc2_op, major_3b_op,
33 scd_op, sdc1_op, sdc2_op, sd_op
37 * func field of spec opcode.
40 sll_op, movc_op, srl_op, sra_op,
41 sllv_op, pmon_op, srlv_op, srav_op,
42 jr_op, jalr_op, movz_op, movn_op,
43 syscall_op, break_op, spim_op, sync_op,
44 mfhi_op, mthi_op, mflo_op, mtlo_op,
45 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
46 mult_op, multu_op, div_op, divu_op,
47 dmult_op, dmultu_op, ddiv_op, ddivu_op,
48 add_op, addu_op, sub_op, subu_op,
49 and_op, or_op, xor_op, nor_op,
50 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
51 dadd_op, daddu_op, dsub_op, dsubu_op,
52 tge_op, tgeu_op, tlt_op, tltu_op,
53 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
54 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
55 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
59 * func field of spec2 opcode.
62 madd_op, maddu_op, mul_op, spec2_3_unused_op,
63 msub_op, msubu_op, /* more unused ops */
64 clz_op = 0x20, clo_op,
65 dclz_op = 0x24, dclo_op,
70 * func field of spec3 opcode.
73 ext_op, dextm_op, dextu_op, dext_op,
74 ins_op, dinsm_op, dinsu_op, dins_op,
82 * rt field of bcond opcodes.
85 bltz_op, bgez_op, bltzl_op, bgezl_op,
86 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
87 tgei_op, tgeiu_op, tlti_op, tltiu_op,
88 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
89 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
90 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
91 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
92 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
96 * rs field of cop opcodes.
99 mfc_op = 0x00, dmfc_op = 0x01,
100 cfc_op = 0x02, mtc_op = 0x04,
101 dmtc_op = 0x05, ctc_op = 0x06,
102 bc_op = 0x08, cop_op = 0x10,
107 * rt field of cop.bc_op opcodes
110 bcf_op, bct_op, bcfl_op, bctl_op
114 * func field of cop0 coi opcodes.
117 tlbr_op = 0x01, tlbwi_op = 0x02,
118 tlbwr_op = 0x06, tlbp_op = 0x08,
119 rfe_op = 0x10, eret_op = 0x18
123 * func field of cop0 com opcodes.
126 tlbr1_op = 0x01, tlbw_op = 0x02,
127 tlbp1_op = 0x08, dctr_op = 0x09,
132 * fmt field of cop1 opcodes.
135 s_fmt, d_fmt, e_fmt, q_fmt,
140 * func field of cop1 instructions using d, s or w format.
143 fadd_op = 0x00, fsub_op = 0x01,
144 fmul_op = 0x02, fdiv_op = 0x03,
145 fsqrt_op = 0x04, fabs_op = 0x05,
146 fmov_op = 0x06, fneg_op = 0x07,
147 froundl_op = 0x08, ftruncl_op = 0x09,
148 fceill_op = 0x0a, ffloorl_op = 0x0b,
149 fround_op = 0x0c, ftrunc_op = 0x0d,
150 fceil_op = 0x0e, ffloor_op = 0x0f,
151 fmovc_op = 0x11, fmovz_op = 0x12,
152 fmovn_op = 0x13, frecip_op = 0x15,
153 frsqrt_op = 0x16, fcvts_op = 0x20,
154 fcvtd_op = 0x21, fcvte_op = 0x22,
155 fcvtw_op = 0x24, fcvtl_op = 0x25,
160 * func field of cop1x opcodes (MIPS IV).
163 lwxc1_op = 0x00, ldxc1_op = 0x01,
164 pfetch_op = 0x07, swxc1_op = 0x08,
165 sdxc1_op = 0x09, madd_s_op = 0x20,
166 madd_d_op = 0x21, madd_e_op = 0x22,
167 msub_s_op = 0x28, msub_d_op = 0x29,
168 msub_e_op = 0x2a, nmadd_s_op = 0x30,
169 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
170 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
175 * func field for mad opcodes (MIPS IV).
178 madd_fp_op = 0x08, msub_fp_op = 0x0a,
179 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
183 * func field for special3 lx opcodes (Cavium Octeon).
196 * Damn ... bitfields depend from byteorder :-(
199 struct j_format { /* Jump format */
200 unsigned int opcode : 6;
201 unsigned int target : 26;
204 struct i_format { /* Immediate format (addi, lw, ...) */
205 unsigned int opcode : 6;
208 signed int simmediate : 16;
211 struct u_format { /* Unsigned immediate format (ori, xori, ...) */
212 unsigned int opcode : 6;
215 unsigned int uimmediate : 16;
218 struct c_format { /* Cache (>= R6000) format */
219 unsigned int opcode : 6;
221 unsigned int c_op : 3;
222 unsigned int cache : 2;
223 unsigned int simmediate : 16;
226 struct r_format { /* Register format */
227 unsigned int opcode : 6;
232 unsigned int func : 6;
235 struct p_format { /* Performance counter format (R10000) */
236 unsigned int opcode : 6;
241 unsigned int func : 6;
244 struct f_format { /* FPU register format */
245 unsigned int opcode : 6;
247 unsigned int fmt : 4;
251 unsigned int func : 6;
254 struct ma_format { /* FPU multiply and add format (MIPS IV) */
255 unsigned int opcode : 6;
260 unsigned int func : 4;
261 unsigned int fmt : 2;
264 struct b_format { /* BREAK and SYSCALL */
265 unsigned int opcode:6;
266 unsigned int code:20;
270 #elif defined(__MIPSEL__)
272 struct j_format { /* Jump format */
273 unsigned int target : 26;
274 unsigned int opcode : 6;
277 struct i_format { /* Immediate format */
278 signed int simmediate : 16;
281 unsigned int opcode : 6;
284 struct u_format { /* Unsigned immediate format */
285 unsigned int uimmediate : 16;
288 unsigned int opcode : 6;
291 struct c_format { /* Cache (>= R6000) format */
292 unsigned int simmediate : 16;
293 unsigned int cache : 2;
294 unsigned int c_op : 3;
296 unsigned int opcode : 6;
299 struct r_format { /* Register format */
300 unsigned int func : 6;
305 unsigned int opcode : 6;
308 struct p_format { /* Performance counter format (R10000) */
309 unsigned int func : 6;
314 unsigned int opcode : 6;
317 struct f_format { /* FPU register format */
318 unsigned int func : 6;
322 unsigned int fmt : 4;
324 unsigned int opcode : 6;
327 struct ma_format { /* FPU multiply and add format (MIPS IV) */
328 unsigned int fmt : 2;
329 unsigned int func : 4;
334 unsigned int opcode : 6;
337 struct b_format { /* BREAK and SYSCALL */
339 unsigned int code:20;
340 unsigned int opcode:6;
343 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
344 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
347 union mips_instruction {
349 unsigned short halfword[2];
350 unsigned char byte[4];
351 struct j_format j_format;
352 struct i_format i_format;
353 struct u_format u_format;
354 struct c_format c_format;
355 struct r_format r_format;
356 struct f_format f_format;
357 struct ma_format ma_format;
358 struct b_format b_format;
361 /* HACHACHAHCAHC ... */
363 /* In case some other massaging is needed, keep MIPSInst as wrapper */
365 #define MIPSInst(x) x
367 #define I_OPCODE_SFT 26
368 #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
370 #define I_JTARGET_SFT 0
371 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
374 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
377 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
380 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
381 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
383 #define I_CACHEOP_SFT 18
384 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
386 #define I_CACHESEL_SFT 16
387 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
390 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
393 #define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
396 #define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
398 #define I_FFMT_SFT 21
399 #define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
402 #define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
405 #define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
408 #define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
411 #define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
413 #define I_FMA_FUNC_SFT 2
414 #define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
416 #define I_FMA_FFMT_SFT 0
417 #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
419 typedef unsigned int mips_instruction;
421 #endif /* _ASM_INST_H */