1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
7 #include "mscc,ocelot_pcb.dtsi"
8 #include <dt-bindings/mscc/ocelot_data.h>
11 model = "Ocelot PCB120 Reference Board";
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
19 compatible = "gpio-leds";
22 label = "pcb120:green:poe";
23 gpios = <&sgpio 44 1>; /* p12.1 */
24 default-state = "off";
28 label = "pcb120:red:poe";
29 gpios = <&sgpio 12 1>; /* p12.0 */
30 default-state = "off";
34 label = "pcb120:green:alarm";
35 gpios = <&sgpio 45 1>; /* p13.1 */
36 default-state = "off";
40 label = "pcb120:red:alarm";
41 gpios = <&sgpio 13 1>; /* p13.0 */
42 default-state = "off";
46 label = "pcb120:green:dc_a";
47 gpios = <&sgpio 46 1>; /* p14.1 */
48 default-state = "off";
52 label = "pcb120:red:dc_a";
53 gpios = <&sgpio 14 1>; /* p14.0 */
54 default-state = "off";
58 label = "pcb120:green:dc_b";
59 gpios = <&sgpio 47 1>; /* p15.1 */
60 default-state = "off";
64 label = "pcb120:red:dc_b";
65 gpios = <&sgpio 15 1>; /* p15.0 */
66 default-state = "off";
70 label = "pcb120:green:status";
71 gpios = <&sgpio 48 1>; /* p16.1 */
76 label = "pcb120:red:alarm";
77 gpios = <&sgpio 16 1>; /* p16.0 */
78 default-state = "off";
87 mscc,sgpio-ports = <0x000FFFFF>;
93 phy4: ethernet-phy@4 {
96 phy5: ethernet-phy@5 {
99 phy6: ethernet-phy@6 {
102 phy7: ethernet-phy@7 {
110 phy0: ethernet-phy@0 {
113 phy1: ethernet-phy@1 {
116 phy2: ethernet-phy@2 {
119 phy3: ethernet-phy@3 {
128 phy-handle = <&phy0>;
129 phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
133 phy-handle = <&phy1>;
134 phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
138 phy-handle = <&phy2>;
139 phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
143 phy-handle = <&phy3>;
144 phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
148 phy-handle = <&phy4>;
152 phy-handle = <&phy5>;
156 phy-handle = <&phy6>;
160 phy-handle = <&phy7>;