arch/mips/dts/mt7628a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/mt7628-clk.h>
   3 #include <dt-bindings/reset/mt7628-reset.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "ralink,mt7628a-soc";
   9
  10         cpus {
  11                 #address-cells = <1>;
  12                 #size-cells = <0>;
  13
  14                 cpu@0 {
  15                         compatible = "mti,mips24KEc";
  16                         device_type = "cpu";
  17                         reg = <0>;
  18                 };
  19         };
  20
  21         cpuintc: interrupt-controller {
  22                 #address-cells = <0>;
  23                 #interrupt-cells = <1>;
  24                 interrupt-controller;
  25                 compatible = "mti,cpu-interrupt-controller";
  26         };
  27
  28         palmbus@10000000 {
  29                 compatible = "palmbus", "simple-bus";
  30                 reg = <0x10000000 0x200000>;
  31                 ranges = <0x0 0x10000000 0x1FFFFF>;
  32
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35
  36                 sysc: system-controller@0 {
  37                         compatible = "ralink,mt7620a-sysc", "syscon";
  38                         reg = <0x0 0x100>;
  39                 };
  40
  41                 syscon-reboot {
  42                         compatible = "syscon-reboot";
  43                         regmap = <&sysc>;
  44                         offset = <0x34>;
  45                         mask = <0x1>;
  46                 };
  47
  48                 clkctrl: clkctrl@0x2c {
  49                         reg = <0x2c 0x8>, <0x10 0x4>;
  50                         reg-names = "syscfg0", "clkcfg";
  51                         compatible = "mediatek,mt7628-clk";
  52                         #clock-cells = <1>;
  53                         u-boot,dm-pre-reloc;
  54                 };
  55
  56                 rstctrl: rstctrl@0x34 {
  57                         reg = <0x34 0x4>;
  58                         compatible = "mediatek,mtmips-reset";
  59                         #reset-cells = <1>;
  60                 };
  61
  62                 pinctrl: pinctrl@60 {
  63                         compatible = "mediatek,mt7628-pinctrl";
  64                         reg = <0x3c 0x2c>, <0x1300 0x100>;
  65                         reg-names = "gpiomode", "padconf";
  66
  67                         pinctrl-names = "default";
  68                         pinctrl-0 = <&state_default>;
  69
  70                         state_default: pin_state {
  71                         };
  72
  73                         spi_single_pins: spi_single_pins {
  74                                 groups = "spi";
  75                                 function = "spi";
  76                         };
  77
  78                         spi_dual_pins: spi_dual_pins {
  79                                 spi_master_pins {
  80                                         groups = "spi";
  81                                         function = "spi";
  82                                 };
  83
  84                                 spi_cs1_pin {
  85                                         groups = "spi cs1";
  86                                         function = "spi cs1";
  87                                 };
  88                         };
  89
  90                         uart0_pins: uart0_pins {
  91                                 groups = "uart0";
  92                                 function = "uart0";
  93                         };
  94
  95                         uart1_pins: uart1_pins {
  96                                 groups = "uart1";
  97                                 function = "uart1";
  98                         };
  99
 100                         uart2_pins: uart2_pins {
 101                                 groups = "uart2";
 102                                 function = "uart2";
 103                         };
 104
 105                         i2c_pins: i2c_pins {
 106                                 groups = "i2c";
 107                                 function = "i2c";
 108                         };
 109
 110                         ephy_iot_mode: ephy_iot_mode {
 111                                 ephy4_1_dis {
 112                                         groups = "ephy4_1_pad";
 113                                         function = "digital";
 114                                 };
 115
 116                                 ephy0_en {
 117                                         groups = "ephy0";
 118                                         function = "enable";
 119                                 };
 120                         };
 121
 122                         ephy_router_mode: ephy_router_mode {
 123                                 ephy4_1_en {
 124                                         groups = "ephy4_1_pad";
 125                                         function = "analog";
 126                                 };
 127
 128                                 ephy0_en {
 129                                         groups = "ephy0";
 130                                         function = "enable";
 131                                 };
 132                         };
 133
 134                         sd_iot_mode: sd_iot_mode {
 135                                 ephy4_1_dis {
 136                                         groups = "ephy4_1_pad";
 137                                         function = "digital";
 138                                 };
 139
 140                                 sdxc_en {
 141                                         groups = "sdmode";
 142                                         function = "sdxc";
 143                                 };
 144
 145                                 sdxc_iot_mode {
 146                                         groups = "sd router";
 147                                         function = "iot";
 148                                 };
 149
 150                                 sd_clk_pad {
 151                                         pins = "sd_clk";
 152                                         drive-strength-4g = <8>;
 153                                 };
 154                         };
 155
 156                         sd_router_mode: sd_router_mode {
 157                                 sdxc_router_mode {
 158                                         groups = "sd router";
 159                                         function = "router";
 160                                 };
 161
 162                                 sdxc_map_pins {
 163                                         groups = "gpio0", "i2s", "sdmode", \
 164                                                  "i2c", "uart1";
 165                                         function = "gpio";
 166                                 };
 167
 168                                 sd_clk_pad {
 169                                         pins = "gpio0";
 170                                         drive-strength-28 = <8>;
 171                                 };
 172                         };
 173
 174                         emmc_iot_8bit_mode: emmc_iot_8bit_mode {
 175                                 ephy4_1_dis {
 176                                         groups = "ephy4_1_pad";
 177                                         function = "digital";
 178                                 };
 179
 180                                 emmc_en {
 181                                         groups = "sdmode";
 182                                         function = "sdxc";
 183                                 };
 184
 185                                 emmc_iot_mode {
 186                                         groups = "sd router";
 187                                         function = "iot";
 188                                 };
 189
 190                                 emmc_d4_d5 {
 191                                         groups = "uart2";
 192                                         function = "sdxc d5 d4";
 193                                 };
 194
 195                                 emmc_d6 {
 196                                         groups = "pwm1";
 197                                         function = "sdxc d6";
 198                                 };
 199
 200                                 emmc_d7 {
 201                                         groups = "pwm0";
 202                                         function = "sdxc d7";
 203                                 };
 204
 205                                 sd_clk_pad {
 206                                         pins = "sd_clk";
 207                                         drive-strength-4g = <8>;
 208                                 };
 209                         };
 210                 };
 211
 212                 watchdog: watchdog@100 {
 213                         compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
 214                         reg = <0x100 0x30>;
 215
 216                         resets = <&rstctrl MT7628_TIMER_RST>;
 217                         reset-names = "wdt";
 218
 219                         interrupt-parent = <&intc>;
 220                         interrupts = <24>;
 221                 };
 222
 223                 intc: interrupt-controller@200 {
 224                         compatible = "ralink,rt2880-intc";
 225                         reg = <0x200 0x100>;
 226
 227                         interrupt-controller;
 228                         #interrupt-cells = <1>;
 229
 230                         resets = <&rstctrl MT7628_INT_RST>;
 231                         reset-names = "intc";
 232
 233                         interrupt-parent = <&cpuintc>;
 234                         interrupts = <2>;
 235
 236                         ralink,intc-registers = <0x9c 0xa0
 237                                                  0x6c 0xa4
 238                                                  0x80 0x78>;
 239                 };
 240
 241                 memory-controller@300 {
 242                         compatible = "ralink,mt7620a-memc";
 243                         reg = <0x300 0x100>;
 244                 };
 245
 246                 gpio@600 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249
 250                         compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
 251                         reg = <0x600 0x100>;
 252
 253                         resets = <&rstctrl MT7628_PIO_RST>;
 254                         reset-names = "pio";
 255
 256                         interrupt-parent = <&intc>;
 257                         interrupts = <6>;
 258
 259                         gpio0: bank@0 {
 260                                 reg = <0>;
 261                                 compatible = "mtk,mt7621-gpio-bank";
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                         };
 265
 266                         gpio1: bank@1 {
 267                                 reg = <1>;
 268                                 compatible = "mtk,mt7621-gpio-bank";
 269                                 gpio-controller;
 270                                 #gpio-cells = <2>;
 271                         };
 272
 273                         gpio2: bank@2 {
 274                                 reg = <2>;
 275                                 compatible = "mtk,mt7621-gpio-bank";
 276                                 gpio-controller;
 277                                 #gpio-cells = <2>;
 278                         };
 279                 };
 280
 281                 spi0: spi@b00 {
 282                         compatible = "ralink,mt7621-spi";
 283                         reg = <0xb00 0x40>;
 284
 285                         resets = <&rstctrl MT7628_SPI_RST>;
 286                         reset-names = "spi";
 287
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290
 291                         clocks = <&clkctrl CLK_SPI>;
 292                 };
 293
 294                 uart0: uartlite@c00 {
 295                         compatible = "mediatek,hsuart", "ns16550a";
 296                         reg = <0xc00 0x100>;
 297
 298                         pinctrl-names = "default";
 299                         pinctrl-0 = <&uart0_pins>;
 300
 301                         clocks = <&clkctrl CLK_UART0>;
 302
 303                         resets = <&rstctrl MT7628_UART0_RST>;
 304                         reset-names = "uart0";
 305
 306                         interrupt-parent = <&intc>;
 307                         interrupts = <20>;
 308
 309                         reg-shift = <2>;
 310                 };
 311
 312                 uart1: uart1@d00 {
 313                         compatible = "mediatek,hsuart", "ns16550a";
 314                         reg = <0xd00 0x100>;
 315
 316                         pinctrl-names = "default";
 317                         pinctrl-0 = <&uart1_pins>;
 318
 319                         clocks = <&clkctrl CLK_UART1>;
 320
 321                         resets = <&rstctrl MT7628_UART1_RST>;
 322                         reset-names = "uart1";
 323
 324                         interrupt-parent = <&intc>;
 325                         interrupts = <21>;
 326
 327                         reg-shift = <2>;
 328                 };
 329
 330                 uart2: uart2@e00 {
 331                         compatible = "mediatek,hsuart", "ns16550a";
 332                         reg = <0xe00 0x100>;
 333
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&uart2_pins>;
 336
 337                         clocks = <&clkctrl CLK_UART2>;
 338
 339                         resets = <&rstctrl MT7628_UART2_RST>;
 340                         reset-names = "uart2";
 341
 342                         interrupt-parent = <&intc>;
 343                         interrupts = <22>;
 344
 345                         reg-shift = <2>;
 346                 };
 347         };
 348
 349         eth: eth@10110000 {
 350                 compatible = "mediatek,mt7628-eth";
 351                 reg = <0x10100000 0x10000
 352                        0x10110000 0x8000>;
 353
 354                 resets = <&rstctrl MT7628_EPHY_RST>;
 355                 reset-names = "ephy";
 356
 357                 syscon = <&sysc>;
 358         };
 359
 360         usb_phy: usb-phy@10120000 {
 361                 compatible = "mediatek,mt7628-usbphy";
 362                 reg = <0x10120000 0x1000>;
 363
 364                 #phy-cells = <0>;
 365
 366                 ralink,sysctl = <&sysc>;
 367
 368                 resets = <&rstctrl MT7628_UPHY_RST>;
 369                 reset-names = "phy";
 370
 371                 clocks = <&clkctrl CLK_UPHY>;
 372                 clock-names = "cg";
 373         };
 374
 375         ehci@101c0000 {
 376                 compatible = "generic-ehci";
 377                 reg = <0x101c0000 0x1000>;
 378
 379                 phys = <&usb_phy>;
 380                 phy-names = "usb";
 381
 382                 interrupt-parent = <&intc>;
 383                 interrupts = <18>;
 384         };
 385 };