arch/mips/dts/mt7628a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/mt7628-clk.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "ralink,mt7628a-soc";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         compatible = "mti,mips24KEc";
  15                         device_type = "cpu";
  16                         reg = <0>;
  17                 };
  18         };
  19
  20         resetc: reset-controller {
  21                 compatible = "ralink,rt2880-reset";
  22                 #reset-cells = <1>;
  23         };
  24
  25         cpuintc: interrupt-controller {
  26                 #address-cells = <0>;
  27                 #interrupt-cells = <1>;
  28                 interrupt-controller;
  29                 compatible = "mti,cpu-interrupt-controller";
  30         };
  31
  32         palmbus@10000000 {
  33                 compatible = "palmbus", "simple-bus";
  34                 reg = <0x10000000 0x200000>;
  35                 ranges = <0x0 0x10000000 0x1FFFFF>;
  36
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39
  40                 sysc: system-controller@0 {
  41                         compatible = "ralink,mt7620a-sysc", "syscon";
  42                         reg = <0x0 0x100>;
  43                 };
  44
  45                 syscon-reboot {
  46                         compatible = "syscon-reboot";
  47                         regmap = <&sysc>;
  48                         offset = <0x34>;
  49                         mask = <0x1>;
  50                 };
  51
  52                 clkctrl: clkctrl@0x2c {
  53                         reg = <0x2c 0x8>, <0x10 0x4>;
  54                         reg-names = "syscfg0", "clkcfg";
  55                         compatible = "mediatek,mt7628-clk";
  56                         #clock-cells = <1>;
  57                         u-boot,dm-pre-reloc;
  58                 };
  59
  60                 watchdog: watchdog@100 {
  61                         compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
  62                         reg = <0x100 0x30>;
  63
  64                         resets = <&resetc 8>;
  65                         reset-names = "wdt";
  66
  67                         interrupt-parent = <&intc>;
  68                         interrupts = <24>;
  69                 };
  70
  71                 intc: interrupt-controller@200 {
  72                         compatible = "ralink,rt2880-intc";
  73                         reg = <0x200 0x100>;
  74
  75                         interrupt-controller;
  76                         #interrupt-cells = <1>;
  77
  78                         resets = <&resetc 9>;
  79                         reset-names = "intc";
  80
  81                         interrupt-parent = <&cpuintc>;
  82                         interrupts = <2>;
  83
  84                         ralink,intc-registers = <0x9c 0xa0
  85                                                  0x6c 0xa4
  86                                                  0x80 0x78>;
  87                 };
  88
  89                 memory-controller@300 {
  90                         compatible = "ralink,mt7620a-memc";
  91                         reg = <0x300 0x100>;
  92                 };
  93
  94                 gpio@600 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97
  98                         compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  99                         reg = <0x600 0x100>;
 100
 101                         interrupt-parent = <&intc>;
 102                         interrupts = <6>;
 103
 104                         gpio0: bank@0 {
 105                                 reg = <0>;
 106                                 compatible = "mtk,mt7621-gpio-bank";
 107                                 gpio-controller;
 108                                 #gpio-cells = <2>;
 109                         };
 110
 111                         gpio1: bank@1 {
 112                                 reg = <1>;
 113                                 compatible = "mtk,mt7621-gpio-bank";
 114                                 gpio-controller;
 115                                 #gpio-cells = <2>;
 116                         };
 117
 118                         gpio2: bank@2 {
 119                                 reg = <2>;
 120                                 compatible = "mtk,mt7621-gpio-bank";
 121                                 gpio-controller;
 122                                 #gpio-cells = <2>;
 123                         };
 124                 };
 125
 126                 spi0: spi@b00 {
 127                         compatible = "ralink,mt7621-spi";
 128                         reg = <0xb00 0x40>;
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131
 132                         clocks = <&clkctrl CLK_SPI>;
 133                 };
 134
 135                 uart0: uartlite@c00 {
 136                         compatible = "mediatek,hsuart", "ns16550a";
 137                         reg = <0xc00 0x100>;
 138
 139                         clocks = <&clkctrl CLK_UART0>;
 140
 141                         resets = <&resetc 12>;
 142                         reset-names = "uart0";
 143
 144                         interrupt-parent = <&intc>;
 145                         interrupts = <20>;
 146
 147                         reg-shift = <2>;
 148                 };
 149
 150                 uart1: uart1@d00 {
 151                         compatible = "mediatek,hsuart", "ns16550a";
 152                         reg = <0xd00 0x100>;
 153
 154                         clocks = <&clkctrl CLK_UART1>;
 155
 156                         resets = <&resetc 19>;
 157                         reset-names = "uart1";
 158
 159                         interrupt-parent = <&intc>;
 160                         interrupts = <21>;
 161
 162                         reg-shift = <2>;
 163                 };
 164
 165                 uart2: uart2@e00 {
 166                         compatible = "mediatek,hsuart", "ns16550a";
 167                         reg = <0xe00 0x100>;
 168
 169                         clocks = <&clkctrl CLK_UART2>;
 170
 171                         resets = <&resetc 20>;
 172                         reset-names = "uart2";
 173
 174                         interrupt-parent = <&intc>;
 175                         interrupts = <22>;
 176
 177                         reg-shift = <2>;
 178                 };
 179         };
 180
 181         eth@10110000 {
 182                 compatible = "mediatek,mt7628-eth";
 183                 reg = <0x10100000 0x10000
 184                        0x10110000 0x8000>;
 185
 186                 syscon = <&sysc>;
 187         };
 188
 189         usb_phy: usb-phy@10120000 {
 190                 compatible = "mediatek,mt7628-usbphy";
 191                 reg = <0x10120000 0x1000>;
 192
 193                 #phy-cells = <0>;
 194
 195                 ralink,sysctl = <&sysc>;
 196
 197                 resets = <&resetc 22 &resetc 25>;
 198                 reset-names = "host", "device";
 199
 200                 clocks = <&clkctrl CLK_UPHY>;
 201                 clock-names = "cg";
 202         };
 203
 204         ehci@101c0000 {
 205                 compatible = "generic-ehci";
 206                 reg = <0x101c0000 0x1000>;
 207
 208                 phys = <&usb_phy>;
 209                 phy-names = "usb";
 210
 211                 interrupt-parent = <&intc>;
 212                 interrupts = <18>;
 213         };
 214 };