arch/mips/dts/mrvl,octeon-ebb7304.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell / Cavium Inc. EVB CN7300
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "mrvl,cn73xx.dtsi"
   9
  10 / {
  11         model = "cavium,ebb7304";
  12         compatible = "cavium,ebb7304";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 spi0 = &spi;
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart0;
  21         };
  22 };
  23
  24 &bootbus {
  25         /*
  26          * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
  27          * as the initial size is too small for the 8MiB flash device
  28          */
  29         ranges = <0 0  0       0x1f400000  0xc00000>,
  30                  <1 0  0x10000 0x10000000  0>,
  31                  <2 0  0x10000 0x20000000  0>,
  32                  <3 0  0x10000 0x30000000  0>,
  33                  <4 0  0       0x1d020000  0x10000>,
  34                  <5 0  0x10000 0x50000000  0>,
  35                  <6 0  0x10000 0x60000000  0>,
  36                  <7 0  0x10000 0x70000000  0>;
  37
  38         cavium,cs-config@0 {
  39                 compatible = "cavium,octeon-3860-bootbus-config";
  40                 cavium,cs-index = <0>;
  41                 cavium,t-adr  = <10>;
  42                 cavium,t-ce   = <50>;
  43                 cavium,t-oe   = <50>;
  44                 cavium,t-we   = <35>;
  45                 cavium,t-rd-hld = <25>;
  46                 cavium,t-wr-hld = <35>;
  47                 cavium,t-pause  = <0>;
  48                 cavium,t-wait   = <50>;
  49                 cavium,t-page   = <30>;
  50                 cavium,t-rd-dly = <0>;
  51                 cavium,page-mode = <1>;
  52                 cavium,pages     = <8>;
  53                 cavium,bus-width = <8>;
  54         };
  55
  56         cavium,cs-config@4 {
  57                 compatible = "cavium,octeon-3860-bootbus-config";
  58                 cavium,cs-index = <4>;
  59                 cavium,t-adr  = <10>;
  60                 cavium,t-ce   = <10>;
  61                 cavium,t-oe   = <160>;
  62                 cavium,t-we   = <100>;
  63                 cavium,t-rd-hld = <10>;
  64                 cavium,t-wr-hld = <0>;
  65                 cavium,t-pause  = <50>;
  66                 cavium,t-wait   = <50>;
  67                 cavium,t-page   = <10>;
  68                 cavium,t-rd-dly = <10>;
  69                 cavium,pages     = <0>;
  70                 cavium,bus-width = <8>;
  71         };
  72
  73         flash0: nor@0,0 {
  74                 compatible = "cfi-flash";
  75                 reg = <0 0 0x800000>;
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 partition@0 {
  79                         label = "bootloader";
  80                         reg = <0 0x340000>;
  81                         read-only;
  82                 };
  83                 partition@300000 {
  84                         label = "storage";
  85                         reg = <0x340000 0x4be000>;
  86                 };
  87                 partition@7fe000 {
  88                         label = "environment";
  89                         reg = <0x7fe000 0x2000>;
  90                         read-only;
  91                 };
  92         };
  93 };
  94
  95 &uart0 {
  96         clock-frequency = <1200000000>;
  97 };
  98
  99 &i2c0 {
 100         u-boot,dm-pre-reloc;    /* Needed early for DDR SPD EEPROM */
 101         clock-frequency = <100000>;
 102 };
 103
 104 &i2c1 {
 105         u-boot,dm-pre-reloc;    /* Needed early for DDR SPD EEPROM */
 106         clock-frequency = <100000>;
 107 };
 108
 109 &spi {
 110         flash@0 {
 111                 compatible = "micron,n25q128a11", "jedec,spi-nor";
 112                 spi-max-frequency = <2000000>;
 113                 reg = <0>;
 114         };
 115 };