arch/mips/dts/mrvl,cn73xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell / Cavium Inc. CN73xx
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/octeon-clock.h>
   9
  10 / {
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         soc0: soc@0 {
  15                 interrupt-parent = <&ciu3>;
  16                 compatible = "simple-bus";
  17                 #address-cells = <2>;
  18                 #size-cells = <2>;
  19                 ranges; /* Direct mapping */
  20
  21                 ciu3: interrupt-controller@1010000000000 {
  22                         compatible = "cavium,octeon-7890-ciu3";
  23                         interrupt-controller;
  24                         /*
  25                          * Interrupts are specified by two parts:
  26                          * 1) Source number (20 significant bits)
  27                          * 2) Trigger type: (4 == level, 1 == edge)
  28                          */
  29                         #address-cells = <0>;
  30                         #interrupt-cells = <2>;
  31                         reg = <0x10100 0x00000000 0x0 0xb0000000>;
  32                 };
  33
  34                 bootbus: bootbus@1180000000000 {
  35                         compatible = "cavium,octeon-3860-bootbus","simple-bus";
  36                         reg = <0x11800 0x00000000 0x0 0x200>;
  37                         /* The chip select number and offset */
  38                         #address-cells = <2>;
  39                         /* The size of the chip select region */
  40                         #size-cells = <1>;
  41                 };
  42
  43                 clk: clock {
  44                         compatible = "mrvl,octeon-clk";
  45                         #clock-cells = <1>;
  46                         u-boot,dm-pre-reloc;
  47                 };
  48
  49                 gpio: gpio-controller@1070000000800 {
  50                         #gpio-cells = <2>;
  51                         compatible = "cavium,octeon-7890-gpio";
  52                         reg = <0x10700 0x00000800 0x0 0x100>;
  53                         gpio-controller;
  54                         nr-gpios = <32>;
  55                         /* Interrupts are specified by two parts:
  56                          * 1) GPIO pin number (0..15)
  57                          * 2) Triggering (1 - edge rising
  58                          *                2 - edge falling
  59                          *                4 - level active high
  60                          *                8 - level active low)
  61                          */
  62                         interrupt-controller;
  63                         #interrupt-cells = <2>;
  64                         /* The GPIO pins connect to 16 consecutive CUI bits */
  65                         interrupts = <0x03000 4>, <0x03001 4>,
  66                                      <0x03002 4>, <0x03003 4>,
  67                                      <0x03004 4>, <0x03005 4>,
  68                                      <0x03006 4>, <0x03007 4>,
  69                                      <0x03008 4>, <0x03009 4>,
  70                                      <0x0300a 4>, <0x0300b 4>,
  71                                      <0x0300c 4>, <0x0300d 4>,
  72                                      <0x0300e 4>, <0x0300f 4>;
  73                 };
  74
  75                 reset: reset@1180006001600 {
  76                         compatible = "mrvl,cn7xxx-rst";
  77                         reg = <0x11800 0x06001600 0x0 0x200>;
  78                 };
  79
  80                 uart0: serial@1180000000800 {
  81                         compatible = "cavium,octeon-3860-uart","ns16550";
  82                         reg = <0x11800 0x00000800 0x0 0x400>;
  83                         clock-frequency = <0>;
  84                         current-speed = <115200>;
  85                         reg-shift = <3>;
  86                         interrupts = <0x08000 4>;
  87                 };
  88
  89                 uart1: serial@1180000000c00 {
  90                         compatible = "cavium,octeon-3860-uart","ns16550";
  91                         reg = <0x11800 0x00000c00 0x0 0x400>;
  92                         clock-frequency = <0>;
  93                         current-speed = <115200>;
  94                         reg-shift = <3>;
  95                         interrupts = <0x08040 4>;
  96                 };
  97
  98                 i2c0: i2c@1180000001000 {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101                         compatible = "cavium,octeon-7890-twsi";
 102                         reg = <0x11800 0x00001000 0x0 0x200>;
 103                         /* INT_ST, INT_TS, INT_CORE */
 104                         interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
 105                         clock-frequency = <100000>;
 106                         clocks = <&clk OCTEON_CLK_IO>;
 107                 };
 108
 109                 i2c1: i2c@1180000001200 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         compatible = "cavium,octeon-7890-twsi";
 113                         reg = <0x11800 0x00001200 0x0 0x200>;
 114                         /* INT_ST, INT_TS, INT_CORE */
 115                         interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
 116                         clock-frequency = <100000>;
 117                         clocks = <&clk OCTEON_CLK_IO>;
 118                 };
 119
 120                 spi: spi@1070000001000 {
 121                         compatible = "cavium,octeon-3010-spi";
 122                         reg = <0x10700 0x00001000 0x0 0x100>;
 123                         interrupts = <0x05001 1>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         spi-max-frequency = <25000000>;
 127                         clocks = <&clk OCTEON_CLK_IO>;
 128                 };
 129         };
 130 };