arch/mips/dts/mrvl,cn73xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell / Cavium Inc. CN73xx
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/clock/octeon-clock.h>
   9
  10 / {
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         soc0: soc@0 {
  15                 interrupt-parent = <&ciu3>;
  16                 compatible = "simple-bus";
  17                 #address-cells = <2>;
  18                 #size-cells = <2>;
  19                 ranges; /* Direct mapping */
  20
  21                 ciu3: interrupt-controller@1010000000000 {
  22                         compatible = "cavium,octeon-7890-ciu3";
  23                         interrupt-controller;
  24                         /*
  25                          * Interrupts are specified by two parts:
  26                          * 1) Source number (20 significant bits)
  27                          * 2) Trigger type: (4 == level, 1 == edge)
  28                          */
  29                         #address-cells = <0>;
  30                         #interrupt-cells = <2>;
  31                         reg = <0x10100 0x00000000 0x0 0xb0000000>;
  32                 };
  33
  34                 bootbus: bootbus@1180000000000 {
  35                         compatible = "cavium,octeon-3860-bootbus","simple-bus";
  36                         reg = <0x11800 0x00000000 0x0 0x200>;
  37                         /* The chip select number and offset */
  38                         #address-cells = <2>;
  39                         /* The size of the chip select region */
  40                         #size-cells = <1>;
  41                 };
  42
  43                 clk: clock {
  44                         compatible = "mrvl,octeon-clk";
  45                         #clock-cells = <1>;
  46                         u-boot,dm-pre-reloc;
  47                 };
  48
  49                 gpio: gpio-controller@1070000000800 {
  50                         #gpio-cells = <2>;
  51                         compatible = "cavium,octeon-7890-gpio";
  52                         reg = <0x10700 0x00000800 0x0 0x100>;
  53                         gpio-controller;
  54                         nr-gpios = <32>;
  55                         /* Interrupts are specified by two parts:
  56                          * 1) GPIO pin number (0..15)
  57                          * 2) Triggering (1 - edge rising
  58                          *                2 - edge falling
  59                          *                4 - level active high
  60                          *                8 - level active low)
  61                          */
  62                         interrupt-controller;
  63                         #interrupt-cells = <2>;
  64                         /* The GPIO pins connect to 16 consecutive CUI bits */
  65                         interrupts = <0x03000 4>, <0x03001 4>,
  66                                      <0x03002 4>, <0x03003 4>,
  67                                      <0x03004 4>, <0x03005 4>,
  68                                      <0x03006 4>, <0x03007 4>,
  69                                      <0x03008 4>, <0x03009 4>,
  70                                      <0x0300a 4>, <0x0300b 4>,
  71                                      <0x0300c 4>, <0x0300d 4>,
  72                                      <0x0300e 4>, <0x0300f 4>;
  73                 };
  74
  75                 l2c: l2c@1180080000000 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         compatible = "cavium,octeon-7xxx-l2c";
  79                         reg = <0x11800 0x80000000 0x0 0x01000000>;
  80                         u-boot,dm-pre-reloc;
  81                 };
  82
  83                 lmc: lmc@1180088000000 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         compatible = "cavium,octeon-7xxx-ddr4";
  87                         reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
  88                         u-boot,dm-pre-reloc;
  89                         l2c-handle = <&l2c>;
  90                 };
  91
  92                 reset: reset@1180006001600 {
  93                         compatible = "mrvl,cn7xxx-rst";
  94                         reg = <0x11800 0x06001600 0x0 0x200>;
  95                 };
  96
  97                 uart0: serial@1180000000800 {
  98                         compatible = "cavium,octeon-3860-uart","ns16550";
  99                         reg = <0x11800 0x00000800 0x0 0x400>;
 100                         clock-frequency = <0>;
 101                         current-speed = <115200>;
 102                         reg-shift = <3>;
 103                         interrupts = <0x08000 4>;
 104                 };
 105
 106                 uart1: serial@1180000000c00 {
 107                         compatible = "cavium,octeon-3860-uart","ns16550";
 108                         reg = <0x11800 0x00000c00 0x0 0x400>;
 109                         clock-frequency = <0>;
 110                         current-speed = <115200>;
 111                         reg-shift = <3>;
 112                         interrupts = <0x08040 4>;
 113                 };
 114
 115                 i2c0: i2c@1180000001000 {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         compatible = "cavium,octeon-7890-twsi";
 119                         reg = <0x11800 0x00001000 0x0 0x200>;
 120                         /* INT_ST, INT_TS, INT_CORE */
 121                         interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
 122                         clock-frequency = <100000>;
 123                         clocks = <&clk OCTEON_CLK_IO>;
 124                 };
 125
 126                 i2c1: i2c@1180000001200 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         compatible = "cavium,octeon-7890-twsi";
 130                         reg = <0x11800 0x00001200 0x0 0x200>;
 131                         /* INT_ST, INT_TS, INT_CORE */
 132                         interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
 133                         clock-frequency = <100000>;
 134                         clocks = <&clk OCTEON_CLK_IO>;
 135                 };
 136
 137                 spi: spi@1070000001000 {
 138                         compatible = "cavium,octeon-3010-spi";
 139                         reg = <0x10700 0x00001000 0x0 0x100>;
 140                         interrupts = <0x05001 1>;
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         spi-max-frequency = <25000000>;
 144                         clocks = <&clk OCTEON_CLK_IO>;
 145                 };
 146
 147                 /* USB 0 */
 148                 usb0: uctl@1180068000000 {
 149                         compatible = "cavium,octeon-7130-usb-uctl";
 150                         reg = <0x11800 0x68000000 0x0 0x100>;
 151                         ranges; /* Direct mapping */
 152                         #address-cells = <2>;
 153                         #size-cells = <2>;
 154                         /* Only 100MHz allowed */
 155                         refclk-frequency = <100000000>;
 156                         /* Only "dlmc_ref_clk0" is supported for 73xx */
 157                         refclk-type-ss = "dlmc_ref_clk0";
 158                         /* Only "dlmc_ref_clk0" is supported for 73xx */
 159                         refclk-type-hs = "dlmc_ref_clk0";
 160
 161                         /*
 162                          * Power is specified by three parts:
 163                          * 1) GPIO handle (must be &gpio)
 164                          * 2) GPIO pin number
 165                          * 3) Active high (0) or active low (1)
 166                          */
 167                         xhci@1680000000000 {
 168                                 compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
 169                                 reg = <0x16800 0x00000000 0x10 0x0>;
 170                                 interrupts = <0x68080 4>; /* UAHC_IMAN, level */
 171                                 maximum-speed = "super-speed";
 172                                 dr_mode = "host";
 173                                 snps,dis_u3_susphy_quirk;
 174                                 snps,dis_u2_susphy_quirk;
 175                                 snps,dis_enblslpm_quirk;
 176                         };
 177                 };
 178
 179                 /* USB 1 */
 180                 usb1: uctl@1180069000000 {
 181                         compatible = "cavium,octeon-7130-usb-uctl";
 182                         reg = <0x11800 0x69000000 0x0 0x100>;
 183                         ranges; /* Direct mapping */
 184                         #address-cells = <2>;
 185                         #size-cells = <2>;
 186                         /* 50MHz, 100MHz and 125MHz allowed */
 187                         refclk-frequency = <100000000>;
 188                         /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
 189                         refclk-type-ss = "dlmc_ref_clk0";
 190                         /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or "pll_ref_clk" */
 191                         refclk-type-hs = "dlmc_ref_clk0";
 192
 193                         /*
 194                          * Power is specified by three parts:
 195                          * 1) GPIO handle (must be &gpio)
 196                          * 2) GPIO pin number
 197                          * 3) Active high (0) or active low (1)
 198                          */
 199                         xhci@1690000000000 {
 200                                 compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
 201                                 reg = <0x16900 0x00000000 0x10 0x0>;
 202                                 interrupts = <0x69080 4>; /* UAHC_IMAN, level */
 203                                 dr_mode = "host";
 204                         };
 205                 };
 206         };
 207 };