1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
7 #include "mscc,jr2.dtsi"
8 #include <dt-bindings/mscc/jr2_data.h>
11 model = "Jaguar2 Cu48 PCB111 Reference Board";
12 compatible = "mscc,jr2-pcb111", "mscc,jr2";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
27 label = "pcb111:green:status";
33 label = "pcb111:red:status";
35 default-state = "off";
47 compatible = "jedec,spi-nor";
48 spi-max-frequency = <18000000>; /* input clock */
54 /* SPIO only use DO, CLK, no inputs */
55 sgpio1_pins: sgpio1-pins {
56 pins = "GPIO_4", "GPIO_5";
63 sgpio-ports = <0xffffffff>;
68 sgpio-ports = <0x001effff>;
73 sgpio-ports = <0xff000000>;
74 gpio-ranges = <&sgpio2 0 0 96>;
80 phy0: ethernet-phy@0 {
83 phy1: ethernet-phy@1 {
86 phy2: ethernet-phy@2 {
89 phy3: ethernet-phy@3 {
92 phy4: ethernet-phy@4 {
95 phy5: ethernet-phy@5 {
98 phy6: ethernet-phy@6 {
101 phy7: ethernet-phy@7 {
104 phy8: ethernet-phy@8 {
107 phy9: ethernet-phy@9 {
110 phy10: ethernet-phy@10 {
113 phy11: ethernet-phy@11 {
116 phy12: ethernet-phy@12 {
119 phy13: ethernet-phy@13 {
122 phy14: ethernet-phy@14 {
125 phy15: ethernet-phy@15 {
128 phy16: ethernet-phy@16 {
131 phy17: ethernet-phy@17 {
134 phy18: ethernet-phy@18 {
137 phy19: ethernet-phy@19 {
140 phy20: ethernet-phy@20 {
143 phy21: ethernet-phy@21 {
146 phy22: ethernet-phy@22 {
149 phy23: ethernet-phy@23 {
157 phy24: ethernet-phy@24 {
160 phy25: ethernet-phy@25 {
163 phy26: ethernet-phy@26 {
166 phy27: ethernet-phy@27 {
169 phy28: ethernet-phy@28 {
172 phy29: ethernet-phy@29 {
175 phy30: ethernet-phy@30 {
178 phy31: ethernet-phy@31 {
181 phy32: ethernet-phy@32 {
184 phy33: ethernet-phy@33 {
187 phy34: ethernet-phy@34 {
190 phy35: ethernet-phy@35 {
193 phy36: ethernet-phy@36 {
196 phy37: ethernet-phy@37 {
199 phy38: ethernet-phy@38 {
202 phy39: ethernet-phy@39 {
205 phy40: ethernet-phy@40 {
208 phy41: ethernet-phy@41 {
211 phy42: ethernet-phy@42 {
214 phy43: ethernet-phy@43 {
217 phy44: ethernet-phy@44 {
220 phy45: ethernet-phy@45 {
223 phy46: ethernet-phy@46 {
226 phy47: ethernet-phy@47 {
235 phy-handle = <&phy0>;
236 phys = <&serdes_hsio 0 SERDES6G(4) PHY_MODE_QSGMII>;
240 phy-handle = <&phy1>;
241 phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>;
245 phy-handle = <&phy2>;
246 phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>;
250 phy-handle = <&phy3>;
251 phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>;
255 phy-handle = <&phy4>;
256 phys = <&serdes_hsio 4 SERDES6G(5) PHY_MODE_QSGMII>;
260 phy-handle = <&phy5>;
261 phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>;
265 phy-handle = <&phy6>;
266 phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>;
270 phy-handle = <&phy7>;
271 phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>;
275 phy-handle = <&phy8>;
276 phys = <&serdes_hsio 8 SERDES6G(6) PHY_MODE_QSGMII>;
280 phy-handle = <&phy9>;
281 phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>;
285 phy-handle = <&phy10>;
286 phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>;
290 phy-handle = <&phy11>;
291 phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>;
295 phy-handle = <&phy12>;
296 phys = <&serdes_hsio 12 SERDES6G(7) PHY_MODE_QSGMII>;
300 phy-handle = <&phy13>;
301 phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
305 phy-handle = <&phy14>;
306 phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
310 phy-handle = <&phy15>;
311 phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
315 phy-handle = <&phy16>;
316 phys = <&serdes_hsio 16 SERDES6G(8) PHY_MODE_QSGMII>;
320 phy-handle = <&phy17>;
321 phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
325 phy-handle = <&phy18>;
326 phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
330 phy-handle = <&phy19>;
331 phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
335 phy-handle = <&phy20>;
336 phys = <&serdes_hsio 20 SERDES6G(9) PHY_MODE_QSGMII>;
340 phy-handle = <&phy21>;
341 phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
345 phy-handle = <&phy22>;
346 phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
350 phy-handle = <&phy23>;
351 phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
355 phy-handle = <&phy24>;
356 phys = <&serdes_hsio 24 SERDES6G(10) PHY_MODE_QSGMII>;
360 phy-handle = <&phy25>;
361 phys = <&serdes_hsio 25 0xff PHY_MODE_QSGMII>;
365 phy-handle = <&phy26>;
366 phys = <&serdes_hsio 26 0xff PHY_MODE_QSGMII>;
370 phy-handle = <&phy27>;
371 phys = <&serdes_hsio 27 0xff PHY_MODE_QSGMII>;
375 phy-handle = <&phy28>;
376 phys = <&serdes_hsio 28 SERDES6G(11) PHY_MODE_QSGMII>;
380 phy-handle = <&phy29>;
381 phys = <&serdes_hsio 29 0xff PHY_MODE_QSGMII>;
385 phy-handle = <&phy30>;
386 phys = <&serdes_hsio 30 0xff PHY_MODE_QSGMII>;
390 phy-handle = <&phy31>;
391 phys = <&serdes_hsio 31 0xff PHY_MODE_QSGMII>;
395 phy-handle = <&phy32>;
396 phys = <&serdes_hsio 32 SERDES6G(12) PHY_MODE_QSGMII>;
400 phy-handle = <&phy33>;
401 phys = <&serdes_hsio 33 0xff PHY_MODE_QSGMII>;
405 phy-handle = <&phy34>;
406 phys = <&serdes_hsio 34 0xff PHY_MODE_QSGMII>;
410 phy-handle = <&phy35>;
411 phys = <&serdes_hsio 35 0xff PHY_MODE_QSGMII>;
415 phy-handle = <&phy36>;
416 phys = <&serdes_hsio 36 SERDES6G(13) PHY_MODE_QSGMII>;
420 phy-handle = <&phy37>;
421 phys = <&serdes_hsio 37 0xff PHY_MODE_QSGMII>;
425 phy-handle = <&phy38>;
426 phys = <&serdes_hsio 38 0xff PHY_MODE_QSGMII>;
430 phy-handle = <&phy39>;
431 phys = <&serdes_hsio 39 0xff PHY_MODE_QSGMII>;
435 phy-handle = <&phy40>;
436 phys = <&serdes_hsio 40 SERDES6G(14) PHY_MODE_QSGMII>;
440 phy-handle = <&phy41>;
441 phys = <&serdes_hsio 41 0xff PHY_MODE_QSGMII>;
445 phy-handle = <&phy42>;
446 phys = <&serdes_hsio 42 0xff PHY_MODE_QSGMII>;
450 phy-handle = <&phy43>;
451 phys = <&serdes_hsio 43 0xff PHY_MODE_QSGMII>;
455 phy-handle = <&phy44>;
456 phys = <&serdes_hsio 44 SERDES6G(15) PHY_MODE_QSGMII>;
460 phy-handle = <&phy45>;
461 phys = <&serdes_hsio 45 0xff PHY_MODE_QSGMII>;
465 phy-handle = <&phy46>;
466 phys = <&serdes_hsio 46 0xff PHY_MODE_QSGMII>;
470 phy-handle = <&phy47>;
471 phys = <&serdes_hsio 47 0xff PHY_MODE_QSGMII>;