2 * Startup Code for MIPS32 CPU-core
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm-offsets.h>
12 #include <asm/regdef.h>
13 #include <asm/mipsregs.h>
15 #ifndef CONFIG_SYS_INIT_SP_ADDR
16 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
17 CONFIG_SYS_INIT_SP_OFFSET)
26 # ifdef CONFIG_SYS_LITTLE_ENDIAN
27 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28 (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
30 # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31 ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
33 # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34 # define STATUS_SET ST0_KX
38 * For the moment disable interrupts, mark the kernel mode and
39 * set ST0_KX so that the CPU does not spit fire when using
42 .macro setup_c0_status set clr
45 or t0, ST0_CU0 | \set | 0x1f | \clr
56 /* U-Boot entry point */
60 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
62 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
63 * access external NOR flashes. If the board boots from NOR flash the
64 * internal BootROM does a blind read at address 0xB0000010 to read the
65 * initial configuration for that EBU in order to access the flash
66 * device with correct parameters. This config option is board-specific.
69 .word CONFIG_SYS_XWAY_EBU_BOOTCFG
72 #if defined(CONFIG_MALTA)
74 * Linux expects the Board ID here.
77 .word 0x00000420 # 0x420 (Malta Board with CoreLV)
81 #if defined(CONFIG_ROM_EXCEPTION_VECTORS)
83 /* TLB refill, 32 bit task */
88 /* XTLB refill, 64 bit task */
93 /* Cache error exception */
98 /* General exception */
103 /* Catch interrupt exceptions */
108 /* EJTAG debug exception */
116 #if __mips_isa_rev >= 6
117 mfc0 t0, CP0_CONFIG, 5
118 and t0, t0, MIPS_CONF5_VP
123 mfc0 t0, CP0_GLOBALNUMBER
126 1: mfc0 t0, CP0_EBASE
127 and t0, t0, EBASE_CPUNUM
129 /* Hang if this isn't the first CPU in the system */
136 /* Clear watch registers */
137 4: MTC0 zero, CP0_WATCHLO
138 mtc0 zero, CP0_WATCHHI
140 /* WP(Watch Pending), SW0/1 should be cleared */
143 setup_c0_status STATUS_SET 0
147 mtc0 zero, CP0_COMPARE
149 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
151 and t0, t0, MIPS_CONF_IMPL
152 or t0, t0, CONF_CM_UNCACHED
158 * Initialize $gp, force pointer sized alignment of bal instruction to
159 * forbid the compiler to put nop's between bal and _gp. This is
160 * required to keep _gp and ra aligned to 8 byte.
169 #ifdef CONFIG_MIPS_CM
170 PTR_LA t9, mips_cm_map
175 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
176 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
177 /* Initialize any external memory */
178 PTR_LA t9, lowlevel_init
183 /* Initialize caches... */
184 PTR_LA t9, mips_cache_reset
188 # ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
189 /* Initialize any external memory */
190 PTR_LA t9, lowlevel_init
196 /* Set up temporary stack */
198 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
199 and sp, t1, t0 # force 16 byte alignment
201 sp, sp, GD_SIZE # reserve space for gd
202 and sp, sp, t0 # force 16 byte alignment
203 move k0, sp # save gd pointer
204 #ifdef CONFIG_SYS_MALLOC_F_LEN
205 li t2, CONFIG_SYS_MALLOC_F_LEN
207 sp, sp, t2 # reserve space for early malloc
208 and sp, sp, t0 # force 16 byte alignment
217 PTR_ADDIU t0, PTRSIZE
219 #ifdef CONFIG_SYS_MALLOC_F_LEN
220 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
223 move a0, zero # a0 <-- boot_flags = 0
224 PTR_LA t9, board_init_f
231 * void relocate_code (addr_sp, gd, addr_moni)
233 * This "function" does not return, instead it continues in RAM
234 * after relocating the monitor code.
238 * a2 = destination address
241 move sp, a0 # set new stack pointer
244 move s0, a1 # save gd in s0
245 move s2, a2 # save destination address in s2
247 PTR_LI t0, CONFIG_SYS_MONITOR_BASE
248 PTR_SUB s1, s2, t0 # s1 <-- relocation offset
250 PTR_LA t2, __image_copy_end
254 * t0 = source address
255 * t1 = target address
256 * t2 = source end address
266 * Now we want to update GOT.
268 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
269 * generated by GNU ld. Skip these reserved entries from relocation.
271 PTR_LA t3, num_got_entries
272 PTR_LA t8, _GLOBAL_OFFSET_TABLE_
273 PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
274 PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
284 PTR_ADDIU t8, PTRSIZE
286 /* Update dynamic relocations */
287 PTR_LA t1, __rel_dyn_start
288 PTR_LA t2, __rel_dyn_end
290 b 2f # skip first reserved entry
291 PTR_ADDIU t1, 2 * PTRSIZE
294 lw t8, -4(t1) # t8 <-- relocation info
296 PTR_LI t3, MIPS_RELOC
297 bne t8, t3, 2f # skip non-MIPS_RELOC entries
300 PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
302 PTR_L t8, 0(t3) # t8 <-- original pointer
303 PTR_ADD t8, s1 # t8 <-- adjusted pointer
305 PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
310 PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
313 * Flush caches to ensure our newly modified instructions are visible
314 * to the instruction cache. We're still running with the old GOT, so
315 * apply the reloc offset to the start address.
317 PTR_LA a0, __text_start
318 PTR_LA a1, __text_end
320 PTR_LA t9, flush_cache
324 PTR_ADD gp, s1 # adjust gp
329 * GOT is now relocated. Thus __bss_start and __bss_end can be
330 * accessed directly via $gp.
332 PTR_LA t1, __bss_start # t1 <-- __bss_start
333 PTR_LA t2, __bss_end # t2 <-- __bss_end
338 PTR_ADDIU t1, PTRSIZE
340 move a0, s0 # a0 <-- gd
342 PTR_LA t9, board_init_r